From: pengfuyuan
Fix spelling typo in comments.
Reported-by: k2ci
Signed-off-by: pengfuyuan
---
drivers/gpu/drm/nouveau/include/nvhw/drf.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvhw/drf.h
b/drivers/gpu/drm/nouveau/include/nvhw
On 15/06/2022 16:27, Mauro Carvalho Chehab wrote:
From: Chris Wilson
As an extension of the current skip TLB invalidations,
check if the device is powered down prior to any engine activity,
as, on such cases, all the TLBs were already invalidated, so an
explicit TLB invalidation is not neede
Use ida_alloc_xxx()/ida_free() instead of
ida_simple_get()/ida_simple_remove().
The latter is deprecated and more verbose.
Signed-off-by: Bo Liu
---
drivers/gpu/drm/drm_connector.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi.
This driver calls drm_detect_hdmi_monitor() to receive the same
information, which is less efficient.
Avoid calling drm_detect_hdmi_monitor() and use drm_display_info.is_hdmi
instead.
Signed-
Hi Dave, Daniel,
Here's this week drm-misc-fixes PR
Maxime
drm-misc-fixes-2022-06-16:
Two fixes for TTM, one for a NULL pointer dereference and one to make sure
the buffer is pinned prior to a bulk move, and a fix for a spurious
compiler warning.
The following changes since commit 477277c7fd43d4
On 15/06/2022 16:27, Mauro Carvalho Chehab wrote:
From: Chris Wilson
Skip all further TLB invalidations once the device is wedged and
had been reset, as, on such cases, it can no longer process instructions
on the GPU and the user no longer has access to the TLB's in each engine.
Fixes: 7938
On 15/06/2022 16:27, Mauro Carvalho Chehab wrote:
From: Chris Wilson
Don't flush TLBs when the buffer is only used in the GGTT under full
control of the kernel, as there's no risk of of concurrent access
and stale access from prefetch.
We only need to invalidate the TLB if they are accessibl
On 15/06/2022 16:27, Mauro Carvalho Chehab wrote:
From: Chris Wilson
Don't allow two engines to be reset in parallel, as they would both
try to select a reset bit (and send requests to common registers)
and wait on that register, at the same time. Serialize control of
the reset requests/acks
Quoting Prashant Malani (2022-06-15 10:20:20)
>
> .../display/bridge/analogix,anx7625.yaml | 64 +++
> 1 file changed, 64 insertions(+)
Can this file get a link to the product brief[1]? It helps to quickly
find the block diagram.
>
> diff --git
> a/Documentation/devicetree/
Quoting Dmitry Baryshkov (2022-06-09 05:23:43)
> DB820c makes use of core-vcc-supply and core-vdda-supply, however the
> driver code doesn't support these regulators. Enable them for HDMI on
> 8996 platform.
>
> Fixes: 0afbe59edd3f ("drm/msm/hdmi: Add basic HDMI support for msm8996")
> Signed-off-b
On Tue, 14 Jun 2022 23:55:37 -0500, Samuel Holland wrote:
> This series prepares the sun8i HDMI PHY driver for supporting the new
> custom PHY in the Allwinner D1 SoC. No functional change intended here.
>
> This series was tested on D1, H3, and H6.
>
> Changes in v2:
> - Move error handling ins
Hi Dave & Daniel -
drm-intel-fixes-2022-06-16:
drm/i915 fixes for v5.19-rc3:
- Fix page fault on error state read
- Fix memory leaks in per-gt sysfs
- Fix multiple fence handling
- Remove accidental static from a local variable
BR,
Jani.
The following changes since commit b13baccc3850ca8b8cccb
Hi,
On Wed, Jun 15, 2022 at 12:42:53AM -0500, Samuel Holland wrote:
> If the component driver fails to bind, or is unbound, the driver data
> for the top-level platform device points to a freed drm_device. If the
> system is then suspended, the driver passes this dangling pointer to
> drm_mode_con
On Tue, 14 Jun 2022 02:31:00 -0500, Samuel Holland wrote:
> commit 6de79dd3a920 ("drm/bridge: display-connector: add ddc-en gpio
> support") added a consumer for this GPIO in the HDMI connector device.
> This new consumer conflicts with the pre-existing GPIO consumer in the
> sun8i HDMI controller
On Wed, 15 Jun 2022 00:42:53 -0500, Samuel Holland wrote:
> If the component driver fails to bind, or is unbound, the driver data
> for the top-level platform device points to a freed drm_device. If the
> system is then suspended, the driver passes this dangling pointer to
> drm_mode_config_helper_
As pointed several times in the discussions, start moving resource
allocation from component bind to the probe function. This simplifies
boot process, as the component will not be registered until all
resources (clocks, regulators, IRQ, etc.) are not registered.
Dmitry Baryshkov (3):
drm/msm/hdm
All MSM HDMI devices use "core_physical" and "qfprom_physical" names for
register areas. Drop them from the platform config.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 9 +++--
drivers/gpu/drm/msm/hdmi/hdmi.h | 3 ---
2 files changed, 3 insertions(+), 9 deletions(-
Use devm_pm_runtime_enable() to enable runtime PM. This way its effect
will be reverted on device unbind/destruction.
Fixes: 6ed9ed484d04 ("drm/msm/hdmi: Set up runtime PM for HDMI")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 del
Rather than having all resource allocation happen in the _bind function
(resulting in possible EPROBE_DEFER returns and component bind/unbind
cycles) allocate and check all resources in _probe function. While we
are at it, use platform_get_irq() to get the IRQ rather than going
through the irq_of_p
On 16/06/2022 05:34, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-05-04 17:16:04)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index a37a3bbc04d9..98ae0036ab57 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -262,6 +263,46 @@
This series started from the applied and then reverted [2] patch by
Robin Murphy [1]. After the MDSS rework [3] has landed it is now
possible to reapply the extended version of the original patch. While we
are at it, also rework the IOMMU init code for DPU and MDP5 drivers.
For MDP5 this moves iom
Move iommu_domain_alloc() in front of adress space/IOMMU initialization.
This allows us to drop final bits of struct mdp5_cfg_platform which
remained from the pre-DT days.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 16 --
MDP5 and DPU drivers have the same piece of code now to initialize
IOMMU and GEM address space. Move it to the msm_drv.c
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 32 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 33
driv
Follow the lead of MDP5 driver and check both DPU and MDSS devices for
the IOMMU specifiers.
Historically DPU devices had IOMMU specified in the MDSS device tree
node, but as some of MDP5 devices are being converted to the supported
by the DPU driver, the driver should adapt and check both devices
Change msm_kms_init_aspace() to use generic function
device_iommu_mapped() instead of the fwnode-specific interface
dev_iommu_fwspec_get(). While we are at it, stop referencing
platform_bus_type directly and use the bus of the IOMMU device.
Suggested-by: Robin Murphy
Reviewed-by: Robin Murphy
Si
Even if some IOMMU has registered itself on the platform "bus", that
doesn't necessarily mean it provides translation for the device we
care about. Replace iommu_present() with a more appropriate check.
On Qualcomm platforms the IOMMU can be specified either for the MDP/DPU
device or for its paren
On 15/06/2022 19:24, Rob Clark wrote:
From: Rob Clark
And while we are at it, let's start the fence counter close to the
rollover point so that if issues slip in, they are more obvious.
Signed-off-by: Rob Clark
Should it also have
Fixes: fde5de6cb461 ("drm/msm: move fence code to it's own
Quoting Rob Clark (2022-06-13 13:50:32)
> diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
> index d608339c1643..432032ad4aed 100644
> --- a/drivers/gpu/drm/msm/msm_gem.h
> +++ b/drivers/gpu/drm/msm/msm_gem.h
> @@ -229,7 +229,19 @@ msm_gem_unlock(struct drm_gem_object *obj
On 16/06/2022 02:23, Abhinav Kumar wrote:
After [1] was merged to IGT, we use either the first supported
mode in the list OR the preferred mode to determine the primary
plane to use for the sub-test due to the IGT API [2].
Since writeback does not set any preferred mode, this was
selecting 4k as
On 16/06/2022 00:22, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf and wb resources to dpu_encoder_setup_display()
so that we can utilize the hw caps even during
Hi Dave,
On Tue, Jun 14, 2022 at 05:47:28PM +0100, Dave Stevenson wrote:
> Hi Maxime.
>
> On Fri, 10 Jun 2022 at 10:30, Maxime Ripard wrote:
> >
> > Adding a device-managed action will make the error path easier, so let's
> > create one to disable our clock.
>
> The DPI block has two clocks (co
On Thu, Jun 16, 2022 at 06:23:26AM +1000, Dave Airlie wrote:
> On Wed, 15 Jun 2022 at 20:53, Greg KH wrote:
> >
> > On Wed, Jun 15, 2022 at 06:48:33PM +0800, heliang wrote:
> > > In tegra_uart_init(), of_find_matching_node() will return a node
> > > pointer with refcount incremented. We should use
On Wed, Jun 15, 2022 at 10:30:47PM +0200, Daniel Vetter wrote:
> On Wed, 15 Jun 2022 at 22:23, Dave Airlie wrote:
> >
> > On Wed, 15 Jun 2022 at 20:53, Greg KH wrote:
> > >
> > > On Wed, Jun 15, 2022 at 06:48:33PM +0800, heliang wrote:
> > > > In tegra_uart_init(), of_find_matching_node() will re
On 06/10, Maxime Ripard wrote:
> When doing an asynchronous page flip (PAGE_FLIP ioctl with the
> DRM_MODE_PAGE_FLIP_ASYNC flag set), the current code waits for the
> possible GPU buffer being rendered through a call to
> vc4_queue_seqno_cb().
>
> On the BCM2835-37, the GPU driver is part of the v
Drop empty callbacks msm_hdmi_bridge_enable() and
msm_hdmi_bridge_disable().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
There might be a chain of bridges attached to the HDMI node
(including but not limited to the display-connector bridge). Add support
for attaching them right to the HDMI bridge chain.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 14 ++
drivers/gpu/drm/msm/hdm
At 2022-06-16 16:43:43, "Greg KH" wrote:
>On Wed, Jun 15, 2022 at 10:30:47PM +0200, Daniel Vetter wrote:
>> On Wed, 15 Jun 2022 at 22:23, Dave Airlie wrote:
>> >
>> > On Wed, 15 Jun 2022 at 20:53, Greg KH wrote:
>> > >
>> > > On Wed, Jun 15, 2022 at 06:48:33PM +0800, heliang wrote:
>> > > > In
On 15/06/2022 16:20, Niranjana Vishwanathapura wrote:
On Wed, Jun 15, 2022 at 08:22:23AM +0100, Tvrtko Ursulin wrote:
On 14/06/2022 17:42, Niranjana Vishwanathapura wrote:
On Tue, Jun 14, 2022 at 05:07:37PM +0100, Tvrtko Ursulin wrote:
On 14/06/2022 17:02, Tvrtko Ursulin wrote:
On 14/06/
On Thu, Jun 16, 2022 at 12:42 AM Stephen Boyd wrote:
>
> Quoting Prashant Malani (2022-06-15 10:20:20)
> >
> > .../display/bridge/analogix,anx7625.yaml | 64 +++
> > 1 file changed, 64 insertions(+)
>
> Can this file get a link to the product brief[1]? It helps to quickly
> f
Il 15/06/22 19:20, Prashant Malani ha scritto:
This series introduces a binding for Type-C data lane switches. These
control the routing and operating modes of USB Type-C data lanes based
on the PD messaging from the Type-C port driver regarding connected
peripherals.
The first patch introduces
MDP4 uses custom code to handle LVDS panel. It predates handling
EPROBE_DEFER, it tries to work when the panel device is not available,
etc. Switch MDP4 LCDC code to use drm_panel_bridge/drm_bridge_connector
to follow contemporary DRM practices.
Note, this code has been compile-tested only. Testin
We can check the LCDC clock directly from the LCDC encoder driver, so
remove it from the LVDS connector.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 1 -
.../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 26 ++-
.../drm/msm/disp/mdp4/mdp4_lv
LVDS support in MDP4 driver makes use of drm_connector directly. However
LCDC encoder and LVDS connector are wrappers around drm_panel. Switch
them to use drm_panel_bridge/drm_bridge_connector. This allows using
standard interface for the drm_panel and also inserting additional
bridges between enco
The print function dev_err() is redundant because platform_get_irq()
already prints an error.
This was found by coccicheck:
./drivers/usb/gadget/udc/aspeed_udc.c:1546:2-9: line 1546 is redundant because
platform_get_irq() already prints an error.
Signed-off-by: Jiapeng Chong
---
drivers/usb/g
On Fri, 10 Jun 2022 13:51:35 +0200, Maxime Ripard wrote:
> Here's a series that fixes a significant issue we missed when adding support
> for the BCM2711 / RaspberryPi4 in the vc4 driver.
>
> Indeed, before the introduction of the BCM2711 support, the GPU was fairly
> intertwined with the display
On Wed, Jun 15, 2022 at 12:34:46PM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 15.06.22 um 10:32 schrieb Maxime Ripard:
> [...]
> > > See, helpers should be useful to many drivers. If we add them, we also
> > > add a
> > > resources and maintenance overhead to our libraries. And right now, these
At 2022-06-16 17:20:24, conor.doo...@microchip.com wrote:
>On 16/06/2022 09:52, Liang He wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is safe
>>
>> At 2022-06-16 16:43:43, "Greg KH" wrote:
>>> On Wed, Jun 15, 2022 at 10:30:47PM +0200, Daniel V
Hi Dave,
On Tue, Jun 14, 2022 at 04:57:45PM +0100, Dave Stevenson wrote:
> On Fri, 10 Jun 2022 at 10:30, Maxime Ripard wrote:
> >
> > All the CRTCs, including the TXP, have a debugfs file and name so we can
> > consolidate it into vc4_crtc_data.
> >
> > Signed-off-by: Maxime Ripard
>
> Reviewed
On Wed, Jun 15, 2022 at 05:09:15PM +0100, Robin Murphy wrote:
> The Arm Juno board EDK2 port has provided an EFI GOP display via HDLCD0
> for some time now, which works nicely as an early framebuffer. However,
> once the HDLCD driver probes and takes over the hardware, it should
> take over the log
On Thu, 16 Jun 2022 at 10:41, Maxime Ripard wrote:
>
> Hi Dave,
>
> On Tue, Jun 14, 2022 at 04:57:45PM +0100, Dave Stevenson wrote:
> > On Fri, 10 Jun 2022 at 10:30, Maxime Ripard wrote:
> > >
> > > All the CRTCs, including the TXP, have a debugfs file and name so we can
> > > consolidate it into
On Thu, 16 Jun 2022 at 09:38, Maxime Ripard wrote:
>
> Hi Dave,
>
> On Tue, Jun 14, 2022 at 05:47:28PM +0100, Dave Stevenson wrote:
> > Hi Maxime.
> >
> > On Fri, 10 Jun 2022 at 10:30, Maxime Ripard wrote:
> > >
> > > Adding a device-managed action will make the error path easier, so let's
> > >
> The print function dev_err() is redundant because platform_get_irq() already
> prints an error.
>
> This was found by coccicheck:
>
> ./drivers/usb/gadget/udc/aspeed_udc.c:1546:2-9: line 1546 is redundant
> because platform_get_irq() already prints an error.
>
> Signed-off-by: Jiapeng Chong
Hello Robin,
On 6/15/22 18:09, Robin Murphy wrote:
> The Arm Juno board EDK2 port has provided an EFI GOP display via HDLCD0
> for some time now, which works nicely as an early framebuffer. However,
> once the HDLCD driver probes and takes over the hardware, it should
> take over the logical frame
On Wed, Jun 15, 2022 at 05:11:09PM +0100, Robin Murphy wrote:
> Since we no longer need to conform to the structure of the various DRM
> IRQ callbacks, we can streamline the code by consolidating the piecemeal
> functions and passing around our private data structure directly. We're
> also a platfo
On 5/25/22 20:43, Matthew Auld wrote:
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture interactions, including no longer needing
NEEDS_CPU_ACCESS for objects marked for capture. (Tho
On Sat, Jun 11, 2022 at 10:14:07PM +0800, Liu Ying wrote:
> Patch 1/14 and 2/14 add bus formats used by pixel combiner.
Thanks!
For these:
Acked-by: Sakari Ailus
--
Sakari Ailus
This series add DG2 D3Cold VRAM_SR support.
TODO: GuC Interface state save/restore on VRAM_SR entry/exit.
Anshuman Gupta (8):
drm/i915/dgfx: OpRegion VRAM Self Refresh Support
drm/i915/dg1: OpRegion PCON DG1 MBD config support
drm/i915/dg2: Add DG2_NB_MBD subplatform
drm/i915/dg2: DG2 MBD
Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
opportunistic S0ix system wide suspend flow as well.
Without VRSR enablement i915 has to evict the lmem objects to
system memory. Depending on some heuristics driver
DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
configs. MBD config requires HOST BIOS GPIO toggling support
in order to enable/disable VRAM SR using ACPI OpRegion.
i915 requires to check OpRegion PCON MBD Config bits to
discover whether Gfx Card is MBD config before enabling
V
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.
Cc: Matt Roper
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_device_info.c | 21 +++
Add has_lmem_sr platform specific flag to know,
whether platform has VRAM self refresh support.
As of now both DG1 and DG2 client platforms supports VRAM self refresh
with D3Cold but let it enable first on DG2 as primary lead platform
for D3Cold support. Let it get enable on DG1 once this feature
i
Add DG2 Motherboard Down Config check support.
v2:
- Don't use pciid to check DG2 MBD. [Jani]
BSpec: 44477
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 9 +
2 files changed, 11 i
Setup VRAM Self Refresh with D3COLD state.
VRAM Self Refresh will retain the context of VRAM, driver
need to save any corresponding hardware state that needs
to be restore on D3COLD exit, example PCI state.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915
Intel Client DGFX card supports D3Cold with two option.
D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
i915 requires to evict the lmem objects to smem in order to
support D3Cold-Off, which increases i915 the suspend/resume
latency. Enabling VRAM Self Refresh feature optimize the
latency with addi
Add d3cold_sr_lmem_threshold modparam to choose between
d3cold-off zero watt and d3cold-VRAM Self Refresh.
i915 requires to evict the lmem objects to smem in order to
support d3cold-Off.
If gfx root port is not capable of sending PME from d3cold
then i915 don't need to program d3cold-off/d3cold-vr
From: Tvrtko Ursulin
Store a pointer to respective local memory region in intel_gt so it can be
used when memory local to a GT needs to be allocated.
Cc: Andi Shyti
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm
On 16/06/2022 13:01, Anshuman Gupta wrote:
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.
Cc: Matt Roper
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Setup VRAM Self Refresh with D3COLD state.
> VRAM Self Refresh will retain the context of VRAM, driver
> need to save any corresponding hardware state that needs
> to be restore on D3COLD exit, example PCI state.
>
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
> DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
> opportunistic S0ix system wide suspend flow as well.
>
> Without VRSR enablement i915 has to evict the lmem objects t
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
> configs. MBD config requires HOST BIOS GPIO toggling support
> in order to enable/disable VRAM SR using ACPI OpRegion.
>
> i915 requires to check OpRegion PCON MBD Config bits to
> di
On Mon, Jun 13, 2022 at 4:57 PM Rob Herring wrote:
> 'arm,rtsm-display' is a panel for Arm, Ltd. virtual platforms (e.g. FVP).
> The binding has been in use for a long time, but was never documented.
>
> Some users and an example have a 'panel-dpi' compatible, but that's not
> needed without a 'p
On Thu, Jun 16, 2022 at 1:28 AM Stephen Boyd wrote:
>
> Quoting Rob Clark (2022-06-13 13:50:32)
> > diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
> > index d608339c1643..432032ad4aed 100644
> > --- a/drivers/gpu/drm/msm/msm_gem.h
> > +++ b/drivers/gpu/drm/msm/msm_gem.h
On Thu, Jun 16, 2022 at 1:27 AM Dmitry Baryshkov
wrote:
>
> On 15/06/2022 19:24, Rob Clark wrote:
> > From: Rob Clark
> >
> > And while we are at it, let's start the fence counter close to the
> > rollover point so that if issues slip in, they are more obvious.
> >
> > Signed-off-by: Rob Clark
>
On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
> On 16/06/2022 13:01, Anshuman Gupta wrote:
>> DG2 NB SKU need to distinguish between MBD and AIC to probe
>> the VRAM Self Refresh feature support. Adding those sub platform
>> accordingly.
>>
>> Cc: Matt Roper
>> Signed-off-by: Anshuman Gupta
>> ---
MIPI DSI TX subsystem allows you to quickly create systems based on the
MIPI protocol. It interfaces between the video processing subsystems and
MIPI-based displays. An internal high-speed physical layer design, D-PHY,
is provided to allow direct connection to display peripherals.
The subsystem co
This patch adds dt binding for Xilinx DSI-TX subsystem.
The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem
implements the Mobile Industry Processor Interface (MIPI) based display
interface. It supports the interface with the programmable logic (FPGA).
Signed-off-by: Venkateshwar
The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video
data from AXI-4 stream interface.
It supports upto 4 lanes, optional register interface for the DPHY
and multiple RGB color formats.
This is a MIPI-DSI host driver and provides DSI bus for panels.
This driver also helps to communica
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Add d3cold_sr_lmem_threshold modparam to choose between
> d3cold-off zero watt and d3cold-VRAM Self Refresh.
> i915 requires to evict the lmem objects to smem in order to
> support d3cold-Off.
>
> If gfx root port is not capable of sending PME from d3co
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> From: Tvrtko Ursulin
>
> Store a pointer to respective local memory region in intel_gt so it can be
> used when memory local to a GT needs to be allocated.
>
> Cc: Andi Shyti
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Anshuman Gupta
> ---
> d
On Thu, 16 Jun 2022, Anshuman Gupta wrote:
> Intel Client DGFX card supports D3Cold with two option.
> D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
>
> i915 requires to evict the lmem objects to smem in order to
> support D3Cold-Off, which increases i915 the suspend/resume
> latency. Enabling V
On 16/06/2022 15:15, Jani Nikula wrote:
On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
On 16/06/2022 13:01, Anshuman Gupta wrote:
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.
Cc: Matt Roper
Signed-off-
On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
> On 16/06/2022 15:15, Jani Nikula wrote:
>> On Thu, 16 Jun 2022, Tvrtko Ursulin wrote:
>>> On 16/06/2022 13:01, Anshuman Gupta wrote:
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding tho
Hi,
On Mon, Apr 25, 2022 at 2:07 PM Douglas Anderson wrote:
>
> We're supposed to list the supplies in the dt bindings but there are
> none in the eDP PHY bindings.
>
> Looking at the driver in Linux, I can see that there seem to be two
> relevant supplies: "vdda-phy" and "vdda-pll". Let's add th
On 6/16/22 07:17, Venkateshwar Rao Gannavarapu wrote:
> diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig
> index f9cf93c..a75bd76 100644
> --- a/drivers/gpu/drm/xlnx/Kconfig
> +++ b/drivers/gpu/drm/xlnx/Kconfig
> @@ -1,3 +1,15 @@
> +config DRM_XLNX_DSI
> + tristate "X
On 6/16/2022 1:36 AM, Dmitry Baryshkov wrote:
On 16/06/2022 02:23, Abhinav Kumar wrote:
After [1] was merged to IGT, we use either the first supported
mode in the list OR the preferred mode to determine the primary
plane to use for the sub-test due to the IGT API [2].
Since writeback does no
On 5/19/22 06:05, Daniel Vetter wrote:
> On Mon, Apr 25, 2022 at 11:46:53AM -0700, Randy Dunlap wrote:
>>
>>
>> On 4/5/22 08:15, Borislav Petkov wrote:
>>> From: Borislav Petkov
>>>
>>> Fix:
>>>
>>> drivers/gpu/drm/r128/r128_cce.c: In function ‘r128_do_init_cce’:
>>> drivers/gpu/drm/r128/r1
On 6/16/22 16:55, David Gow wrote:
> On Wed, Jun 15, 2022 at 9:59 PM Maíra Canal wrote:
>>
>> KUnit unifies the test structure and provides helper tools that simplify
>> the development of tests. The basic use case allows running tests as regular
>> processes, which makes it easier to run unit tes
This started with work on the removal of backlight_properties'
deprecated fb_blank field, much of which can be taken care of by using
helper functions provided by backlight.h instead of directly accessing
fields in backlight_properties. This patch series doesn't involve
fb_blank, but it still seems
1) force link training for display resolution change
2) remove pixel_rate from struct dp_ctrl
Kuogee Hsieh (2):
drm/msm/dp: force link training for display resolution change
drm/msm/dp: clean up pixel_rate from dp_ctrl.c
drivers/gpu/drm/msm/dp/dp_ctrl.c| 147 -
Display resolution change is implemented through drm modeset. Older
modeset (resolution) has to be disabled first before newer modeset
(resolution) can be enabled. Display disable will turn off both
pixel clock and main link clock so that main link have to be
re-trained during display enable to hav
dp_ctrl keep an local cache of pixel_rate which increase confusing
in regrading how pixel_rate being used. This patch refer pixel_rate
directly from dp_panel to eliminate unnecessary pixel_rate variable
from struct dp_ctrl.
Changes in v8:
-- add this patch to remove pixel_rate from dp_ctrl
Signed
On Fri, 10 Jun 2022 13:15:10 +0200, Bastian Krause wrote:
> Add Ampire AM-800600P5TMQW-TB8H 8" TFT LCD panel compatible string.
>
> Signed-off-by: Bastian Krause
> ---
> .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob He
backlight_properties.fb_blank is deprecated. The states it represents
are handled by other properties; but instead of accessing those
properties directly, drivers should use the helpers provided by
backlight.h.
This will ultimately allow fb_blank to be removed.
Changes since v1:
- remove the last
Instead of retrieving the backlight brightness in struct
backlight_properties manually, and then checking whether the backlight
should be on at all, use backlight_get_brightness() which does all
this and insulates this from future changes.
Instead of setting the power state by manually updating fi
Instead of retrieving the backlight brightness in struct
backlight_properties manually, and then checking whether the backlight
should be on at all, use backlight_get_brightness() which does all
this and insulates this from future changes.
Instead of manually checking the power state in struct
bac
backlight_properties.fb_blank is deprecated. The states it represents
are handled by other properties; but instead of accessing those
properties directly, drivers should use the helpers provided by
backlight.h.
Instead of retrieving the backlight brightness in struct
backlight_properties manually,
Hi!
Javier Martinez Canillas wrote:
> Before merging this, could you please reach the folks working on [0] ?
> I think that would be good to have some consistency with regard to KUnit
> tests from the start to avoid future refactorings. For instance, you are
> adding the tests under a `kunit` sub-
https://bugzilla.kernel.org/show_bug.cgi?id=216119
Harald Judt (h.j...@gmx.at) changed:
What|Removed |Added
Status|RESOLVED|REOPENED
Resolution
Add FourCCs for two missing permutations of the packed YUV 4:4:4 color
components, namely AVUY and XVUY.
These formats are needed by the NXP i.MX8 ISI. While the ISI is
supported by a V4L2 device (corresponding formats have been submitted to
V4L2), it is handled in userspace by libcamera, which us
On Wed, Jun 15, 2022 at 04:25:34AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/dp/mst: Read the extended DPCD capabilities during system resume
> URL : https://patchwork.freedesktop.org/series/105102/
> State : failure
Thanks for the reviews, pushed the patch to drm-misc-next
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