Am 06.06.22 um 13:00 schrieb Bas Nieuwenhuizen:
On Mon, Jun 6, 2022 at 12:35 PM Christian König
wrote:
[SNIP]
That part won't work at all and would cause additional synchronization
problems.
First of all for implicit synced CS we should use READ, not BOOKKEEP.
Because BOOKKEEP would incorrectl
Hi Bas,
sorry I totally missed your reply. Just tried to answer your original
questions.
Regards,
Christian.
Am 15.06.22 um 02:40 schrieb Bas Nieuwenhuizen:
Hi Christian,
Friendly ping on the comments here. Are you okay with me re-spinning
the series with a fixed patch 1 or do we need furth
On 14/06/2022 17:42, Niranjana Vishwanathapura wrote:
On Tue, Jun 14, 2022 at 05:07:37PM +0100, Tvrtko Ursulin wrote:
On 14/06/2022 17:02, Tvrtko Ursulin wrote:
On 14/06/2022 16:43, Niranjana Vishwanathapura wrote:
On Tue, Jun 14, 2022 at 08:16:41AM +0100, Tvrtko Ursulin wrote:
On 14/06/
Hi
Am 14.06.22 um 14:09 schrieb Maxime Ripard:
On Tue, Jun 14, 2022 at 01:47:28PM +0200, Thomas Zimmermann wrote:
Am 14.06.22 um 11:04 schrieb Maxime Ripard:
On Tue, Jun 14, 2022 at 10:29:20AM +0200, Thomas Zimmermann wrote:
Am 14.06.22 um 09:37 schrieb Maxime Ripard:
Hi Thomas,
On Mon, Jun
Hi
Am 14.06.22 um 23:06 schrieb Robin Murphy:
On 2022-06-14 14:48, Thomas Zimmermann wrote:
Hi
Am 14.06.22 um 15:04 schrieb Robin Murphy:
The Arm Juno board EDK2 port has provided an EFI GOP display via HDLCD0
for some time now, which works nicely as an early framebuffer. However,
once the HD
On 6/15/22 09:39, Thomas Zimmermann wrote:
> Hi
>
> Am 14.06.22 um 23:06 schrieb Robin Murphy:
>> On 2022-06-14 14:48, Thomas Zimmermann wrote:
>>> Hi
>>>
>>> Am 14.06.22 um 15:04 schrieb Robin Murphy:
The Arm Juno board EDK2 port has provided an EFI GOP display via HDLCD0
for some time
Am 15.06.22 um 09:50 schrieb Javier Martinez Canillas:
[...]
Historically, most drivers call this function very early. But for error
recovery it would be better to do it as late as possible. Ideally,
drivers would first initialize their DRM software state, then kickout
the generic driver, and
On 6/15/22 09:53, Thomas Zimmermann wrote:
>
>
> Am 15.06.22 um 09:50 schrieb Javier Martinez Canillas:
> [...]
>>> Historically, most drivers call this function very early. But for error
>>> recovery it would be better to do it as late as possible. Ideally,
>>> drivers would first initialize th
On Wed, Jun 15, 2022 at 09:22:55AM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 14.06.22 um 14:09 schrieb Maxime Ripard:
> > On Tue, Jun 14, 2022 at 01:47:28PM +0200, Thomas Zimmermann wrote:
> > > Am 14.06.22 um 11:04 schrieb Maxime Ripard:
> > > > On Tue, Jun 14, 2022 at 10:29:20AM +0200, Thomas
Il 14/06/22 18:57, Prashant Malani ha scritto:
On Tue, Jun 14, 2022 at 1:18 AM AngeloGioacchino Del Regno
wrote:
Il 09/06/22 20:09, Prashant Malani ha scritto:
When the DT node has "switches" available, register a Type-C mode-switch
for each listed "switch". This allows the driver to receive
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang wrote:
>
> Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
> helper method. This way, we can make it easier to get CRCs from other HW
> blocks by adding other get_crc helper methods.
>
> Changes since V1:
> - Moved common bitmasks
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang wrote:
>
> Add support for setting MISR registers within the interface
>
> Changes since V1:
> - Replaced dpu_hw_intf collect_misr and setup_misr implementations with
> calls to dpu_hw_utils helper methods
>
> Signed-off-by: Jessica Zhang
Reviewed-by
https://bugzilla.kernel.org/show_bug.cgi?id=216092
RockT (tr...@gmx.de) changed:
What|Removed |Added
CC||tr...@gmx.de
--- Comment #1 from R
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang wrote:
>
> Add support for writing CRC values for the interface block to
> the debugfs by calling the necessary MISR setup/collect methods.
>
> Changes since V1:
> - Set values_cnt to only include phys with backing hw_intf
> - Loop over all drm_encs conn
On 08/06/2022 21:45, Niranjana Vishwanathapura wrote:
On Wed, Jun 08, 2022 at 09:54:24AM +0100, Tvrtko Ursulin wrote:
On 08/06/2022 09:45, Lionel Landwerlin wrote:
On 08/06/2022 11:36, Tvrtko Ursulin wrote:
On 08/06/2022 07:40, Lionel Landwerlin wrote:
On 03/06/2022 09:53, Niranjana Vishw
On Wed, Jun 15, 2022 at 10:00:52AM +0200, Javier Martinez Canillas wrote:
> On 6/15/22 09:53, Thomas Zimmermann wrote:
> >
> >
> > Am 15.06.22 um 09:50 schrieb Javier Martinez Canillas:
> > [...]
> >>> Historically, most drivers call this function very early. But for error
> >>> recovery it would
On Wed, 15 Jun 2022 at 02:01, Emma Anholt wrote:
>
> This is an SMMU for the adreno gpu, and adding this compatible lets
> the driver use per-fd page tables, which are required for security
> between GPU clients.
>
> Signed-off-by: Emma Anholt
> ---
>
> Tested with a full deqp-vk run on RB5, whic
Hi
Am 15.06.22 um 10:32 schrieb Maxime Ripard:
[...]
See, helpers should be useful to many drivers. If we add them, we also add a
resources and maintenance overhead to our libraries. And right now, these
new functions appear to work around the design of the vc4 driver's data
structures. If you
On Wed, 15 Jun 2022 at 02:01, Emma Anholt wrote:
>
> Required for turning on per-process page tables for the GPU.
>
> Signed-off-by: Emma Anholt
Reviewed-by: Dmitry Baryshkov
> ---
>
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/
On Wed, Jun 15, 2022 at 06:48:33PM +0800, heliang wrote:
> In tegra_uart_init(), of_find_matching_node() will return a node
> pointer with refcount incremented. We should use of_node_put()
> when it is not used anymore.
>
> Signed-off-by: heliang
We need a real name please, one you sign document
On Wed, 15 Jun 2022 at 00:54, Douglas Anderson wrote:
>
> Let's add support for being able to read the HPD pin even if it's
> hooked directly to the controller. This will let us take away the
> waiting in the AUX transfer functions of the eDP controller drivers.
>
> Signed-off-by: Douglas Anderson
On 21/02/2022 17:51, Vinod Polimera wrote:
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Changes in v2:
- As per review suggestion by D
Make dp_connector_mode_valid() return precise MODE_CLOCK_HIGH rather
than generic MODE_BAD in case the mode clock is higher than
DP_MAX_PIXEL_CLK_KHZ (675 MHz).
Reviewed-by: Kuogee Hsieh
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
1
On 01/05/2022 18:12, Dmitry Baryshkov wrote:
The commit 0f40ba48de3b ("drm/msm/dsi: Pass DSC params to drm_panel")
added a pointer to the DSC data to the struct drm_panel. However DSC
support is not limited to the DSI panels. MIPI DSI bridges can also
consume DSC command streams. Thus add struct
On 03/06/2022 12:42, Vinod Polimera wrote:
During probe defer, drm device is not initialized and an external
trigger to shutdown is trying to clean up drm device leading to crash.
Add checks to avoid drm device cleanup in such cases.
BUG: unable to handle kernel NULL pointer dereference at virtu
On 03/06/2022 12:42, Vinod Polimera wrote:
During probe defer, drm device is not initialized and an external
trigger to shutdown is trying to clean up drm device leading to crash.
Add checks to avoid drm device cleanup in such cases.
BUG: unable to handle kernel NULL pointer dereference at virtu
On 03/06/2022 23:09, Kuogee Hsieh wrote:
Use quic id instead of codeaurora id in maintainers list
for display devicetree bindings.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
We can pick it through the msm/ tree, if no one objects.
---
Documentation/devicetree/bindings/dis
On 11/06/2022 01:02, Luca Weiss wrote:
From: Vladimir Lypak
There is currently two function for performing reset: dsi_sw_reset and
dsi_sw_reset_restore. Only difference betwean those is that latter one
assumes that DSI controller is enabled. In contrary former one assumes
that controller is dis
Replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi for more
efficiency
Tested on "Oland [Radeon HD 8570 / R7 240/340 OEM]" & "Caicos [R5 230]"
Signed-off-by: hongao
---
drivers/gpu/drm/radeon/atombios_encoders.c | 6 +++---
drivers/gpu/drm/radeon/radeon_connectors.c | 12 ++---
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf and wb resources to dpu_encoder_setup_display()
so that we can utilize the hw caps even during
On 14/06/2022 22:32, Abhinav Kumar wrote:
Writeback block for sm8250 was using the default maxlinewidth
of 2048. But this is not right as it supports upto 4096.
This should have no effect on most resolutions as we are
still limiting upto maxlinewidth of SSPP for adding the modes.
Fix the maxlin
On 14/06/2022 22:32, Abhinav Kumar wrote:
Remove the hard-coded limit for writeback and lets start using
the one from catalog instead.
Fixes: d7d0e73f7de3 ("introduce the dpu_encoder_phys_* for writeback")
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/ms
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf and wb resources to dpu_encoder_setup_display()
so that we can utilize the hw caps even during
On 09/06/2022 20:42, Rob Clark wrote:
From: Rob Clark
Similar to AMD commit
874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the
infrastructure added in previous patches, we add basic client info
and GPU engine utilisation for msm.
Example output:
# cat /proc/`pgrep glm
On 09/06/2022 20:42, Rob Clark wrote:
From: Rob Clark
The DEFINE_DRM_GEM_FOPS() helper is a bit limiting if a driver wants to
provide additional file ops, like show_fdinfo().
v2: Split out DRM_GEM_FOPS instead of making DEFINE_DRM_GEM_FOPS
varardic
v3: nits
Signed-off-by: Rob Clark
Acke
On 26/04/2022 16:21, Wan Jiabing wrote:
Fix following coccicheck warning:
drivers/gpu/drm/msm/msm_gpu_devfreq.c:72:1-7: WARNING: do_div() does a 64-by-32
division, please consider using div64_ul instead.
Use div64_ul instead of do_div to avoid a possible truncation.
Signed-off-by: Wan Jiabing
On 09/06/2022 18:42, Rob Clark wrote:
From: Rob Clark
Similar to AMD commit
874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the
infrastructure added in previous patches, we add basic client info
and GPU engine utilisation for msm.
Example output:
# cat /proc/`pgrep g
On 11/04/2022 23:47, Sean Paul wrote:
From: Sean Paul
Rebased set from November. Fixed a nit from Stephen in the msm patch and
moved hdcp registers into the trogdor dtsi file to avoid differences
with sc7180-based windows devices. The set is 4 patches lighter since
some of the changes were acce
Using IS_ERR_OR_NULL() together with PTR_ERR() is a typical mistake. If
the value is NULL, then the function will return 0 instead of a proper
return code. Moreover dpu_hw_vbif_init() function can not return NULL.
So, replace corresponding IS_ERR_OR_NULL() call with IS_ERR().
Reviewed-by: Abhinav
We do not expect to have other VBIFs. Drop VBIF_n indices and always use
VBIF_RT and VBIF_NRT.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 4 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++--
drivers/gpu/drm/msm/disp
Remove loops over hw_vbif. Instead always VBIF's idx as an index in the
array. This fixes an error in dpu_kms_hw_init(), where we fill
dpu_kms->hw_vbif[i], but check for an error pointer at
dpu_kms->hw_vbif[vbif_idx].
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Dmitry Ba
Hi,
On Tue, Jun 14, 2022 at 10:50 PM Hsin-Yi Wang wrote:
>
> On Thu, Jun 9, 2022 at 3:27 PM Hsin-Yi Wang wrote:
> >
> > Panels usually call drm_connector_set_panel_orientation(), which is
> > later than drm/kms driver calling drm_dev_register(). This leads to a
> > WARN()[1].
> >
> > The orienta
https://bugzilla.kernel.org/show_bug.cgi?id=216092
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
https://bugzilla.kernel.org/show_bug.cgi?id=216092
--- Comment #3 from Alex Deucher (alexdeuc...@gmail.com) ---
Does reverting c1b972a18d05d007f0ddff31db2ff50790576e92 fix the issue?
--
You may reply to this email to add a comment.
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Am 15.06.22 um 14:45 schrieb Dmitry Baryshkov:
On 09/06/2022 20:42, Rob Clark wrote:
From: Rob Clark
The DEFINE_DRM_GEM_FOPS() helper is a bit limiting if a driver wants to
provide additional file ops, like show_fdinfo().
v2: Split out DRM_GEM_FOPS instead of making DEFINE_DRM_GEM_FOPS
https://bugzilla.kernel.org/show_bug.cgi?id=216092
--- Comment #4 from RockT (tr...@gmx.de) ---
(In reply to Alex Deucher from comment #3)
> Does reverting c1b972a18d05d007f0ddff31db2ff50790576e92 fix the issue?
I never rebuild an Arch/Manjaro Kernel.
Will try but cannot promise.
--
You may rep
Il 14/06/22 18:58, Prashant Malani ha scritto:
On Tue, Jun 14, 2022 at 2:08 AM Pin-yen Lin wrote:
Hi AngeloGioacchino,
On Tue, Jun 14, 2022 at 4:15 PM AngeloGioacchino Del Regno
wrote:
Il 09/06/22 20:09, Prashant Malani ha scritto:
From: Pin-Yen Lin
Add the callback function when the d
KUnit unifies the test structure and provides helper tools that simplify
the development of tests. The basic use case allows running tests as regular
processes, which makes it easier to run unit tests on a development machine
and to integrate the tests into a CI system.
That said, the conversion o
Considering the current adoption of the KUnit framework, convert the
DRM damage helper selftest to the KUnit API.
Co-developed-by: Arthur Grillo
Signed-off-by: Arthur Grillo
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile
From: Arthur Grillo
Refactor the tests by modularizing the functions to avoid code repetition.
Co-developed-by: Maíra Canal
Signed-off-by: Arthur Grillo
Signed-off-by: Maíra Canal
---
.../drm/selftests/test-drm_cmdline_parser.c | 579 +-
1 file changed, 156 insertions(+), 4
Considering the current adoption of the KUnit framework, convert the
DRM cmdline parser selftest to the KUnit API.
Co-developed-by: Arthur Grillo
Signed-off-by: Arthur Grillo
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/selftests/Makefile| 2 +-
.../gpu/drm/selftests/drm_cmdlin
Considering the current adoption of the KUnit framework, convert the
DRM rect selftest to the KUnit API.
Co-developed-by: Carlos Veras
Signed-off-by: Carlos Veras
Co-developed-by: Matheus Vieira
Signed-off-by: Matheus Vieira
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/selftests/Makefile
Replace magic register writes in msm_mdss_enable() with version that
contains less magic and more variable names that can be traced back to
the dpu_hw_catalog or the downstream dtsi files.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 80 +++
Enable (optional) core (MDP_CLK) clock that allows accessing HW_REV
registers during the platform init.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/ms
Considering the current adoption of the KUnit framework, convert the
DRM format selftest to the KUnit API.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/selftests/Makefile| 3 +-
.../gpu/drm/selftests/drm_modeset_selftests.h | 3 -
drivers/gpu/drm/selftests/test-drm_format.c |
Considering the current adoption of the KUnit framework, convert the
DRM plane helper selftest to the KUnit API.
Co-developed-by: Djakson C. G. Filho
Signed-off-by: Djakson C. G. Filho
Co-developed-by: Anderson Fraga
Signed-off-by: Anderson Fraga
Signed-off-by: Maíra Canal
---
drivers/gpu/dr
Rather than checking whether the platform is an mdp5 or dpu platform,
check if the MDP_CLK is provided or not before trying to access HW_REV
(and skip reading the registers if the clock is not provided by the DT).
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 22 ++
Add MDP_CLK ("core") clock to the mdss device to allow MDSS driver to
access HW_REV/etc registers.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm6
Move is_mdp5 check to a more logical place, to the msm_mdss_init(),
rather than getting it in the mdss_probe() and passing it then as an
argument.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/
Considering the current adoption of the KUnit framework, convert the
DRM DP MST helper selftest to the KUnit API.
Co-developed-by: Rubens Gomes Neto
Signed-off-by: Rubens Gomes Neto
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/selftests/Makefile| 3 +-
.../gpu/drm/selftests/drm_
Considering the current adoption of the KUnit framework, convert the
DRM framebuffer selftest to the KUnit API.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/selftests/Makefile| 5 +--
.../gpu/drm/selftests/drm_modeset_selftests.h | 9 --
.../drm/selftests/test-drm_modeset_com
Considering the current adoption of the KUnit framework, convert the
DRM buddy selftest to the KUnit API.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/selftests/Makefile| 2 +-
.../gpu/drm/selftests/drm_buddy_selftests.h | 15 -
drivers/gpu/drm/selftests/test-drm_buddy.c|
From: Arthur Grillo
Refactor the tests by modularizing the functions to avoid code repetition.
Co-developed-by: Maíra Canal
Signed-off-by: Arthur Grillo
Signed-off-by: Maíra Canal
---
.../drm/selftests/test-drm_cmdline_parser.c | 579 +-
1 file changed, 156 insertions(+), 4
Hi Stephen,
I would appreciate if you could add
https://gitlab.freedesktop.org/lumag/msm.git msm-next-lumag
to the linux-next tree.
This tree is a part of drm/msm maintenance structure. As a co-maintainer
I collect and test display patches, while Rob concenctrates on GPU part
of the driver.
From: Arthur Grillo
Considering the current adoption of the KUnit framework, convert the
DRM mm selftest to the KUnit API.
Signed-off-by: Arthur Grillo
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/Kconfig | 20 -
drivers/gpu/drm/Makefile |1 -
On Mon, 2022-06-13 at 09:53 -0700, Matt Roper wrote:
> As with past platforms, the bspec's performance tuning guide provides
> recommended MMIO settings. Although not technically "workarounds" we
> apply these through the workaround framework to ensure that they're
> re-applied at the proper times
On Sat, Jun 11, 2022 at 11:16 AM Steev Klimaszewski wrote:
>
> Hi Rob,
>
> On 6/10/22 12:20 PM, Rob Clark wrote:
> > From: Rob Clark
> >
> > Keep the warn, but drop the early return. If we do manage to hit this
> > sort of issue, skipping the cleanup just makes things worse (dangling
> > drm_mm_
From: Rob Clark
I noticed while looking at some traces, that we could miss calls to
msm_update_fence(), as the irq could have raced with retire_submits()
which could have already popped the last submit on a ring out of the
queue of in-flight submits. But walking the list of submits in the
irq ha
From: Rob Clark
Prior to the last commit, this could result in setting the GPU
written fence value back to an older value, if we had missed
updating completed_fence prior to suspend. This was mostly
harmless as the GPU would eventually overwrite it again with
the correct value. But we should ju
I am crashing the kernel by doing something I believe I am allowed to do.
Using mmap to write to /dev/fb0 as the compatibility layer for Tiny
DRM vot,v220hf01a-t (ili9225).
First it happens that because of the display resolution of 220*176 the
buffer is (16 bit) 77440 bytes, which is not a multip
Hi Daniel
Thank you for your feedback! We are working on the comments you pointed out.
On 6/7/22 23:36, Daniel Latypov wrote:
> On Tue, Jun 7, 2022 at 6:09 PM Maíra Canal wrote:
>> diff --git
>> a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/display_mode_lib_test.c
>> b/drivers/gpu/drm/amd/disp
On Wed, Jun 15, 2022 at 08:22:23AM +0100, Tvrtko Ursulin wrote:
On 14/06/2022 17:42, Niranjana Vishwanathapura wrote:
On Tue, Jun 14, 2022 at 05:07:37PM +0100, Tvrtko Ursulin wrote:
On 14/06/2022 17:02, Tvrtko Ursulin wrote:
On 14/06/2022 16:43, Niranjana Vishwanathapura wrote:
On Tue, Jun
From: Chris Wilson
Don't allow two engines to be reset in parallel, as they would both
try to select a reset bit (and send requests to common registers)
and wait on that register, at the same time. Serialize control of
the reset requests/acks using the uncore->lock, which will also ensure
that no
From: Chris Wilson
Avoid trying to invalidate the TLB in the middle of performing an
engine reset, as this may result in the reset timing out. Currently,
the TLB invalidate is only serialised by its own mutex, forgoing the
uncore lock, but we can take the uncore->lock as well to serialise
the mmi
From: Chris Wilson
Don't flush TLBs when the buffer is only used in the GGTT under full
control of the kernel, as there's no risk of of concurrent access
and stale access from prefetch.
We only need to invalidate the TLB if they are accessible by the user.
Fixes: 7938d61591d3 ("drm/i915: Flush
i915 selftest hangcheck is causing the i915 driver timeouts, as reported
by Intel CI bot:
http://gfx-ci.fi.intel.com/cibuglog-ng/issuefilterassoc/24297?query_key=42a999f48fa6ecce068bc8126c069be7c31153b4
When such test runs, the only output is:
[ 68.811639] i915: Performing liv
From: Chris Wilson
Skip all further TLB invalidations once the device is wedged and
had been reset, as, on such cases, it can no longer process instructions
on the GPU and the user no longer has access to the TLB's in each engine.
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backi
From: Chris Wilson
As an extension of the current skip TLB invalidations,
check if the device is powered down prior to any engine activity,
as, on such cases, all the TLBs were already invalidated, so an
explicit TLB invalidation is not needed.
This becomes more significant with GuC, as it can
From: Chris Wilson
On gen12 HW, ensure that the TLB of the OA unit is also invalidated
as just invalidating the TLB of an engine is not enough.
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson
Cc: Fei Yang
Cc: Andi Shyti
Cc: sta...@vger.
Since commit 1ea2a07a532b ("iommu: Add DMA ownership management
interfaces") the Rockchip display driver on the Firefly RK3288 fails to
initialise properly. This is because ARM DMA domain is still attached.
Let's follow the lead of exynos and tegra and add code to explicitly
remove the ARM domain
Dne sreda, 15. junij 2022 ob 07:42:53 CEST je Samuel Holland napisal(a):
> If the component driver fails to bind, or is unbound, the driver data
> for the top-level platform device points to a freed drm_device. If the
> system is then suspended, the driver passes this dangling pointer to
> drm_mode
Display resolution change is implemented through drm modeset. Older
modeset (resolution) has to be disabled first before newer modeset
(resolution) can be enabled. Display disable will turn off both
pixel clock and main link clock so that main link have to be
re-trained during display enable to hav
On Tue, 14 Jun 2022 at 09:52, AngeloGioacchino Del Regno
wrote:
>
> Il 13/06/22 18:37, Nícolas F. R. A. Prado ha scritto:
> > While parsing the DT, the anx7625 driver checks for the presence of a
> > panel bridge on endpoint 1. If it is missing, pdata->panel_bridge stores
> > the error pointer and
The Arm Juno board EDK2 port has provided an EFI GOP display via HDLCD0
for some time now, which works nicely as an early framebuffer. However,
once the HDLCD driver probes and takes over the hardware, it should
take over the logical framebuffer as well, otherwise the now-defunct GOP
device hangs a
Since we no longer need to conform to the structure of the various DRM
IRQ callbacks, we can streamline the code by consolidating the piecemeal
functions and passing around our private data structure directly. We're
also a platform device so should never see IRQ_NOTCONNECTED either.
Furthermore we
On 6/15/2022 2:35 AM, Dmitry Baryshkov wrote:
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang wrote:
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by adding other get_crc helper methods.
C
On 6/15/2022 2:44 AM, Dmitry Baryshkov wrote:
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang wrote:
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Changes since V1:
- Set values_cnt to only include phys with backi
On 15/06/2022 19:11, Jessica Zhang wrote:
On 6/15/2022 2:35 AM, Dmitry Baryshkov wrote:
On Wed, 15 Jun 2022 at 00:13, Jessica Zhang
wrote:
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by
From: Rob Clark
And while we are at it, let's start the fence counter close to the
rollover point so that if issues slip in, they are more obvious.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fence.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/dr
On Mon, 13 Jun 2022 at 16:54, Zheng Bin wrote:
>
> The driver uses crypto hash functions so it needs to select CRYPTO_HASH.
> This fixes build errors:
>
> drivers/gpu/drm/bridge/ite-it6505.o: in function `it6505_hdcp_wait_ksv_list':
> ite-it6505.c:(.text+0x4c26): undefined reference to `crypto_all
From: Rob Clark
In debugging fence rollover, I noticed that GPU state capture and
devcore dumps were showing me negative fence numbers. Let's fix that
and some related signed vs unsigned confusion.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 +-
1 file ch
On 6/15/2022 5:36 AM, Dmitry Baryshkov wrote:
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf and wb resources to
dpu_encoder_setup_displa
On Wed, Jun 15, 2022 at 8:33 AM hongao wrote:
>
> Replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi for more
> efficiency
>
> Tested on "Oland [Radeon HD 8570 / R7 240/340 OEM]" & "Caicos [R5 230]"
Can you verify that drm_display_info.is_hdmi has been populated when
all of these fun
On Wed, Jun 15, 2022 at 1:45 AM AngeloGioacchino Del Regno
wrote:
>
> Il 14/06/22 18:57, Prashant Malani ha scritto:
> > On Tue, Jun 14, 2022 at 1:18 AM AngeloGioacchino Del Regno
> > wrote:
> >>
> >> Il 09/06/22 20:09, Prashant Malani ha scritto:
> >>> When the DT node has "switches" available,
On 15/06/2022 19:40, Abhinav Kumar wrote:
On 6/15/2022 5:36 AM, Dmitry Baryshkov wrote:
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during
dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf a
On Wed, Jun 15, 2022 at 04:27:36PM +0100, Mauro Carvalho Chehab wrote:
From: Chris Wilson
On gen12 HW, ensure that the TLB of the OA unit is also invalidated
as just invalidating the TLB of an engine is not enough.
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Si
On 6/15/2022 10:04 AM, Dmitry Baryshkov wrote:
On 15/06/2022 19:40, Abhinav Kumar wrote:
On 6/15/2022 5:36 AM, Dmitry Baryshkov wrote:
On 14/06/2022 22:32, Abhinav Kumar wrote:
intf and wb resources are not dependent on the rm global
state so need not be allocated during
dpu_encoder_virt
This series introduces a binding for Type-C data lane switches. These
control the routing and operating modes of USB Type-C data lanes based
on the PD messaging from the Type-C port driver regarding connected
peripherals.
The first patch introduces a change to the Type-C mux class mode-switch
matc
Loosen the typec_mux_match() requirements so that searches where an
alt mode is not specified, but the target mux device lists the
"mode-switch" property, return a success.
This is helpful in Type C port drivers which would like to get a pointer
to the mux switch associated with a Type C port, but
There are some drivers that can use the Type C mux API, but don't have
to. Introduce CONFIG guards for the mux functions so that drivers can
include the header file and not run into compilation errors on systems
which don't have CONFIG_TYPEC enabled. When CONFIG_TYPEC is not enabled,
the Type C mux
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