On Mon, Apr 25, 2022 at 02:12:50PM -0700, Matt Roper wrote:
The IDs added here are the subset reserved for 'motherboard down'
designs of DG2. We have all the necessary support upstream to enable
these now (although they'll continue to require force_probe until the
usual requirements are met).
T
Fix spelling typo in comment.
Signed-off-by: pengfuyuan
---
drivers/gpu/drm/arm/malidp_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/malidp_regs.h
b/drivers/gpu/drm/arm/malidp_regs.h
index 514c50dcb74d..3bc16db70ddb 100644
--- a/drivers/gpu/drm/a
While technically Xen dom0 is a virtual machine too, it does have
access to most of the hardware so it doesn't need to be considered a
"passthrough". Commit b818a5d37454 ("drm/amdgpu/gmc: use PCI BARs for
APUs in passthrough") changed how FB is accessed based on passthrough
mode. This breaks amdgpu
Signed-off-by: oushixiong
---
drivers/gpu/drm/amd/include/atomfirmware.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 7bd763361d6e..b7a1e2116e7e 100644
--- a/drivers/gpu/drm/amd/i
Fix spelling typo in comment.
Signed-off-by: pengfuyuan
---
drivers/gpu/drm/arm/malidp_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/malidp_regs.h
b/drivers/gpu/drm/arm/malidp_regs.h
index 514c50dcb74d..59f63cc2b304 100644
--- a/drivers/gpu/drm/a
Signed-off-by: oushixiong
---
drivers/gpu/drm/amd/include/atomfirmware.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 7bd763361d6e..b7a1e2116e7e 100644
--- a/drivers/gpu/drm/amd/i
Hi Laurent,
On Do, Apr 21, 2022 at 07:33:18 +0300, Laurent Pinchart wrote:
> On Thu, Apr 21, 2022 at 06:12:59PM +0200, Eugeniu Rosca wrote:
> > Since the meat of the Renesas patch [1]
> > is basically a printk in the interrupt context and an array storing
> > the total number of underruns occurred
The IT6505 is using functions provided by the DRM_DP_HELPER driver.
In order to avoid having the bridge enabled but the helper disabled,
let's add a select in order to be sure that the DP helper functions are
always available.
Fixes: b5c84a9edcd4 ("drm/bridge: add it6505 driver")
Signed-off-by: Fa
On Tue, Apr 26, 2022 at 05:29:31PM +0200, Neil Armstrong wrote:
> On 26/04/2022 16:15, Fabien Parent wrote:
> > The IT6505 is using functions provided by the DRM_DP_HELPER driver.
> > In order to avoid having the bridge enabled but the helper disabled,
> > let's add a select in order to be sure tha
On Tue, 26 Apr 2022 21:43:12 -0300
Igor Torrente wrote:
> On 4/26/22 04:09, Pekka Paalanen wrote:
> > On Mon, 25 Apr 2022 21:56:12 -0300
> > Igor Torrente wrote:
> >
> >> Hi Pekka,
> >>
> >> On 4/25/22 04:56, Pekka Paalanen wrote:
> >>> On Sat, 23 Apr 2022 12:12:51 -0300
> >>> Igor Torrente
On Tue, 26 Apr 2022 22:22:22 -0300
Igor Torrente wrote:
> On April 26, 2022 10:03:09 PM GMT-03:00, Igor Torrente
> wrote:
> >
> >
> >On 4/25/22 22:54, Igor Torrente wrote:
> >> Hi Pekka,
> >>
> >> On 4/25/22 05:10, Pekka Paalanen wrote:
> >>> On Sat, 23 Apr 2022 15:53:20 -0300
> >>> Igor T
On 27/04/2022 00:12, Kuogee Hsieh wrote:
Current DP driver implementation has adding safe mode done at
dp_hpd_plug_handle() which is expected to be executed under event
thread context.
However there is possible circular locking happen (see blow stack trace)
after edp driver call dp_hpd_plug_hand
On Tue, 26 Apr 2022 21:53:19 -0300
Igor Torrente wrote:
> Hi Pekka,
>
> On 4/21/22 07:58, Pekka Paalanen wrote:
> > On Mon, 4 Apr 2022 17:45:15 -0300
> > Igor Torrente wrote:
> >
> >> Adds this common format to vkms.
> >>
> >> This commit also adds new helper macros to deal with fixed-point
Disable ABM feature when the system is running on AC mode to get the more
perfect contrast of the display.
v2: remove "UPSTREAM" from the subject.
v3: adv->pm.ac_power updating by amd gpu_acpi_event_handler.
V4: Add the file I lost to fix the build error.
Signed-off-by: Ryan Lin
---
drivers/
On 20/04/2022 18:13, Matthew Auld wrote:
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture interactions, including no longer needing
NEEDS_CPU_ACCESS for objects marked for capture. (
https://bugzilla.kernel.org/show_bug.cgi?id=215892
Artem S. Tashkinov (a...@gmx.com) changed:
What|Removed |Added
Status|NEW |RESOLVED
Sorry for late reply,
On Thu, 2022-04-14 at 17:13 +0100, Robert Beckett wrote:
>
>
> On 14/04/2022 15:05, Thomas Hellström wrote:
> > On Tue, 2022-04-12 at 15:18 +, Robert Beckett wrote:
> > > stolen/kernel buffers should not be mmapable by userland.
> > > do not provide callbacks to facilit
On 26/04/2022 17:41, Abhinav Kumar wrote:
Change the DRM traces to include both the intf_mode
and wb_idx similar to the DRM prints in the previous change.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
This commit got traces broken. I'm going to apply a fix.
---
drivers/gpu/d
Hi Dave, Daniel,
Here goes the first drm-intel-gt-next PR towards 5.19.
A lot of stuff here across the board in terms of new features, new platform
support and bug fixes. For bug fixes the most interesting are:
* a fix for out of bounds kernel access in mmap ops due incorrect object bound
On 27/04/2022 00:50, Stephen Boyd wrote:
Quoting Vinod Polimera (2022-04-25 23:02:11)
Avoid clearing irqs and derefernce hw_intr when hw_intr is null.
Presumably this is only the case when the display driver doesn't fully
probe and something probe defers? Can you clarify how this situation
hap
Hi Ville and Alex,
thanks for the replies. More below.
TL;DR:
My take-away from this is that I should slam 'max bpc' to the max by
default, and offer a knob for the user in case they want to lower it.
On Tue, 26 Apr 2022 20:55:14 +0300
Ville Syrjälä wrote:
> On Tue, Apr 26, 2022 at 11:35:02A
The Arm PL110 and PL111 are IP blocks that provide a display engine with
an LCD interface, being able to drive a variety of LC panels.
Convert the binding over to DT schema, to the DTs can be automatically
checked.
This still contains the deprecated "arm,pl11x,tft-r0g0b0-pads" property,
because th
The Arm Mali Display Processor (DP) 5xx/6xx is a series of IP that scans
out a framebuffer and hands the pixels over to a digital signal encoder.
It supports multiple layers, scaling and rotation.
Convert the existing DT binding to DT schema.
Signed-off-by: Andre Przywara
---
.../bindings/displ
The Arm Komeda (aka Mali-D71) is a display controller that scans out a
framebuffer and hands a signal to a digital encoder to generate a DVI
or HDMI signal. It supports up to two pipelines, each frame can be
composed of up to four layers.
Convert the existing DT binding to DT schema.
Signed-off-b
The Arm HDLCD is a display controller that scans out a framebuffer and
hands a signal to a digital encoder to generate a DVI or HDMI signal.
Convert the existing DT binding to DT schema.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/display/arm,hdlcd.txt | 79
.../b
On Wed, Apr 27, 2022 at 12:29 PM Jagan Teki wrote:
>
> On Thu, Apr 21, 2022 at 1:54 PM Maxime Ripard wrote:
> >
> > On Thu, Apr 21, 2022 at 01:15:54PM +0530, Jagan Teki wrote:
> > > + Linus
> > > + Marek
> > > + Laurent
> > > + Robert
> > >
> > > On Thu, Apr 21, 2022 at 4:40 AM Bjorn Andersson
>
Fix following coccicheck error:
./drivers/gpu/drm/i915/gvt/handlers.c:2925:35-41: ERROR: block is NULL but
dereferenced.
Use gvt->mmio.mmio_block instead of block to avoid NULL pointer
dereference when find_mmio_block returns NULL.
Fixes: e0f74ed4634d ("i915/gvt: Separate the MMIO tracking table
On Tue, 26 Apr 2022 at 17:36, Christian König wrote:
>
> Hi Mike,
>
> sounds like somehow stitching together the SG table for PRIME doesn't
> work any more with this patch.
>
> Can you try with P2P DMA disabled?
-CONFIG_PCI_P2PDMA=y
+# CONFIG_PCI_P2PDMA is not set
If that's what you're meaning,
On Tue, Apr 26, 2022 at 08:16:39PM +0800, pengfuyuan wrote:
> Fix spelling typo in comment.
>
> Signed-off-by: pengfuyuan
Acked-by: Liviu Dudau
Many thanks for fixing this!
Best regards,
Liviu
> ---
> drivers/gpu/drm/arm/malidp_regs.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
https://bugzilla.kernel.org/show_bug.cgi?id=215892
--- Comment #6 from Mark Johnston (ula...@gmail.com) ---
There is one potentially similar report here:
https://gitlab.freedesktop.org/drm/amd/-/issues/1933
Though both of the users report having working desktop environments and nothing
about amdg
On Tue, Apr 26, 2022 at 05:26:14PM -0700, Daniele Ceraolo Spurio wrote:
> The huc_is_authenticated function return is based on our SW tracking of
> the HuC auth status. However, around suspend/resume and reset this can
> go out of sync with the actual HW state, which is why we use
> huc_check_state
On Tue, Apr 26, 2022 at 05:26:17PM -0700, Daniele Ceraolo Spurio wrote:
> The previous patch introduced new failure cases in the HuC init flow
> that can be hit by simply changing the config, so we want to avoid
> failing the probe in those scenarios. HuC load failure is already
> considered a non-
Hi Paul,
On Wed, Apr 27, 2022 at 5:49 PM Paul Kocialkowski
wrote:
>
> Hi Jagan,
>
> On Wed 27 Apr 22, 17:22, Jagan Teki wrote:
> > On Wed, Apr 27, 2022 at 12:29 PM Jagan Teki
> > wrote:
> > >
> > > On Thu, Apr 21, 2022 at 1:54 PM Maxime Ripard wrote:
> > > >
> > > > On Thu, Apr 21, 2022 at 01:
On Wed, Apr 27, 2022 at 05:22:32PM +0530, Jagan Teki wrote:
> On Wed, Apr 27, 2022 at 12:29 PM Jagan Teki wrote:
> > On Thu, Apr 21, 2022 at 1:54 PM Maxime Ripard wrote:
> > > On Thu, Apr 21, 2022 at 01:15:54PM +0530, Jagan Teki wrote:
> > > > + Linus
> > > > + Marek
> > > > + Laurent
> > > > + Rob
On Tue, Apr 26, 2022 at 02:54:01PM +0200, Maxime Ripard wrote:
> On Tue, Apr 26, 2022 at 02:41:44PM +0200, Paul Kocialkowski wrote:
> > On Tue 26 Apr 22, 14:33, Laurent Pinchart wrote:
> > > On Tue, Apr 26, 2022 at 09:54:36AM +0200, Paul Kocialkowski wrote:
> > > > On Thu 21 Apr 22, 10:59, Paul Koc
Hi,
I withdraw this series of patches.
I'm going to submit updated version after applying checkpatch.pl with strict
option.
Best regards,
Yuji
> -Original Message-
> From: Yuji Ishikawa
> Sent: Tuesday, April 19, 2022 4:20 PM
> To: iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> ; Sumit Semwal
> ;
This series is the AFFINE image processing accelerator driver for Toshiba's ARM
SoC, Visconti[0].
This provides DT binding documentation, device driver, MAINTAINER files.
The second patch "soc: visconti: Add Toshiba Visconti image processing
accelerator common source"
is commonly used among accl
Adds common operations for image processing accelerator drivers
including dma-buf control and ioctl definitiion
Signed-off-by: Yuji Ishikawa
Reviewed-by: Nobuhiro Iwamatsu
---
v1 -> v2:
- apply checkpatch.pl --strict
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile
Adds the Device Tree binding documentation that allows to describe
the AFFINE image processing accelerator found in Toshiba Visconti SoCs.
Signed-off-by: Yuji Ishikawa
Reviewed-by: Nobuhiro Iwamatsu
---
.../soc/visconti/toshiba,visconti-affine.yaml | 53 +++
1 file changed, 53 i
Signed-off-by: Yuji Ishikawa
Reviewed-by: Nobuhiro Iwamatsu
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index dd36acc87..231b2c6f9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2796,12 +2796,14 @@ F:
Documentation/devicetree/bindings/net
Adds support to AFFINE image processing accelerator on Toshiba Visconti ARM
SoCs.
This accelerator supoorts affine transform, lens undistortion and LUT transform.
Signed-off-by: Yuji Ishikawa
Reviewed-by: Nobuhiro Iwamatsu
---
v1 -> v2:
- apply checkpatch.pl --strict
- renamed identifiers;
This patch fixes a bug where GEN1 VMs doesn't allow resolutions greater
than 64 MB size (eg 7680x4320). Unnecessary PCI check limits Gen1 VRAM
to legacy PCI BAR size only (ie 64MB). Thus any, resolution requesting
greater then 64MB (eg 7680x4320) would fail. MMIO region assigning this
memory should
On Wed, Apr 20, 2022 at 03:50:00PM -0700, Niranjana Vishwanathapura wrote:
> On Thu, Mar 31, 2022 at 01:37:08PM +0200, Daniel Vetter wrote:
> > One thing I've forgotten, since it's only hinted at here: If/when we
> > switch tlb flushing from the current dumb&synchronous implementation
> > we now ha
On Thu, Apr 14, 2022 at 01:24:30PM +0300, Jani Nikula wrote:
> On Mon, 11 Apr 2022, Alex Deucher wrote:
> > On Mon, Apr 11, 2022 at 6:18 AM Hans de Goede wrote:
> >>
> >> Hi,
> >>
> >> On 4/8/22 17:11, Alex Deucher wrote:
> >> > On Fri, Apr 8, 2022 at 10:56 AM Hans de Goede
> >> > wrote:
> >> >
Since it's inception in 2012 it has been understood that the DRM GEM CMA
helpers do not depend on CMA as the backend allocator. In fact the first
bug fix to ensure the cma-helpers work correctly with an IOMMU backend
appeared in 2014. However currently the documentation for
drm_gem_cma_create() tal
On Wed, Apr 13, 2022 at 06:12:59PM +0200, Michel Dänzer wrote:
> From: Michel Dänzer
>
> Instead of relying on it getting pulled in indirectly.
>
> Signed-off-by: Michel Dänzer
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/tiny/bochs.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
Move all format-specific handling in per-line conversion functions and
share the overall loop among conversion helpers. This is another step
towards composable format conversion.
Thomas Zimmermann (4):
drm/format-helper: Implement drm_fb_swab() with per-line helpers
drm/format-helper: Remove
Implement per-pixel byte swapping in a separate conversion helper
for the single function that requires it. Select the correct helper
for each conversion.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_format_helper.c | 32 +
1 file changed, 24 insertions(+)
Give each per-line conversion helper pointers of type void and the
number of pixels in the line. Remove the unused swab parameters.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_format_helper.c | 87 +
1 file changed, 50 insertions(+), 37 deletions(-)
diff
Provide format-independent conversion helpers for system and I/O
memory. Implement most existing helpers on top of it. The source and
destination formats of each conversion is handled by a per-line
helper that is given to the generic implementation.
Signed-off-by: Thomas Zimmermann
---
drivers/g
Replace the inner loop of drm_fb_swab() with helper functions that
swap the bytes in each pixel. This will allow to share the outer
loop with other conversion helpers.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_format_helper.c | 60 +
1 file changed, 35
On Thu, Apr 14, 2022 at 10:37:55PM +0200, Helge Deller wrote:
> Hello dri-devel & dim users,
Apologies for late reply, I'm way behind on stuff.
> I committed this patch to the drm-misc-next branch:
>
> commit d6cd978f7e6b6f6895f8d0c4ce6e5d2c8e979afe
> video: fbdev: fbmem: fix pointer referen
On Wed, 27 Apr 2022, Daniel Vetter wrote:
> On Thu, Apr 14, 2022 at 01:24:30PM +0300, Jani Nikula wrote:
>> On Mon, 11 Apr 2022, Alex Deucher wrote:
>> > On Mon, Apr 11, 2022 at 6:18 AM Hans de Goede wrote:
>> >>
>> >> Hi,
>> >>
>> >> On 4/8/22 17:11, Alex Deucher wrote:
>> >> > On Fri, Apr 8, 2
On Wed, Apr 27, 2022 at 05:23:22PM +0300, Jani Nikula wrote:
> On Wed, 27 Apr 2022, Daniel Vetter wrote:
> > On Thu, Apr 14, 2022 at 01:24:30PM +0300, Jani Nikula wrote:
> >> On Mon, 11 Apr 2022, Alex Deucher wrote:
> >> > On Mon, Apr 11, 2022 at 6:18 AM Hans de Goede
> >> > wrote:
> >> >>
> >>
LGTM
Acked-by: Siva Mullati
On 06/04/22 14:48, Vivekanandan, Balasubramani wrote:
> When copying RSA use io memcpy functions if the destination address
> contains a GPU local memory address. Considering even the source
> address can be on local memory, a bounce buffer is used to copy from io
> t
On Tue, Apr 26, 2022 at 01:40:31PM +0530, Jagan Teki wrote:
> On Tue, Apr 26, 2022 at 1:24 PM Paul Kocialkowski
> wrote:
> >
> > Hi,
> >
> > On Thu 21 Apr 22, 10:59, Paul Kocialkowski wrote:
> > > Hi Maxime,
> > >
> > > On Thu 21 Apr 22, 10:23, Maxime Ripard wrote:
> > > > On Thu, Apr 21, 2022 at
Hi Dmitry
Thanks for fixing it up.
I agree about the indentation issue.
And yes even wb_idx missing in TP_ARGS seems like a geniune miss.
But the weird part is it did not break my compilation. I tested even now
without your fix.
Am I missing something to be enabled in my config to replicate
On 2022-04-26 22:31, Hangyu Hua wrote:
On 2022/4/26 22:55, Andrey Grodzovsky wrote:
On 2022-04-25 22:54, Hangyu Hua wrote:
On 2022/4/25 23:42, Andrey Grodzovsky wrote:
On 2022-04-25 04:36, Hangyu Hua wrote:
When drm_sched_job_add_dependency() fails, dma_fence_put() will be
called
internall
Applied. Thanks!
Alex
On Wed, Apr 27, 2022 at 3:12 AM Marek Marczykowski-Górecki
wrote:
>
> While technically Xen dom0 is a virtual machine too, it does have
> access to most of the hardware so it doesn't need to be considered a
> "passthrough". Commit b818a5d37454 ("drm/amdgpu/gmc: use PCI BAR
On Mon, Apr 18, 2022 at 10:18:54PM +0300, Dmitry Osipenko wrote:
> Hello,
>
> On 4/18/22 21:38, Thomas Zimmermann wrote:
> > Hi
> >
> > Am 18.04.22 um 00:37 schrieb Dmitry Osipenko:
> >> Replace drm_gem_shmem locks with the reservation lock to make GEM
> >> lockings more consistent.
> >>
> >> Pre
On 27/04/2022 07:55, Christian König wrote:
Well usually we increment the drm minor version when adding some new
flags on amdgpu.
Additional to that just one comment from our experience with that: You
don't just need one flag, but two. The first one is a hint which says
"CPU access needed" an
On Tue, Apr 19, 2022 at 11:40:41PM +0300, Dmitry Osipenko wrote:
> On 4/19/22 10:22, Thomas Zimmermann wrote:
> > Hi
> >
> > Am 18.04.22 um 00:37 schrieb Dmitry Osipenko:
> >> Introduce a common DRM SHMEM shrinker. It allows to reduce code
> >> duplication among DRM drivers that implement theirs o
Am 27.04.22 um 17:02 schrieb Matthew Auld:
On 27/04/2022 07:55, Christian König wrote:
Well usually we increment the drm minor version when adding some new
flags on amdgpu.
Additional to that just one comment from our experience with that:
You don't just need one flag, but two. The first one
On 2022-04-27 04:08, Ryan Lin wrote:
Disable ABM feature when the system is running on AC mode to get the more
perfect contrast of the display.
v2: remove "UPSTREAM" from the subject.
v3: adv->pm.ac_power updating by amd gpu_acpi_event_handler.
V4: Add the file I lost to fix the build error
On Wed, Apr 20, 2022 at 09:24:11AM +0200, Javier Martinez Canillas wrote:
> Learning about the DRM subsystem could be quite overwhelming for newcomers
> but there are lots of useful talks, slides and articles available that can
> help to understand the needed concepts and ease the learning curve.
>
On Wed, Apr 27, 2022 at 08:55:07AM +0200, Christian König wrote:
> Well usually we increment the drm minor version when adding some new flags
> on amdgpu.
>
> Additional to that just one comment from our experience with that: You don't
> just need one flag, but two. The first one is a hint which s
On 2022-04-27 06:52, Pekka Paalanen wrote:
> Hi Ville and Alex,
>
> thanks for the replies. More below.
>
> TL;DR:
>
> My take-away from this is that I should slam 'max bpc' to the max by
> default, and offer a knob for the user in case they want to lower it.
>
>
> On Tue, 26 Apr 2022 20:55
On 27/04/2022 07:48, Lionel Landwerlin wrote:
One question though, how do we detect that this flag
(I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) is accepted on a given kernel?
I assume older kernels are going to reject object creation if we use
this flag?
From some offline discussion with Lionel
On 27/04/2022 18:18, Matthew Auld wrote:
On 27/04/2022 07:48, Lionel Landwerlin wrote:
One question though, how do we detect that this flag
(I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) is accepted on a given
kernel?
I assume older kernels are going to reject object creation if we use
this flag?
On Wed, Apr 20, 2022 at 03:45:25PM -0700, Niranjana Vishwanathapura wrote:
On Thu, Mar 31, 2022 at 10:28:48AM +0200, Daniel Vetter wrote:
Adding a pile of people who've expressed interest in vm_bind for their
drivers.
Also note to the intel folks: This is largely written with me having my
subsy
On Thu, Apr 21, 2022 at 09:10:02PM +0200, Christian König wrote:
> drm_gem_plane_helper_prepare_fb() was using
> drm_atomic_set_fence_for_plane() which ignores all implicit fences when an
> explicit fence is already set. That's rather unfortunate when the fb still
> has a kernel fence we need to wa
On Tue, Apr 26, 2022 at 11:20 PM Christian König
wrote:
>
> Am 26.04.22 um 20:50 schrieb Chia-I Wu:
> > On Tue, Apr 26, 2022 at 11:02 AM Christian König
> > wrote:
> >> Am 26.04.22 um 19:40 schrieb Chia-I Wu:
> >>> [SNIP]
> >> Well I just send a patch to completely remove the trace point.
> >
On 25/04/2022 17:24, Ramalingam C wrote:
Capture the eviction details for Flat-CCS capable, lmem objects.
v2:
Fix the Flat-ccs capbility of lmem obj with smem residency
possibility [Thomas]
Signed-off-by: Ramalingam C
cc: Thomas Hellstrom
cc: Matthew Auld
---
drivers/gpu/drm/i915/gt/
Am Mittwoch, dem 27.04.2022 um 15:09 +0100 schrieb Daniel Thompson:
> Since it's inception in 2012 it has been understood that the DRM GEM CMA
> helpers do not depend on CMA as the backend allocator. In fact the first
> bug fix to ensure the cma-helpers work correctly with an IOMMU backend
> appear
From: John Harrison
Add GuC firmware for DG2.
Note that an older version of this patch exists in the CI topic
branch. Hence this set includes a revert of that patch before applying
the new version. When merging, the revert would simply be dropped and
the corresponding patch in the topic branch w
From: John Harrison
This reverts commit 55c7f980e48e56861496526e02ed5bbfdac49ede.
The CI topic branch within drm-top contains an old patch for
supporting GuC on DG2. That needs to be dropped and an updated patch
merged to drm-gt-next. Hence this patch reverts it so the new patch
can be sent in i
From: John Harrison
First release of GuC for DG2.
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/g
On 25/04/2022 17:24, Ramalingam C wrote:
Capture the impact of memory region preference list of an object, on
their memory residency and Flat-CCS capability of the objects.
v2:
Fix the Flat-CCS capability of an obj with {lmem, smem} preference
list [Thomas]
Signed-off-by: Ramalingam C
cc
Hello Daniel,
On 4/27/22 17:29, Daniel Vetter wrote:
> On Wed, Apr 20, 2022 at 09:24:11AM +0200, Javier Martinez Canillas wrote:
>> Learning about the DRM subsystem could be quite overwhelming for newcomers
>> but there are lots of useful talks, slides and articles available that can
>> help to un
On 27/04/2022 09:36, Tvrtko Ursulin wrote:
On 20/04/2022 18:13, Matthew Auld wrote:
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture interactions, including no longer needing
NEEDS_C
On Wed, Apr 27, 2022 at 9:07 AM Rob Clark wrote:
>
> On Tue, Apr 26, 2022 at 11:20 PM Christian König
> wrote:
> >
> > Am 26.04.22 um 20:50 schrieb Chia-I Wu:
> > > On Tue, Apr 26, 2022 at 11:02 AM Christian König
> > > wrote:
> > >> Am 26.04.22 um 19:40 schrieb Chia-I Wu:
> > >>> [SNIP]
> > >>>
john.c.harri...@intel.com kirjoitti 27.4.2022 klo 19.55:
From: John Harrison
Add GuC firmware for DG2.
Note that an older version of this patch exists in the CI topic
branch. Hence this set includes a revert of that patch before applying
the new version. When merging, the revert would simply b
Hey! I will try to test this out ASAP on all of the HDR backlight machines I
have (so, many :) at some point this week, will let you know when
On Tue, 2022-04-26 at 15:30 +0300, Jouni Högander wrote:
> This patch set splits out static hdr metadata backlight range parsing
> from gpu/drm/amd/display
Hi Daniel,
On 4/27/22 16:21, Daniel Vetter wrote:
> On Thu, Apr 14, 2022 at 10:37:55PM +0200, Helge Deller wrote:
>> Hello dri-devel & dim users,
>
> Apologies for late reply, I'm way behind on stuff.
>
>> I committed this patch to the drm-misc-next branch:
>>
>> commit d6cd978f7e6b6f6895f8d0c4ce6
On 4/27/22 15:47, Saurabh Sengar wrote:
> This patch fixes a bug where GEN1 VMs doesn't allow resolutions greater
> than 64 MB size (eg 7680x4320). Unnecessary PCI check limits Gen1 VRAM
> to legacy PCI BAR size only (ie 64MB). Thus any, resolution requesting
> greater then 64MB (eg 7680x4320) woul
On 25/04/2022 17:24, Ramalingam C wrote:
Calculate the ccs_sz that needs to be emitted based on the src
and dst pages emitted per chunk. And handle the return value of emit_pte
for the ccs pages.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 36 +---
On 25/04/2022 17:24, Ramalingam C wrote:
While locating the start of ccs scatterlist in smem scatterlist, that has
to be the size of lmem obj size + corresponding ccs data size. Report bug
if scatterlist terminate before that length.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/int
On Wed, Apr 27, 2022 at 12:25:26PM +0100, Andre Przywara wrote:
> The Arm HDLCD is a display controller that scans out a framebuffer and
> hands a signal to a digital encoder to generate a DVI or HDMI signal.
>
> Convert the existing DT binding to DT schema.
>
> Signed-off-by: Andre Przywara
> -
On Wed, Apr 27, 2022 at 12:25:27PM +0100, Andre Przywara wrote:
> The Arm Mali Display Processor (DP) 5xx/6xx is a series of IP that scans
> out a framebuffer and hands the pixels over to a digital signal encoder.
> It supports multiple layers, scaling and rotation.
>
> Convert the existing DT bin
This is V3 of my nested AVIC patches.
I fixed few more bugs, and I also split the cod insto smaller patches.
Review is welcome!
Best regards,
Maxim Levitsky
Maxim Levitsky (19):
KVM: x86: document AVIC/APICv inhibit reasons
KVM: x86: inhibit APICv/AVIC when the guest and/or host cha
These days there are too many AVIC/APICv inhibit
reasons, and it doesn't hurt to have some documentation
for them.
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/kvm_host.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/inc
Neither of these settings should be changed by the guest and it is
a burden to support it in the acceleration code, so just inhibit
it instead.
Also add a boolean 'apic_id_changed' to indicate if apic id ever changed.
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/kvm_host.h | 3 +++
a
AVIC is now inhibited if the guest changes apic id, thus remove
that broken code.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 35 ---
1 file changed, 35 deletions(-)
diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
index 54fe03714f8a
This allows to enable the write tracking only when KVMGT is
actually used and doesn't carry any penalty otherwise.
Tested by booting a VM with a kvmgt mdev device.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/Kconfig | 3 ---
arch/x86/kvm/mmu/mmu.c | 2 +-
drivers/gpu/dr
This will be used to enable write tracking from nested AVIC code
and can also be used to enable write tracking in GVT-g module
when it actually uses it as opposed to always enabling it,
when the module is compiled in the kernel.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
a
This is a tiny refactoring, and can be useful to check
if a GPA/GFN is within a memslot a bit more cleanly.
Signed-off-by: Maxim Levitsky
---
include/linux/kvm_host.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
If a non leaf mmu page is write tracked externally for some reason,
which can in theory happen if it was used for nested avic physid page
before, then this code will enter an endless loop of page faults because
unprotecting the mmu page will not remove write tracking, nor will the
write tracker cal
This will make the code a bit easier to read when nested AVIC support
is added.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 51 +++--
arch/x86/kvm/svm/svm.h | 14 ++-
2 files changed, 37 insertions(+), 2
This patch adds few tracepoints that will be used
to debug/profile the nested AVIC.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/trace.h | 157 ++-
arch/x86/kvm/x86.c | 13
2 files changed, 169 insertions(+), 1 deletion(-)
diff --git a/arch/x86/
This implements a few helpers that help manipulate the AVIC's
physical and logical id table entries.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/svm.h | 45 ++
1 file changed, 45 insertions(+)
diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/
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