On Wed, Apr 06, 2022 at 09:43:49AM +0800, Andy Yan wrote:
> Hi Sacha:
>
> On 4/5/22 17:05, Sascha Hauer wrote:
> > On Sat, Apr 02, 2022 at 09:25:33AM +0800, Andy Yan wrote:
> > > Hi Sascha:
> > >
> > > On 4/1/22 20:55, Sascha Hauer wrote:
> > > > On Thu, Mar 31, 2022 at 07:00:34PM +0800, Andy Yan
On Fri, Apr 1, 2022 at 1:58 PM Xiaomeng Tong wrote:
>
> Instead of exiting the loop as expected when an entry is found, the
> list_for_each_entry() continues until the traversal is complete. To
> avoid potential executing 'ret = gma_backlight_init(dev);' repeatly,
> break the loop when the entry i
From: Lv Ruyi
'dm_services.h' included in 'freesync,c' is duplicated, so remove one.
Reported-by: Zeal Robot
Signed-off-by: Lv Ruyi
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/frees
change upate to update
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
include/drm/drm_modeset_helper_vtables.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_modeset_helper_vtables.h
b/include/drm/drm_modeset_helper_vtables.h
index fdfa9f37ce05..fafa70
On Wed, 6 Apr 2022 at 03:43, Marek Vasut wrote:
>
> Fix copy-paste error, module exit function should be marked with __exit
> instead of __init.
>
> Fixes: 8dde6f7452a1 ("drm: bridge: icn6211: Add I2C configuration support")
> Reported-by: Stephen Rothwell
> Signed-off-by: Marek Vasut
> Cc: Jaga
Applied to drm-misc-next.
On 05/04/2022 17:05, Daniel Vetter wrote:
On Tue, Apr 05, 2022 at 04:53:45PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Mixup in rebasing and patchwork re-runs made me push the wrong version of
the patch. Or I even forgot to send out the fixed version. Fix it up.
Signed-off-by: Tvrtk
On Fri, Apr 1, 2022 at 1:50 PM Xiaomeng Tong wrote:
>
> Instead of exiting the loop as expected when an entry is found, the
> list_for_each_entry() continues until the traversal is complete.
> when found the entry, add a break after the switch statement.
>
> Signed-off-by: Xiaomeng Tong
Thanks f
Hi:
On 4/6/22 15:04, Sascha Hauer wrote:
On Wed, Apr 06, 2022 at 09:43:49AM +0800, Andy Yan wrote:
Hi Sacha:
On 4/5/22 17:05, Sascha Hauer wrote:
On Sat, Apr 02, 2022 at 09:25:33AM +0800, Andy Yan wrote:
Hi Sascha:
On 4/1/22 20:55, Sascha Hauer wrote:
On Thu, Mar 31, 2022 at 07:00:34PM +08
Hi Daniel,
rebased on top of all the changes in drm-misc-next now and hopefully
ready for 5.19.
I think I addressed all concern, but there was a bunch of rebase fallout
from i915, so better to double check that once more.
Regards,
Christian.
Audit all the users of dma_resv_add_excl_fence() and make sure they
reserve a shared slot also when only trying to add an exclusive fence.
This is the next step towards handling the exclusive fence like a
shared one.
v2: fix missed case in amdgpu
v3: and two more radeon, rename function
v4: add o
This change adds the dma_resv_usage enum and allows us to specify why a
dma_resv object is queried for its containing fences.
Additional to that a dma_resv_usage_rw() helper function is added to aid
retrieving the fences for a read or write userspace submission.
This is then deployed to the diffe
Instead of distingting between shared and exclusive fences specify
the fence usage while adding fences.
Rework all drivers to use this interface instead and deprecate the old one.
v2: some kerneldoc comments suggested by Daniel
v3: fix a missing case in radeon
v4: rebase on nouveau changes, fix l
Rework the internals of the dma_resv object to allow adding more than one
write fence and remember for each fence what purpose it had.
This allows removing the workaround from amdgpu which used a container for
this instead.
Signed-off-by: Christian König
Cc: amd-...@lists.freedesktop.org
---
dr
Always wait for kernel fences before kmap and not only for UVD kmaps.
Signed-off-by: Christian König
---
drivers/gpu/drm/radeon/radeon_object.c | 7 ++-
drivers/gpu/drm/radeon/radeon_uvd.c| 12 ++--
2 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/
Wait only for kernel fences before kmap or UVD direct submission.
This also makes sure that we always wait in amdgpu_bo_kmap() even when
returning a cached pointer.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_u
Even for explicit synchronization we should wait for kernel fences.
Signed-off-by: Christian König
---
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 27 ++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
b/drivers/gp
Add an usage for kernel submissions. Waiting for those are mandatory for
dynamic DMA-bufs.
As a precaution this patch also changes all occurrences where fences are
added as part of memory management in TTM, VMWGFX and i915 to use the
new value because it now becomes possible for drivers to ignore
Use DMA_RESV_USAGE_BOOKKEEP for VM page table updates and KFD preemption fence.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/dri
Don't wait for user space submissions. I'm not 100% sure if that is
correct, but it seems to match what the code initially intended.
Signed-off-by: Christian König
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nou
We only need to wait for kernel submissions here.
Signed-off-by: Christian König
---
drivers/infiniband/core/umem_dmabuf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/infiniband/core/umem_dmabuf.c
b/drivers/infiniband/core/umem_dmabuf.c
index f9901d273b8e..fce80a
We have previously done that in the individual drivers but it is
more defensive to move that into the common code.
Dynamic attachments should wait for map operations to complete by themselves.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/dma-buf/dma-buf.c
Add an usage for submissions independent of implicit sync but still
interesting for memory management.
v2: cleanup the kerneldoc a bit
v3: separate amdgpu changes from this
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/dma-buf/dma-resv.c | 4 ++--
driv
This is now handled by the DMA-buf framework in the dma_resv obj.
Also remove the workaround inside VMWGFX to update the moving fence.
Signed-off-by: Christian König
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 13 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 5 ++-
drivers/g
That should now be handled by the common dma_resv framework.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Cc: intel-...@lists.freedesktop.org
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 41 ---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 +---
drivers
This should be possible now since we don't have the distinction
between exclusive and shared fences any more.
The only possible pitfall is that a dma_fence would be reused during the
RCU grace period, but even that could be handled with a single extra check.
Signed-off-by: Christian König
---
d
Using memset on local arrays before exiting the function is pointless.
Compilator will remove this code. Also for local arrays is preferable to
use {0} instead of memset. Mistakes are often made when working with
memset.
Signed-off-by: Grigory Vasilyev
---
drivers/gpu/drm/amd/amdgpu/atom.c | 8 +
On 2022-03-21 14:36, Christophe Branchereau wrote:
Hi Christophe,
looks good to me.
Cheers,
Artur
Acked-by: Artur Rojek
ingenic_drm_bridge_atomic_enable allows the CRTC to be enabled after
panels have slept out, and before their display is turned on, solving
a graphical bug on the newvision
A typo in the code. It was assumed that it was
possible to shift the pointer to sizeof(BIOS_ATOM_PREFIX) - 1.
Signed-off-by: Grigory Vasilyev
---
drivers/gpu/drm/amd/amdgpu/atom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c
b/drivers/gpu
A typo in the code. It was assumed that it was
possible to shift the pointer to sizeof(BIOS_ATOM_PREFIX) - 1.
Signed-off-by: Grigory Vasilyev
---
drivers/gpu/drm/amd/amdgpu/atom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c
b/drivers/gpu
The code is useless and doesn't change the value.
(0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT) = 0
gb_addr_config | 0 = gb_addr_config
Perhaps there could be 1 instead of 0, but this does not correspond with
the logic of the switch.
Signed-off-by: Grigory Vasilyev
---
drivers/gpu/drm/amd/amdgpu/gfx_
Às 17:45 de 04/04/22, Igor Torrente escreveu:
> Add a helper function to validate the connector configuration receive in
Maybe it should be "received"
> the encoder atomic_check by the drivers.
>
> So the drivers don't need do these common validations themselves.
"don't need do" -> "don't need
Hi Igor,
Thanks for your patch!
Às 17:45 de 04/04/22, Igor Torrente escreveu:
> Currently, the memory to the composition frame is being allocated using
> the kzmalloc. This comes with the limitation of maximum size of one
> page size(which in the x86_64 is 4Kb and 4MB for default and hugepage
> r
A typo in the code. It was assumed that it was
possible to shift the pointer to sizeof(BIOS_ATOM_PREFIX) - 1.
Signed-off-by: Grigory Vasilyev
---
drivers/gpu/drm/amd/amdgpu/atom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c
b/drivers/gpu
On Wed, Apr 06, 2022 at 03:47:18PM +0800, Andy Yan wrote:
> Hi:
>
> On 4/6/22 15:04, Sascha Hauer wrote:
> > On Wed, Apr 06, 2022 at 09:43:49AM +0800, Andy Yan wrote:
> > > Hi Sacha:
> > >
> > > On 4/5/22 17:05, Sascha Hauer wrote:
> > > > On Sat, Apr 02, 2022 at 09:25:33AM +0800, Andy Yan wrote:
This driver has been changed to use the resource managed
devm_drm_of_get_bridge() to get bridge from ->attach(), it's
unnecessary to assign NULL to out_bridge to remove the bridge
from ->detach() as devm_drm_of_get_bridge() is automatically
remove the bridge when @dev is unbound.
Drop explicit NUL
On Wed, Apr 06, 2022 at 10:02:59AM +0800, Andy Yan wrote:
> Hi:
>
> On 4/5/22 17:37, Sascha Hauer wrote:
> > On Sat, Apr 02, 2022 at 09:37:17AM +0800, Andy Yan wrote:
> > > Hi Sacha:
> > >
> > > On 4/1/22 20:52, Sascha Hauer wrote:
> > > > --
> > > > >From cbc03073623a7180243331ac24c3afaf9dec752
Hi:
On 4/6/22 16:13, Sascha Hauer wrote:
On Wed, Apr 06, 2022 at 10:02:59AM +0800, Andy Yan wrote:
Hi:
On 4/5/22 17:37, Sascha Hauer wrote:
On Sat, Apr 02, 2022 at 09:37:17AM +0800, Andy Yan wrote:
Hi Sacha:
On 4/1/22 20:52, Sascha Hauer wrote:
--
>From cbc03073623a7180243331ac24c3afaf9dec
From: Sandor Yu
HDMI1.4b specification section 6.5.3:
Source shall only send GCPs with non-zero CD to sinks
that indicate support for Deep Color.
DW HDMI GPC default enabled, clear gpc_auto bit for bpp 24.
Signed-off-by: Sandor Yu
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 8
1
From: Sandor Yu
It is new features and bug fix patch set for DW_HDMI DRM bridge driver
that has verified by NXP iMX865.
Three new feature added:
1. Add GP Audio interface for DW_HDMI.
2. Add CEC PM functions to restore CEC status when device suspend/resume
3. New API for reset PHY Gen1.
Two bugs
Am 25.02.22 um 15:35 schrieb Maxime Ripard:
The HVS core clock isn't really obvious, so let's add a bunch more
comments and some logging for easier debugging.
Signed-off-by: Maxime Ripard
Acked-by: Thomas Zimmermann
---
drivers/gpu/drm/vc4/vc4_kms.c | 11 +++
1 file changed, 1
Am 25.02.22 um 15:35 schrieb Maxime Ripard:
Now that the clock driver makes sure we never end up with a rate of 0,
the HDMI driver doesn't need to care anymore.
Signed-off-by: Maxime Ripard
Acked-by: Thomas Zimmermann
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 13 -
1 file chang
Hi Stephen,
Le mer., avril 6 2022 at 10:50:49 +1000, Stephen Rothwell
a écrit :
Hi all,
After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/gpu/drm/panel/panel-newvision-nv3052c.c:478:19: error:
initialization of 'void (*)(struct spi_dev
Hi Maxime
Am 28.03.22 um 17:36 schrieb Maxime Ripard:
If we use a format that has padding instead of the alpha component (such
as XRGB), it appears that the Transposer will fill the padding to 0,
disregarding what was stored in the input buffer padding.
This leads to issues with IGT, since
Am 28.03.22 um 17:36 schrieb Maxime Ripard:
The documentation explicitly states we must prevent the output
2 and 3 from feeding from the same HVS channel.
Let's add a warning to make some noise if we ever find ourselves in such
a case.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/v
Hi
Am 28.03.22 um 17:36 schrieb Maxime Ripard:
Hi,
This series address multiple issues with the transposer support, and thus the
writeback support.
With my comments considered, feel free to add
Acked-by: Thomas Zimmermann
I cannot really check the correctness of the individual HW operation
When copying RSA use io memcpy functions if the destination address
contains a GPU local memory address. Considering even the source
address can be on local memory, a bounce buffer is used to copy from io
to io.
The intention of this patch is to make i915 portable outside x86 mainly
on ARM64.
Sign
Hi Robin,
On Tue, Apr 05, 2022 at 03:11:18PM +0100, Robin Murphy wrote:
> iommu_get_domain_for_dev() is already perfectly happy to return NULL
> if the given device has no IOMMU. Drop the unnecessary check.
>
> Signed-off-by: Robin Murphy
LGTM, Acked-by: Brian Starkey
I'll have to leave it to
In case the MXSFB is connected to a bridge, attempt to obtain bus flags
from that bridge state too. The bus flags may specify e.g. the DE signal
polarity.
Signed-off-by: Marek Vasut
Cc: Alexander Stein
Cc: Laurent Pinchart
Cc: Lucas Stach
Cc: Peng Fan
Cc: Robby Cai
Cc: Sam Ravnborg
Cc: Stef
The DE signal is active high on this display, fill in the missing bus_flags.
This aligns panel_desc with its display_timing .
Fixes: a5d2ade627dca ("drm/panel: simple: Add support for Innolux G070Y2-L01")
Signed-off-by: Marek Vasut
Cc: Christoph Fritz
Cc: Laurent Pinchart
Cc: Maxime Ripard
Cc:
Display Stream Compression (DSC) compresses the display stream in host which
is later decoded by panel. This series enables this for Qualcomm msm driver.
This was tested on Google Pixel3 phone which use LGE SW43408 panel.
The changes include DSC data and hardware block enabling for DPU1 then
supp
Display Stream Compression (DSC) parameters need to be calculated. Add
helpers and struct msm_display_dsc_config in msm_drv for this
msm_display_dsc_config uses drm_dsc_config for DSC parameters.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu
When DSC is enabled, we need to get the DSC parameters from the panel
driver, so add a dsc parameter in panel to fetch and pass DSC
configuration for DSI panels to DPU encoder, which will enable and
then configure DSC hardware blocks accordingly.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhin
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 13 ++
drivers/gpu/drm/
This adds SDM845 DSC blocks into hw_catalog
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog
In SDM845, DSC can be enabled by writing to pingpong block registers, so
add support for DSC in hw_pp
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++-
drivers/gpu/drm/msm/disp/dpu1/d
We need to configure the encoder for DSC configuration and calculate DSC
parameters for the given timing so this patch adds that support by
adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
From: Dmitry Baryshkov
DPU supports different topologies for the case when multiple INTFs are
being driven by the single phys_enc. The driver defaults to using 3DMux
in such cases. Don't use it if DSC merge is used instead.
Suggested-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
Signed-off
Somehow documentation for num_dspp was missed, so add that
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/msm_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
inde
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions up to 4k. For more resolutions like 8k this won't
work.
Also, it is better to use 2 LMs and DSC instances as half width results
in lesser power consumption as compared to single LM, DSC at full width.
The
This add the bits in RM to enable the DSC blocks
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
Add a mode valid callback for dsi_mgr for checking mode being valid in
case of DSC. For DSC the height and width needs to be multiple of slice,
so we check that here
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi.h |
Update headers from mesa commit:
commit 28ae397be111c37c6ced397e12d453a7695701bd
Author: Vinod Koul
Date: Fri Apr 1 16:53:04 2022 +0530
freedreno/registers: update dsi registers to support dsc
Display Stream compression (DSC) compresses the display stream in
host which
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Dmit
> Wiadomość napisana przez Piotr Oniszczuk w dniu
> 01.04.2022, o godz. 15:05:
>
>
>
>> Wiadomość napisana przez Sascha Hauer w dniu
>> 01.04.2022, o godz. 14:52:
>>
>> Based on the discussion with Andy please try the following patch, it
>> should fix your green screen issue. Note that w
On Wed, 6 Apr 2022 at 07:03, Stephen Boyd wrote:
>
> Quoting Dmitry Baryshkov (2022-04-05 16:50:59)
> > diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> > index d661debb50f1..ee3093890d97 100644
> > --- a/drivers/gpu/drm/msm/msm_drv.h
> > +++ b/drivers/gpu/drm/msm/msm_d
On Wed, Apr 06, 2022 at 03:30:36PM +0800, Sui Jingfeng wrote:
> change upate to update
>
> Signed-off-by: Sui Jingfeng <15330273...@189.cn>
Applied to drm-misc-next, thanks for the patch.
-Daniel
> ---
> include/drm/drm_modeset_helper_vtables.h | 2 +-
> 1 file changed, 1 insertion(+), 1 delet
Remove unused field plane_property from struct msm_drm_private. Also
drop the enum msm_mdp_plane_property which also becomes unused.
Fixes: 7d36db0be3b9 ("drm/msm/mdp5: switch to standard zpos property")
Signed-off-by: Dmitry Baryshkov
---
Changes since v1: also drop enum msm_mdp_plane_property
Hi,
On Mon, Mar 28, 2022 at 10:22:11AM +0800, Zhengbin (OSKernel) wrote:
> On 2022/3/25 21:05, Maxime Ripard wrote:
> > On Fri, Mar 25, 2022 at 10:18:31AM +0800, Zheng Bin wrote:
> > > If CONFIG_DRM_VC4=y, CONFIG_RASPBERRYPI_FIRMWARE=m, CONFIG_COMPILE_TEST=n,
> > > bulding fails:
> > >
> > > driv
Remove manual removal of DRM modesetting objects, it is done anyway by
the drm_mode_config_cleanup() called from msm_drm_uninit(). Other
MSM display drivers (MDP4, MDP5) do not manually destroy objects and
trust generic code to do it's work.
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshk
There is no point now in storing arrays of creates planes, connectors
and encoders. Remove them from struct msm_drm_private.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 13 +++--
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 7 ---
drivers/gpu/drm/msm
Rather than manually looping over encoders array, use standard
drm_for_each_encoder() macro.
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +++--
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 6 ++
2 files changed, 5 insertions(+), 6
MSM DRM driver stores connectors, encoders and planes in the arrays
inside struct msm_drm_private. They are not really necessary, as
drm_devices also references lists of these objects. Drop private arrays
and use drm_mode_foo() macros.
Note, the crtc array is kept intact as it is used in vblank ha
On 06/04/2022 05:51, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-04-05 16:45:48)
Add calls to drm_bridge_add()/drm_bridge_remove() for the internal HDMI
bridges. This fixes the following warning.
[2.195003] [ cut here ]
Usually this line is left out
[2
Il 06/04/22 11:46, Rex-BC Chen ha scritto:
The driver data of MT8183 and MT8173 are different.
The value of has_gamma for MT8173 is true while the value of MT8183 is
false. Therefore, the compatible of disp_aal for MT8183 is not suitable
for the compatible for MT8173.
Signed-off-by: Rex-BC Chen
Il 06/04/22 11:46, Rex-BC Chen ha scritto:
The driver data of MT8183 and MT8173 are different.
The value of has_gamma for MT8173 is true while the value of MT8183 is
false. Therefore, the compatible of disp_aal for MT8183 is not suitable
for the compatible for MT8173.
Signed-off-by: Rex-BC Chen
Il 06/04/22 11:46, Rex-BC Chen ha scritto:
The driver data for MT8192 is the same with MT8183. Therefore, we
correct it.
Signed-off-by: Rex-BC Chen
Reviewed-by: AngeloGioacchino Del Regno
...though, from what I know, you should also move MT8195 down there!
Hi
Am 31.03.22 um 16:37 schrieb Maxime Ripard:
The vc4_hvs_update_dlist function mostly deals with setting up the
vblank events and setting up the dlist entry pointer to our current
active one.
We'll want to do the former separately from the vblank handling in later
patches, so let's move it to
On Fri, 25 Feb 2022 15:35:22 +0100, Maxime Ripard wrote:
> This is a follow-up of the discussion here:
> https://lore.kernel.org/linux-clk/20210319150355.xzw7ikwdaga2dwhv@gilmour/
>
> and here:
> https://lore.kernel.org/all/20210914093515.260031-1-max...@cerno.tech/
>
> While the initial proposal
Hi Maxime,
for the whole patchset
Acked-by: Thomas Zimmermann
Best regards
Thomas
Am 31.03.22 um 16:37 schrieb Maxime Ripard:
Hi,
These patches used to be part of the series:
https://lore.kernel.org/all/20220221134155.125447-1-max...@cerno.tech/
but since the main patch got superseded by a
Il 06/04/22 12:48, Rex-BC Chen ha scritto:
On Wed, 2022-04-06 at 18:40 +0800, AngeloGioacchino Del Regno wrote:
Il 06/04/22 11:46, Rex-BC Chen ha scritto:
The driver data for MT8192 is the same with MT8183. Therefore, we
correct it.
Signed-off-by: Rex-BC Chen
Reviewed-by: AngeloGioacchino D
On 2022-03-28 16:10, Sascha Hauer wrote:
Whenever pclk_vo is enabled hclk_vo must be enabled as well. This is
described in the Reference Manual as:
| 2.8.6 NIU Clock gating reliance
|
| A part of niu clocks have a dependence on another niu clock in order to
| sharing the internal bus. When these
Instead of exiting the loop as expected when an entry is found, the
list_for_each_entry() continues until the traversal is complete. To
avoid potential executing 'ret = gma_backlight_init(dev);' repeatly,
goto outside the loop when the entry is found.
Signed-off-by: Xiaomeng Tong
---
changes sin
On Wed, Apr 06, 2022 at 09:51:17AM +0200, Christian König wrote:
> Audit all the users of dma_resv_add_excl_fence() and make sure they
> reserve a shared slot also when only trying to add an exclusive fence.
>
> This is the next step towards handling the exclusive fence like a
> shared one.
>
> v
On Wed, Apr 06, 2022 at 09:51:19AM +0200, Christian König wrote:
> Instead of distingting between shared and exclusive fences specify
> the fence usage while adding fences.
>
> Rework all drivers to use this interface instead and deprecate the old one.
>
> v2: some kerneldoc comments suggested by
On Wed, Apr 06, 2022 at 02:32:22PM +0200, Daniel Vetter wrote:
> On Wed, Apr 06, 2022 at 09:51:19AM +0200, Christian König wrote:
> > Instead of distingting between shared and exclusive fences specify
> > the fence usage while adding fences.
> >
> > Rework all drivers to use this interface instead
On Wed, Apr 06, 2022 at 09:51:20AM +0200, Christian König wrote:
> Rework the internals of the dma_resv object to allow adding more than one
> write fence and remember for each fence what purpose it had.
>
> This allows removing the workaround from amdgpu which used a container for
> this instead.
On Wed, Apr 06, 2022 at 09:51:21AM +0200, Christian König wrote:
> Add an usage for kernel submissions. Waiting for those are mandatory for
> dynamic DMA-bufs.
>
> As a precaution this patch also changes all occurrences where fences are
> added as part of memory management in TTM, VMWGFX and i915
On Wed, Apr 06, 2022 at 09:51:22AM +0200, Christian König wrote:
> Wait only for kernel fences before kmap or UVD direct submission.
>
> This also makes sure that we always wait in amdgpu_bo_kmap() even when
> returning a cached pointer.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/dr
On Wed, Apr 06, 2022 at 09:51:23AM +0200, Christian König wrote:
> Always wait for kernel fences before kmap and not only for UVD kmaps.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/radeon/radeon_object.c | 7 ++-
> drivers/gpu/drm/radeon/radeon_uvd.c| 12 ++--
> 2
On Wed, Apr 06, 2022 at 09:51:24AM +0200, Christian König wrote:
> Even for explicit synchronization we should wait for kernel fences.
Yeah I don't think this patch makes much sense, because aside from etnaviv
there's also msm and lima which allow you to ignore all dma_resv fences
completely.
But
On Wed, Apr 06, 2022 at 09:51:25AM +0200, Christian König wrote:
> Don't wait for user space submissions. I'm not 100% sure if that is
> correct, but it seems to match what the code initially intended.
>
> Signed-off-by: Christian König
I'll let nouveau folks review/test this one.
-Daniel
> ---
On Wed, Apr 06, 2022 at 09:51:26AM +0200, Christian König wrote:
> We only need to wait for kernel submissions here.
>
> Signed-off-by: Christian König
I think we had an implied ack from Jason on this one. Not quite enough cc
to regrab it.
Reviewed-by: Daniel Vetter
> ---
> drivers/infiniban
On Wed, Apr 06, 2022 at 09:51:31AM +0200, Christian König wrote:
> This is now handled by the DMA-buf framework in the dma_resv obj.
>
> Also remove the workaround inside VMWGFX to update the moving fence.
>
> Signed-off-by: Christian König
Looks all reasonable.
Reviewed-by: Daniel Vetter
>
On Wed, Apr 06, 2022 at 09:51:16AM +0200, Christian König wrote:
> Hi Daniel,
>
> rebased on top of all the changes in drm-misc-next now and hopefully
> ready for 5.19.
>
> I think I addressed all concern, but there was a bunch of rebase fallout
> from i915, so better to double check that once mo
On Wed, Apr 06, 2022 at 09:51:32AM +0200, Christian König wrote:
> This should be possible now since we don't have the distinction
> between exclusive and shared fences any more.
>
> The only possible pitfall is that a dma_fence would be reused during the
> RCU grace period, but even that could be
On Sun, Apr 03, 2022 at 03:53:54PM -0700, Randy Dunlap wrote:
> Add @cache description to eliminate a kernel-doc warning.
>
> include/linux/host1x.h:104: warning: Function parameter or member 'cache' not
> described in 'host1x_client'
>
> Fixes: 1f39b1dfa53c ("drm/tegra: Implement buffer object
On Thu, Mar 24, 2022 at 11:30:25AM +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> Buffer mappings used in job submissions are usually small and not
> rapidly reused as opposed to framebuffers (which are usually large and
> rapidly reused, for example when page-flipping between double-buf
Le mercredi 06 avril 2022 à 09:20 +0800, Yunfei Dong a écrit :
> Will return -EINVAL using standard framework api when test stateless
> decoder with cmd VIDIOC_(TRY)DECODER_CMD.
>
> Using another return value to adjust v4l2 compliance test for user
> driver(GStreamer/Chrome) won't use decoder cmd.
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