Dear Christian,
Am 05.04.22 um 08:54 schrieb Christian König:
Am 05.04.22 um 08:45 schrieb Paul Menzel:
Am 04.04.22 um 23:42 schrieb Philip Yang:
bo_adev is NULL for system memory mapping to GPU.
Fixes: 05fe8eeca92 (drm/amdgpu: fix TLB flushing during eviction)
Sorry, where can I find th
Am 04.04.22 um 13:47 schrieb Karol Herbst:
On Sun, Apr 3, 2022 at 5:59 PM Christian König wrote:
Just a gentle ping to the nouveau guys.
Any more comments on this? Otherwise I'm pushing that with Daniels rb.
It looks fine, but given that this area broke in the past I will try
to do some test
From: Thomas Zimmermann
commit cd9f7f7ac5932129fe81b4c7559cfcb226ec7c5c upstream.
Mark screen buffers in system memory with FBINFO_VIRTFB. Otherwise, fbdev
deferred I/O marks mmap'ed areas of system memory with VM_IO. (There's an
inverse relationship between the two flags.)
For shadow buffers,
On Wed, 23 Mar 2022 16:48:23 +0100, Maxime Ripard wrote:
> MIPI-DSI devices, if they are controlled through the bus itself, have to
> be described as a child node of the controller they are attached to.
>
> Thus, there's no requirement on the controller having an OF-Graph output
> port to model th
On 23/03/2022 13:19, Tvrtko Ursulin wrote:
Hi,
On 21/03/2022 16:45, Alan Previn wrote:
This series:
1. Enables support of GuC to report error-state-capture
using a list of MMIO registers the driver registers
and GuC will dump, log and notify right before a GuC
triggered
Am 23.03.22 um 14:36 schrieb Daniel Vetter:
On Mon, Mar 21, 2022 at 02:58:43PM +0100, Christian König wrote:
Drivers should never touch this directly.
v2: fix rebase clash
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
I guess as soon as we have the rdma ack you can land up to t
On Sat, Apr 02, 2022 at 02:41:18AM +0200, Marek Vasut wrote:
> The datasheet for this bridge is not available, the PLL behavior has been
> inferred from [1] and [2] and by analyzing the DPI pixel clock with scope.
> After further testing with other displays and different DSI data lane count,
> it t
From: Kees Cook
[ Upstream commit a2151490cc6c57b368d7974ffd447a8b36ade639 ]
The link_status array was not large enough to read the Adjust Request
Post Cursor2 register, so remove the common helper function to avoid
an OOB read, found with a -Warray-bounds build:
drivers/gpu/drm/drm_dp_helper.c
On 04/04/2022 16:36, Daniel Vetter wrote:
On Mon, Apr 04, 2022 at 10:23:53AM +0100, Tvrtko Ursulin wrote:
+ Dave and Daniel
Guys, are you okay with merging this via drm-intel-gt-next? It is one new
file at Documentation/gpu/drm-usage-stats.rst only which is outside i915. It
has acks from Chr
From: Tim Gardner
[ Upstream commit 37a1a2e6eeeb101285cd34e12e48a881524701aa ]
Coverity complains of a possible buffer overflow. However,
given the 'static' scope of nvidia_setup_i2c_bus() it looks
like that can't happen after examiniing the call sites.
CID 19036 (#1 of 1): Copy into fixed size
From: Kees Cook
commit d4da1f27396fb1dde079447a3612f4f512caed07 upstream.
The pcon_dsc_dpcd array holds 13 registers (0x92 through 0x9E). Fix the
math to calculate the max size. Found from a -Warray-bounds build:
drivers/gpu/drm/drm_dp_helper.c: In function 'drm_dp_pcon_dsc_bpp_incr':
drivers/g
Den 04.04.2022 21.21, skrev Marek Vasut:
> Make the width-mm/height-mm panel properties mandatory
> to correctly report the panel dimensions to the OS.
>
> Fixes: 2f3468b82db97 ("dt-bindings: display: add bindings for MIPI DBI
> compatible SPI panels")
> Signed-off-by: Marek Vasut
> Cc: Chris
On Wed, Feb 09, 2022 at 01:19:26AM +0100, Javier Martinez Canillas wrote:
> On 2/8/22 22:08, Daniel Vetter wrote:
> > This reverts commit fb561bf9abde49f7e00fdbf9ed2ccf2d86cac8ee.
> >
> > With
> >
> > commit 27599aacbaefcbf2af7b06b0029459bbf682000d
> > Author: Thomas Zimmermann
> > Date: Tue J
On Tue, Apr 05, 2022 at 10:36:35AM +0200, Daniel Vetter wrote:
> On Wed, Feb 09, 2022 at 01:19:26AM +0100, Javier Martinez Canillas wrote:
> > On 2/8/22 22:08, Daniel Vetter wrote:
> > > This reverts commit fb561bf9abde49f7e00fdbf9ed2ccf2d86cac8ee.
> > >
> > > With
> > >
> > > commit 27599aacbaef
From: Thomas Zimmermann
commit cd9f7f7ac5932129fe81b4c7559cfcb226ec7c5c upstream.
Mark screen buffers in system memory with FBINFO_VIRTFB. Otherwise, fbdev
deferred I/O marks mmap'ed areas of system memory with VM_IO. (There's an
inverse relationship between the two flags.)
For shadow buffers,
On Thu, Feb 10, 2022 at 12:46:32PM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 08.02.22 um 22:08 schrieb Daniel Vetter:
> > There's two minor behaviour changes in here:
> > - in error paths we now consistently call fb_ops->fb_release
> > - fb_release really can't fail (fbmem.c ignores it too) and
On Mon, Apr 04, 2022 at 09:44:02PM +0200, Thomas Zimmermann wrote:
> OF framebuffers do not have an underlying device in the Linux
> device hierarchy. Do a regular unregister call instead of hot
> unplugging such a non-existing device. Fixes a NULL dereference.
> An example error message on ppc64le
On Sat, Apr 02, 2022 at 09:25:33AM +0800, Andy Yan wrote:
> Hi Sascha:
>
> On 4/1/22 20:55, Sascha Hauer wrote:
> > On Thu, Mar 31, 2022 at 07:00:34PM +0800, Andy Yan wrote:
> > > Hi:
> > >
> > > On 3/31/22 16:18, Sascha Hauer wrote:
> > > > On Thu, Mar 31, 2022 at 03:20:37PM +0800, Andy Yan wrot
In the amdgpu_amdkfd_get_xgmi_bandwidth_mbytes function,
the peer_adev pointer can be NULL and is passed to amdgpu_xgmi_get_num_links.
In amdgpu_xgmi_get_num_links, peer_adev pointer is dereferenced
without any checks: peer_adev->gmc.xgmi.node_id .
Signed-off-by: Grigory Vasilyev
---
drivers/gp
Variable igp_lane_info always is 0. 0 & any value = 0 and false.
In this way, all сonditional statements will false.
Therefore, it is not clear what this code does.
Signed-off-by: Grigory Vasilyev
---
.../gpu/drm/amd/amdgpu/atombios_encoders.c| 21 ---
1 file changed, 21 dele
From: Tim Gardner
[ Upstream commit 37a1a2e6eeeb101285cd34e12e48a881524701aa ]
Coverity complains of a possible buffer overflow. However,
given the 'static' scope of nvidia_setup_i2c_bus() it looks
like that can't happen after examiniing the call sites.
CID 19036 (#1 of 1): Copy into fixed size
Hi Marek,
Thank you for the patch.
On Mon, Apr 04, 2022 at 09:21:05PM +0200, Marek Vasut wrote:
> Make the width-mm/height-mm panel properties mandatory
> to correctly report the panel dimensions to the OS.
>
> Fixes: 2f3468b82db97 ("dt-bindings: display: add bindings for MIPI DBI
> compatible
From: Kees Cook
commit d4da1f27396fb1dde079447a3612f4f512caed07 upstream.
The pcon_dsc_dpcd array holds 13 registers (0x92 through 0x9E). Fix the
math to calculate the max size. Found from a -Warray-bounds build:
drivers/gpu/drm/drm_dp_helper.c: In function 'drm_dp_pcon_dsc_bpp_incr':
drivers/g
Hello Daniel,
On 4/5/22 10:40, Daniel Vetter wrote:
> On Tue, Apr 05, 2022 at 10:36:35AM +0200, Daniel Vetter wrote:
>> On Wed, Feb 09, 2022 at 01:19:26AM +0100, Javier Martinez Canillas wrote:
>>> On 2/8/22 22:08, Daniel Vetter wrote:
This reverts commit fb561bf9abde49f7e00fdbf9ed2ccf2d86cac
On Tue, 5 Apr 2022 at 11:19, Javier Martinez Canillas
wrote:
>
> Hello Daniel,
>
> On 4/5/22 10:40, Daniel Vetter wrote:
> > On Tue, Apr 05, 2022 at 10:36:35AM +0200, Daniel Vetter wrote:
> >> On Wed, Feb 09, 2022 at 01:19:26AM +0100, Javier Martinez Canillas wrote:
> >>> On 2/8/22 22:08, Daniel V
Am 29.03.22 um 18:02 schrieb Daniel Vetter:
On Mon, Mar 21, 2022 at 02:58:56PM +0100, Christian König wrote:
[SNIP]
static unsigned long ttm_bo_io_mem_pfn(struct ttm_buffer_object *bo,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index f999f
From: Thomas Zimmermann
commit cd9f7f7ac5932129fe81b4c7559cfcb226ec7c5c upstream.
Mark screen buffers in system memory with FBINFO_VIRTFB. Otherwise, fbdev
deferred I/O marks mmap'ed areas of system memory with VM_IO. (There's an
inverse relationship between the two flags.)
For shadow buffers,
On Sat, Apr 02, 2022 at 09:37:17AM +0800, Andy Yan wrote:
> Hi Sacha:
>
> On 4/1/22 20:52, Sascha Hauer wrote:
> > --
> > >From cbc03073623a7180243331ac24c3afaf9dec7522 Mon Sep 17 00:00:00 2001
> > From: Sascha Hauer
> > Date: Fri, 1 Apr 2022 14:48:49 +0200
> > Subject: [PATCH] fixup! drm: rockch
Am 2022-04-05 11:23, schrieb codrin.ciubota...@microchip.com:
On 03.03.2022 18:17, Michael Walle wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know
the content is safe
The supplied buffer might be on the stack and we get the following
error
message:
[3.312058]
On 01.04.2022 18:07, Ramalingam C wrote:
> Move the static calculations out of the loops for copy and clear.
>
> Signed-off-by: Ramalingam C
> Reviewed-by: Thomas Hellstrom
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c | 40 -
> 1 file changed, 19 insertions(+), 21 del
From: Tim Gardner
[ Upstream commit 37a1a2e6eeeb101285cd34e12e48a881524701aa ]
Coverity complains of a possible buffer overflow. However,
given the 'static' scope of nvidia_setup_i2c_bus() it looks
like that can't happen after examiniing the call sites.
CID 19036 (#1 of 1): Copy into fixed size
On 4/5/22 11:24, Daniel Vetter wrote:
> On Tue, 5 Apr 2022 at 11:19, Javier Martinez Canillas
[snip]
>>
>> This is how I think that work, please let me know if you see something
>> wrong in my logic:
>>
>> 1) A PCI device of OF device is registered for the GPU, this attempt to
>>match a regis
From: Kees Cook
commit d4da1f27396fb1dde079447a3612f4f512caed07 upstream.
The pcon_dsc_dpcd array holds 13 registers (0x92 through 0x9E). Fix the
math to calculate the max size. Found from a -Warray-bounds build:
drivers/gpu/drm/drm_dp_helper.c: In function 'drm_dp_pcon_dsc_bpp_incr':
drivers/g
On 2022-03-29 at 18:53:42 +0530, Balasubramani Vivekanandan wrote:
> On 29.03.2022 00:37, Ramalingam C wrote:
> > Move the static calculations out of the loops for copy and clear.
> >
> > Signed-off-by: Ramalingam C
> > Reviewed-by: Thomas Hellström
> > ---
> > drivers/gpu/drm/i915/gt/intel_mig
On 2022-03-28 13:55, Jonathan Marek wrote:
This matches the implementation of iommu_map_sgtable() used for the
non-per-process page tables path.
This works around the dma_map_sgtable() call (used to invalidate cache)
overwriting sgt->nents with 1 (which is probably a separate issue).
FWIW that
From: Tim Gardner
[ Upstream commit 37a1a2e6eeeb101285cd34e12e48a881524701aa ]
Coverity complains of a possible buffer overflow. However,
given the 'static' scope of nvidia_setup_i2c_bus() it looks
like that can't happen after examiniing the call sites.
CID 19036 (#1 of 1): Copy into fixed size
On Tue, 5 Apr 2022 at 11:52, Javier Martinez Canillas
wrote:
>
> On 4/5/22 11:24, Daniel Vetter wrote:
> > On Tue, 5 Apr 2022 at 11:19, Javier Martinez Canillas
>
> [snip]
>
> >>
> >> This is how I think that work, please let me know if you see something
> >> wrong in my logic:
> >>
> >> 1) A PCI
When DMAR / VT-d is enabled, the display engine uses overfetching,
presumably to deal with the increased latency. To avoid display engine
errors and DMAR faults, as a workaround the GGTT is populated with scatch
PTEs when VT-d is enabled. However starting with gen10, Write-combined
writing of scrat
Am 2022-04-05 12:02, schrieb codrin.ciubota...@microchip.com:
On 05.04.2022 12:38, Michael Walle wrote:
Am 2022-04-05 11:23, schrieb codrin.ciubota...@microchip.com:
+ if (dev->use_dma) {
+ dma_buf = i2c_get_dma_safe_msg_buf(m_start, 1);
If you want, you could just dev->bu
Hi Marek,
Thank you for the patch.
On Sun, Feb 13, 2022 at 03:26:48AM +0100, Marek Vasut wrote:
> In rare cases, the bridge may not start up correctly, which usually
> leads to no display output. In case this happens, warn about it in
> the kernel log.
Do you know what this is caused by ? It's a
On Fri, 18 Mar 2022 at 12:25, Dave Stevenson
wrote:
>
> On Fri, 4 Mar 2022 at 15:18, Dave Stevenson
> wrote:
> >
> > Hi All
>
> A gentle ping on this series. Any comments on the approach?
> Thanks.
I realise the merge window has just closed and therefore folks have
been busy, but no responses on
On 4/5/22 13:42, Laurent Pinchart wrote:
Hi Marek,
Hi,
Thank you for the patch.
On Sun, Feb 13, 2022 at 03:26:48AM +0100, Marek Vasut wrote:
In rare cases, the bridge may not start up correctly, which usually
leads to no display output. In case this happens, warn about it in
the kernel log.
Hi Laurent
On Tue, 5 Apr 2022 at 12:42, Laurent Pinchart
wrote:
>
> Hi Marek,
>
> Thank you for the patch.
>
> On Sun, Feb 13, 2022 at 03:26:48AM +0100, Marek Vasut wrote:
> > In rare cases, the bridge may not start up correctly, which usually
> > leads to no display output. In case this happens,
On Tue, 5 Apr 2022 at 13:00, Thomas Hellström
wrote:
>
> When DMAR / VT-d is enabled, the display engine uses overfetching,
> presumably to deal with the increased latency. To avoid display engine
> errors and DMAR faults, as a workaround the GGTT is populated with scatch
> PTEs when VT-d is enabl
On Tue, 5 Apr 2022 at 11:25, Christian König wrote:
>
> Am 29.03.22 um 18:02 schrieb Daniel Vetter:
> > On Mon, Mar 21, 2022 at 02:58:56PM +0100, Christian König wrote:
> > [SNIP]
> >> static unsigned long ttm_bo_io_mem_pfn(struct ttm_buffer_object *bo,
> >> diff --git a/drivers/gpu/drm/vmwgfx/v
On Mon, 4 Apr 2022 at 23:53, Doug Anderson wrote:
>
> Hi,
>
> On Sat, Apr 2, 2022 at 1:26 PM Dmitry Baryshkov
> wrote:
> >
> > On Sat, 2 Apr 2022 at 20:06, Doug Anderson wrote:
> > >
> > > Hi,
> > >
> > > On Sat, Apr 2, 2022 at 3:37 AM Dmitry Baryshkov
> > > wrote:
> > > >
> > > > On 01/04/2022
On Mon, Apr 04, 2022 at 09:44:02PM +0200, Thomas Zimmermann wrote:
> OF framebuffers do not have an underlying device in the Linux
> device hierarchy. Do a regular unregister call instead of hot
> unplugging such a non-existing device. Fixes a NULL dereference.
> An example error message on ppc64le
Hi Dave,
On Tue, Apr 05, 2022 at 01:00:28PM +0100, Dave Stevenson wrote:
> On Tue, 5 Apr 2022 at 12:42, Laurent Pinchart wrote:
> > On Sun, Feb 13, 2022 at 03:26:48AM +0100, Marek Vasut wrote:
> > > In rare cases, the bridge may not start up correctly, which usually
> > > leads to no display outpu
On Tue, Apr 5, 2022 at 3:02 AM Paul Menzel wrote:
>
> Dear Christian,
>
>
> Am 05.04.22 um 08:54 schrieb Christian König:
> > Am 05.04.22 um 08:45 schrieb Paul Menzel:
>
> >> Am 04.04.22 um 23:42 schrieb Philip Yang:
> >>> bo_adev is NULL for system memory mapping to GPU.
> >>>
> >>> Fixes: 05fe8e
Applied. Thanks!
Alex
On Thu, Mar 31, 2022 at 11:00 PM Guo Zhengkui wrote:
>
> Replace `if (!ret)` with `else` for simplification.
>
> Signed-off-by: Guo Zhengkui
> ---
> drivers/gpu/drm/radeon/radeon_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/dr
Hi Daniel,
On Tue, Apr 5, 2022 at 1:48 PM Daniel Vetter wrote:
> On Tue, 5 Apr 2022 at 11:52, Javier Martinez Canillas
> wrote:
> > On 4/5/22 11:24, Daniel Vetter wrote:
> > > On Tue, 5 Apr 2022 at 11:19, Javier Martinez Canillas
> > >> This is how I think that work, please let me know if you se
On Tue, 5 Apr 2022 at 14:08, Laurent Pinchart
wrote:
>
> Hi Dave,
>
> On Tue, Apr 05, 2022 at 01:00:28PM +0100, Dave Stevenson wrote:
> > On Tue, 5 Apr 2022 at 12:42, Laurent Pinchart wrote:
> > > On Sun, Feb 13, 2022 at 03:26:48AM +0100, Marek Vasut wrote:
> > > > In rare cases, the bridge may no
On 4/5/22 12:34, Daniel Vetter wrote:
> On Tue, 5 Apr 2022 at 11:52, Javier Martinez Canillas
> wrote:
[snip]
>>
>> I believe the correct fix would be for the fbdev core to keep a list of
>> the apertures struct that are passed to remove_conflicting_framebuffers(),
>> that way it will know what
Applied. Thanks!
Alex
On Tue, Apr 5, 2022 at 2:04 AM Christian König wrote:
>
> Am 05.04.22 um 00:57 schrieb Tom Rix:
> > Smatch reports these issues
> > si_blit_shaders.c:31:11: warning: symbol 'si_default_state'
> >was not declared. Should it be static?
> > si_blit_shaders.c:253:11: warni
On Tue, Apr 05, 2022 at 03:24:40PM +0200, Geert Uytterhoeven wrote:
> Hi Daniel,
>
> On Tue, Apr 5, 2022 at 1:48 PM Daniel Vetter wrote:
> > On Tue, 5 Apr 2022 at 11:52, Javier Martinez Canillas
> > wrote:
> > > On 4/5/22 11:24, Daniel Vetter wrote:
> > > > On Tue, 5 Apr 2022 at 11:19, Javier Ma
Il 01/04/22 10:13, Yunfei Dong ha scritto:
Will return -EINVAL using standard framework api when test stateless
decoder with cmd VIDIOC_(TRY)DECODER_CMD.
Using another return value to adjust v4l2 compliance test for user
driver(GStreamer/Chrome) won't use decoder cmd.
Fixes: 8cdc3794b2e3 ("medi
Changes in RFC:
- Rebase changes to the latest code base.
- Append rotation config variables with v2 and
remove unused variables.(Dmitry)
- Move pixel_ext setup separately from scaler3 config.(Dmitry)
- Add 270 degree rotation to supported rotation list.(Dmitry)
Changes in V2:
- Remove unused macr
- Some DPU versions support inline rot90. It is supported only for
limited amount of UBWC formats.
- There are two versions of inline rotators, v1 (present on sm8250 and
sm7250) and v2 (sc7280). These versions differ in the list of supported
formats and in the scaler possibilities.
Co-developed-by
Check if the dpu format is supported or not using dpu_find_format.
Co-developed-by: Kalyan Thota
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 22 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++---
2
On 4/5/22 15:25, Dave Stevenson wrote:
On Tue, 5 Apr 2022 at 14:08, Laurent Pinchart
wrote:
Hi Dave,
On Tue, Apr 05, 2022 at 01:00:28PM +0100, Dave Stevenson wrote:
On Tue, 5 Apr 2022 at 12:42, Laurent Pinchart wrote:
On Sun, Feb 13, 2022 at 03:26:48AM +0100, Marek Vasut wrote:
In rare cas
On Tue, 5 Apr 2022 at 16:41, Vinod Polimera wrote:
>
> Check if the dpu format is supported or not using dpu_find_format.
>
> Co-developed-by: Kalyan Thota
> Signed-off-by: Kalyan Thota
> Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_f
On Tue, 5 Apr 2022 at 16:41, Vinod Polimera wrote:
>
> - Some DPU versions support inline rot90. It is supported only for
> limited amount of UBWC formats.
> - There are two versions of inline rotators, v1 (present on sm8250 and
> sm7250) and v2 (sc7280). These versions differ in the list of suppo
On Tue, Apr 5, 2022 at 5:07 AM Grigory Vasilyev wrote:
>
> Variable igp_lane_info always is 0. 0 & any value = 0 and false.
> In this way, all сonditional statements will false.
> Therefore, it is not clear what this code does.
It was leftover from when the code was ported from radeon. The igp
l
On Mon, 4 Apr 2022 at 19:35, Vinod Koul wrote:
>
> Update headers from mesa commit:
>
> commit 28ae397be111c37c6ced397e12d453a7695701bd
> Author: Vinod Koul
> Date: Fri Apr 1 16:53:04 2022 +0530
>
> freedreno/registers: update dsi registers to support dsc
>
> Display Stream co
On Mon, 4 Apr 2022 at 19:35, Vinod Koul wrote:
>
> When DSC is enabled, we need to configure DSI registers accordingly and
> configure the respective stream compression registers.
>
> Add support to calculate the register setting based on DSC params and
> timing information and configure these reg
On Mon, 2022-04-04 at 17:38 +0200, Daniel Vetter wrote:
> On Fri, Apr 01, 2022 at 04:56:00PM -0400, Zack Rusin wrote:
> > From: Zack Rusin
> >
> > Add a few debugfs entries for every used TTM placement that vmwgfx
> > is
> > using. This allows basic tracking of memory usage inside vmwgfx,
> > e.g
Dear Alex,
Am 05.04.22 um 15:14 schrieb Alex Deucher:
On Tue, Apr 5, 2022 at 3:02 AM Paul Menzel wrote:
Am 05.04.22 um 08:54 schrieb Christian König:
Am 05.04.22 um 08:45 schrieb Paul Menzel:
Am 04.04.22 um 23:42 schrieb Philip Yang:
bo_adev is NULL for system memory mapping to GPU.
Fi
Am 2022-04-05 15:58, schrieb codrin.ciubota...@microchip.com:
On 05.04.2022 14:09, Michael Walle wrote:
Am 2022-04-05 12:02, schrieb codrin.ciubota...@microchip.com:
On 05.04.2022 12:38, Michael Walle wrote:
Am 2022-04-05 11:23, schrieb codrin.ciubota...@microchip.com:
+ if (dev->use_dm
Hello Thomas,
On 4/4/22 21:44, Thomas Zimmermann wrote:
> OF framebuffers do not have an underlying device in the Linux
> device hierarchy. Do a regular unregister call instead of hot
> unplugging such a non-existing device. Fixes a NULL dereference.
> An example error message on ppc64le is shown
iommu_get_domain_for_dev() is already perfectly happy to return NULL
if the given device has no IOMMU. Drop the unnecessary check.
Signed-off-by: Robin Murphy
---
drivers/gpu/drm/arm/malidp_planes.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/dr
On Tue, Apr 5, 2022 at 10:03 AM Paul Menzel wrote:
>
> Dear Alex,
>
>
> Am 05.04.22 um 15:14 schrieb Alex Deucher:
> > On Tue, Apr 5, 2022 at 3:02 AM Paul Menzel wrote:
>
> >> Am 05.04.22 um 08:54 schrieb Christian König:
> >>> Am 05.04.22 um 08:45 schrieb Paul Menzel:
> >>
> Am 04.04.22 um 2
Remove the pointless check. If an IOMMU is providing transparent DMA API
ops for any device(s) we care about, the DT code will have enforced the
appropriate probe ordering already.
Signed-off-by: Robin Murphy
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4
1 file changed, 4 deletions(-)
di
Dear Alex,
Am 05.04.22 um 16:13 schrieb Alex Deucher:
On Tue, Apr 5, 2022 at 10:03 AM Paul Menzel wrote:
Am 05.04.22 um 15:14 schrieb Alex Deucher:
On Tue, Apr 5, 2022 at 3:02 AM Paul Menzel wrote:
Am 05.04.22 um 08:54 schrieb Christian König:
Am 05.04.22 um 08:45 schrieb Paul Menzel:
Even if some IOMMU has registered itself on the platform "bus", that
doesn't necessarily mean it provides translation for the device we
care about. Replace iommu_present() with a more appropriate check.
Signed-off-by: Robin Murphy
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
1 file changed, 1 inser
Remove the pointless check. host1x_drm_wants_iommu() cannot return true
unless an IOMMU exists for the host1x platform device, which at the moment
means the iommu_present() test could never fail.
Signed-off-by: Robin Murphy
---
drivers/gpu/drm/tegra/drm.c | 2 +-
1 file changed, 1 insertion(+),
Hi Marek.
On Tue, 5 Apr 2022 at 14:49, Marek Vasut wrote:
>
> On 4/5/22 15:25, Dave Stevenson wrote:
> > On Tue, 5 Apr 2022 at 14:08, Laurent Pinchart
> > wrote:
> >>
> >> Hi Dave,
> >>
> >> On Tue, Apr 05, 2022 at 01:00:28PM +0100, Dave Stevenson wrote:
> >>> On Tue, 5 Apr 2022 at 12:42, Lauren
Even if some IOMMU has registered itself on the platform "bus", that
doesn't necessarily mean it provides translation for the device we
care about. Replace iommu_present() with a more appropriate check.
Signed-off-by: Robin Murphy
---
drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 2 +-
1
On Mon, Apr 4, 2022 at 3:39 PM Michele Ballabio wrote:
>
> On Mon, 4 Apr 2022 13:03:41 -0400
> Alex Deucher wrote:
>
> > On Sun, Apr 3, 2022 at 10:19 AM Michele Ballabio
> > wrote:
> > >
> > > Hi,
> > > I've hit a regression on 5.17.1 (haven't tested 5.17.0, but
> > > 5.16-stable didn't
Defer the IOMMU domain setup until after successfully binding
components, so we can figure out IOMMU support directly from the VOP
devices themselves, rather than manually inferring it from the DT (which
also fails to account for whether the IOMMU driver is actually loaded).
Although this is somewh
On Xe-HP and later devices, we use dedicated compression control
state (CCS) stored in local memory for each surface, to support
the 3D and media compression formats.
The memory required for the CCS of the entire local memory is
1/256 of the local memory size. So before the kernel
boot, the requir
Use faster XY_FAST_COLOR_BLT cmd on graphics version of 12 and more,
for clearing (Zero out) the pages of the newly allocated object.
XY_FAST_COLOR_BLT is faster than the older XY_COLOR_BLT.
v2:
Typo fix at title [Thomas]
v3:
XY_FAST_COLOR_BLT is used only for FLAT_CCS capable gen12+
Signed-
To make it uniform across copy and clear, use the engine offset directly
to calculate the offset in the cmd forming for emit_clear.
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletion
Move the static calculations out of the loops for copy and clear.
v2:
Fix the loss of proper error code on emit_pte
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellstrom (v1)
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 34 -
1 file changed, 17 insertions(+), 17
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
XY_CTRL_SURF_COPY_BLT is a BLT cmd used for reading and writing the
ccs surface
When emit_pte doesn't update any PTE with return value as 0, interpret
it as -EINVAL.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/
Extend the live migrate selftest, to verify the ccs surface clearing
during the Flat-CCS capable lmem obj clear.
v2:
Look at right places for ccs data [Thomas]
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 250 ++---
On Xe-HP and later devices, dedicated compression control state (CCS)
stored in local memory is used for each surface, to support the
3D and media compression formats.
The memory required for the CCS of the entire local memory is 1/256 of
the local memory size. So before the kernel boot, the requi
When we are swapping out the local memory obj on flat-ccs capable platform,
we need to capture the ccs data too along with main meory and we need to
restore it when we are swapping in the content.
When lmem object is swapped into a smem obj, smem obj will
have the extra pages required to hold the
Consider the possible round up happened at obj size alignment to
min_page_size during the obj allocation.
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selft
On 4/4/22 23:26, Javier Martinez Canillas wrote:
> On 4/5/22 08:12, Simon Ser wrote:
>> On Monday, April 4th, 2022 at 23:35, Randy Dunlap
>> wrote:
>>
>>> On 4/4/22 09:04, Simon Ser wrote:
>>>
Both doc patches pushed, thanks. I had to manually edit them because they
wouldn't apply cl
On 4/5/22 16:20, Dave Stevenson wrote:
Hi,
If we can initialise the DSI host before the bridge for the
pre_enable, then all the configuration moves to the atomic_pre_enable
and there should be no need to have the delay.
I can't 100% guarantee that, but one of the folks on the Pi forums is
usin
From: Tvrtko Ursulin
Current processing landscape seems to be more and more composed of pipelines
where computations are done on multiple hardware devices. Furthermore some of
the non-CPU devices, like in this case many GPUs supported by the i915 driver,
actually support priority based scheduling
From: Tvrtko Ursulin
Introduce the concept of context nice value which matches the process
nice.
We do this by extending the struct i915_sched_attr and add a helper
(i915_sched_attr_priority) to be used to convert to effective priority
when used by backend code and for priority sorting.
Context
From: Tvrtko Ursulin
Code added in 71ed60112d5d ("drm/i915: Add kick_backend function to
i915_sched_engine") and ee242ca704d3 ("drm/i915/guc: Implement GuC
priority management") introduced some scheduling related vfuncs which
take integer request priority as argument.
Make them instead take stru
From: Tvrtko Ursulin
Inherit submitter nice at point of request submission to account for
long running processes getting either externally or self re-niced.
Nice value will only apply to requests which originate from user
contexts and have default context priority.
Signed-off-by: Tvrtko Ursulin
On Tuesday, April 5th, 2022 at 16:39, Randy Dunlap
wrote:
> On 4/4/22 23:26, Javier Martinez Canillas wrote:
>
> > On 4/5/22 08:12, Simon Ser wrote:
> >
> > > On Monday, April 4th, 2022 at 23:35, Randy Dunlap rdun...@infradead.org
> > > wrote:
> > >
> > > > On 4/4/22 09:04, Simon Ser wrote:
> >
On Xe-HP and later devices, we use dedicated compression control
state (CCS) stored in local memory for each surface, to support
the 3D and media compression formats.
The memory required for the CCS of the entire local memory is
1/256 of the local memory size. So before the kernel
boot, the requir
To make it uniform across copy and clear, use the engine offset directly
to calculate the offset in the cmd forming for emit_clear.
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletion
Move the static calculations out of the loops for copy and clear.
v2:
Fix the loss of proper error code on emit_pte
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellstrom (v1)
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 34 -
1 file changed, 17 insertions(+), 17
Use faster XY_FAST_COLOR_BLT cmd on graphics version of 12 and more,
for clearing (Zero out) the pages of the newly allocated object.
XY_FAST_COLOR_BLT is faster than the older XY_COLOR_BLT.
v2:
Typo fix at title [Thomas]
v3:
XY_FAST_COLOR_BLT is used only for FLAT_CCS capable gen12+
Signed-
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