On Sat, 26 Mar 2022 22:38:05 -0700, Guenter Roeck wrote:
> > @@ -103,11 +103,16 @@ nvkm_control_mthd_pstate_attr(struct nvkm_control
> > *ctrl, void *data, u32 size)
> > return -EINVAL;
> >
> > if (args->v0.state != NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT) {
> > - l
On Sat, Mar 26, 2022 at 05:22:55PM +0530, kushagra...@outlook.com wrote:
> >From 9a9918b051d5709b5e14ca8afa29f3ef644b8688 Mon Sep 17 00:00:00 2001
> From: Kushagra Verma
> Date: Sat, 26 Mar 2022 16:43:15 +0530
> Subject: [PATCH] Documentation: fixed doc-build warnings
This should not be in the bo
The bug is here:
cstate = to_dpu_crtc_state(drm_crtc->state);
For the drm_for_each_crtc(), just like list_for_each_entry(),
the list iterator 'drm_crtc' will point to a bogus position
containing HEAD if the list is empty or no element is found.
This case must be checked before any use of
The bug is here:
return encoder;
The list iterator value 'encoder' will *always* be set and non-NULL
by drm_for_each_encoder_mask(), so it is incorrect to assume that the
iterator value will be NULL if the list is empty or no element found.
Otherwise it will bypass some NULL checks and lea
The bug is here:
if (nvkm_cstate_valid(clk, cstate, max_volt, clk->temp))
return cstate;
The list iterator value 'cstate' will *always* be set and non-NULL
by list_for_each_entry_from_reverse(), so it is incorrect to assume
that the iterator value will be unchanged if the l
Hi Kishon, Vinod,
On Thu, 2021-06-10 at 17:38 +0800, Liu Ying wrote:
> Hi Kishon, Vinod,
>
> Any follow-up comments/suggestions based on my previous reply?
> Or, perhaps, just keep the patch as-is to support the generic lvds
> phy
> configuration structure?
Ping... Any follow-up comments/suggest
There is a display controller in loongson's LS2K1000 SoC and LS7A1000
bridge chip, the display controller is a PCI device in those chips. It
has two display pipes but with only one hardware cursor. Each way has
a DVO interface which provide RGB888 signals, vertical & horizontal
synchronisations, da
The display controller is a pci device, it is used in ls2k1000 SoC and
LS7A1000 bridge. Its PCI vendor id is 0x0014, its PCI device id is 0x7a06.
In order to let the driver to know which chip the DC is contained in,
the compatible of the display controller is named according to the chip's
name.
Fo
This patch introduce three board specific dts and assign different
model property to them according to the board name on the top overlay
of the PCB.
The model property added is used to provide board specific information,
mips kernel use it as machine name. For example:
$ cat /proc/cpuinfo
system
Add DT bindings and simple usages for Loongson display controller
found in LS7A1000 bridges chip and LS2k1000 SoC.
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
.../loongson/loongson,display-controller.yaml | 322 ++
1 file changed, 322 insertions(+)
create mode 100644
Do
There is a display controller in loongson's LS2K1000 SoC and LS7A1000
bridge chip, the display controller is a PCI device in those chips. It
has two display pipes but with only one hardware cursor. Each way has
a DVO interface which provide RGB888 signals, vertical & horizontal
synchronisations, da
ls3A4000 evb board ship with adv7123 and tfp410 while ls2k1000 PI board
use a DPI panel from FORLINX company and a sii9022 HDMI transmitter.
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
arch/mips/configs/loongson2k_defconfig | 5 +
arch/mips/configs/loongson3_defconfig | 5 +
2 f
This patch add myself as maintainer
My company email is
my personal email is <15330273...@189.cn>
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 10476280acb8..21184d8577f4 100644
--
在 2022/3/27 12:38, Sui Jingfeng 写道:
Add DT bindings and simple usages for Loongson display controller
found in LS7A1000 bridges chip and LS2k1000 SoC.
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
[...]
+
+ - |
+#include
+bus {
+
+#address-cells = <3>;
+#size-ce
.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/intel-lab-lkp/linux/commits/Sui-Jingfeng/drm-loongson-add-drm-driver-for-loongson-display-controller/20220327-194016
base: git://anongit.freedeskt
On Sun, 27 Mar 2022 19:38:43 +0800, Sui Jingfeng wrote:
> Add DT bindings and simple usages for Loongson display controller
> found in LS7A1000 bridges chip and LS2k1000 SoC.
>
> Signed-off-by: Sui Jingfeng <15330273...@189.cn>
> ---
> .../loongson/loongson,display-controller.yaml | 322 +
The display controller is a pci device, it is used in ls2k1000 SoC and
LS7A1000 bridge. Its PCI vendor id is 0x0014, its PCI device id is 0x7a06.
In order to let the driver to know which chip the DC is contained in,
the compatible of the display controller is named according to the chip's
name.
Fo
There is a display controller in loongson's LS2K1000 SoC and LS7A1000
bridge chip, the display controller is a PCI device in those chips. It
has two display pipes but with only one hardware cursor. Each way has
a DVO interface which provide RGB888 signals, vertical & horizontal
synchronisations, da
Add DT bindings and simple usages for Loongson display controller
found in LS7A1000 bridge chip and LS2k1000 SoC.
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
.../loongson/loongson,display-controller.yaml | 321 ++
1 file changed, 321 insertions(+)
create mode 100644
Doc
This patch introduce three board specific dts and assign different
model property to them according to the board name on the top overlay
of the PCB.
The model property added is used to provide board specific information,
mips kernel use it as machine name. For example:
$ cat /proc/cpuinfo
system
There is a display controller in loongson's LS2K1000 SoC and LS7A1000
bridge chip, the display controller is a PCI device in those chips. It
has two display pipes but with only one hardware cursor. Each way has
a DVO interface which provide RGB888 signals, vertical & horizontal
synchronisations, da
This patch add myself as maintainer
My company email is
my personal email is <15330273...@189.cn>
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 10476280acb8..21184d8577f4 100644
--
On 3/26/22 23:59, Xiaomeng Tong wrote:
On Sat, 26 Mar 2022 22:38:05 -0700, Guenter Roeck wrote:
@@ -103,11 +103,16 @@ nvkm_control_mthd_pstate_attr(struct nvkm_control *ctrl,
void *data, u32 size)
return -EINVAL;
if (args->v0.state != NVIF_CONTROL_PSTATE_ATTR_V0_STATE_C
On Sun, 27 Mar 2022 at 08:39, Xiaomeng Tong wrote:
>
> The bug is here:
> return encoder;
>
> The list iterator value 'encoder' will *always* be set and non-NULL
> by drm_for_each_encoder_mask(), so it is incorrect to assume that the
> iterator value will be NULL if the list is empty or no
Hi Christophe
On Mon, Mar 21, 2022 at 02:36:50PM +0100, Christophe Branchereau wrote:
> This driver supports the NewVision NV3052C based LCDs. Right now, it
> only supports the LeadTek LTK035C5444T 2.4" 640x480 TFT LCD panel, which
> can be found in the Anbernic RG-350M handheld console.
>
> Sign
Hi Christophe,
On Mon, Mar 21, 2022 at 03:42:08PM +0100, Christophe Branchereau wrote:
> Sorry I meant "sleep out" not "sleep in" obviously
>
> On Mon, Mar 21, 2022 at 3:39 PM Christophe Branchereau
> wrote:
> >
> > Following the introduction of bridge_atomic_enable in the ingenic
> > drm driver
Based on a6xx_gpu.c, stripped down and updated for a7xx based on the
downstream driver. Implements the minimum to be able to submit commands to
the GPU and use it for userspace driver development. Notably this doesn't
implement support for the GMU (this means that the clock driver needs to
support
These will be used by a7xx, so move them to common code. A6XX_ prefix is
kept because the generic ADRENO_ is already in use.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 17 -
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++
2 files changed, 6 i
The high half of 64-bit registers is always at +1 offset, so change these
helpers to be more convenient by removing the unnecessary argument.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 3 +--
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 27 -
Adds a7xx changes for the kernel driver.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a7xx.xml.h | 666
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 63 +-
2 files changed, 716 insertions(+), 13 deletions(-)
create mode 100644 drivers/gpu/drm/msm/adr
Based on a6xx_gpu.c, stripped down and updated for a7xx based on the
downstream driver. Implements the minimum to be able to submit commands to
the GPU and use it for userspace driver development. Notably this doesn't
implement support for the GMU (this means that the clock driver needs to
support
this series is built around the DisplayPort driver. The dpi/dpintf
driver and the added helper functions are required for the DisplayPort
driver to work.
This v9 is not quite ready yet, as project constraints forces me to
publish v9 this week, I'm sorry if it's not standard practice.
Moreover, it
From: Markus Schneider-Pargmann
DP_INTF is similar to DPI but does not have the exact same feature set
or register layouts.
DP_INTF is the sink of the display pipeline that is connected to the
DisplayPort controller and encoder unit. It takes the same clocks as
DPI.
Signed-off-by: Markus Schnei
From: Markus Schneider-Pargmann
This controller is present on several mediatek hardware. Currently
mt8195 and mt8395 have this controller without a functional difference,
so only one compatible field is added.
The controller can have two forms, as a normal display port and as an
embedded display
This patch adds two helper functions that extract the frequency and word
length from a struct cea_sad.
For these helper functions new defines are added that help translate the
'freq' and 'byte2' fields into real numbers.
Signed-off-by: Markus Schneider-Pargmann
Signed-off-by: Guillaume Ranquet
Add flexibility by moving the dpi limits to the SoC specific config
Signed-off-by: Guillaume Ranquet
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/med
Signed-off-by: Guillaume Ranquet
---
include/drm/drm_edid.h | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 144c495b99c4..5d4d840b9904 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -359,12
From: Markus Schneider-Pargmann
Similar to HDMI, DP uses audio infoframes as well which are structured
very similar to the HDMI ones.
This patch adds a helper function to pack the HDMI audio infoframe for
DP, called hdmi_audio_infoframe_pack_for_dp().
hdmi_audio_infoframe_pack_only() is split in
This phy controller is embedded in the Display Port Controller on mt8195 SoCs.
Signed-off-by: Guillaume Ranquet
---
.../bindings/phy/mediatek,dp-phy.yaml | 43 +++
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.y
Add flexibility by moving the csc_enable bit to SoC specific config
Signed-off-by: Guillaume Ranquet
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/d
From: Markus Schneider-Pargmann
This is a new driver that supports the integrated DisplayPort phy for
mediatek SoCs, especially the mt8195. The phy is integrated into the
DisplayPort controller and will be created by the mtk-dp driver. This
driver expects a struct regmap to be able to work on the
Add flexibility by moving the hvsize mask to SoC specific config
Signed-off-by: Guillaume Ranquet
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
Add flexibility by moving the yuv422 en bit to SoC specific config
Signed-off-by: Guillaume Ranquet
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/dr
Add flexibility by moving the dimension mask to the SoC config
Signed-off-by: Guillaume Ranquet
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediat
This patch adds External DisplayPort support to the mt8195 eDP driver.
Signed-off-by: Guillaume Ranquet
---
drivers/gpu/drm/mediatek/mtk_dp.c | 301 +++---
1 file changed, 278 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c
b/drivers/gpu/dr
Adds a bit of flexibility to support SoCs without swap_input support
Signed-off-by: Guillaume Ranquet
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_
From: Jitao Shi
>From the DP spec 1.4a chapter 3.3, upstream devices should implement
HPD signal de-bouncing on an external connection.
A period of 100ms should be used to detect an HPD connect event.
To cover these cases, HPD de-bounce should be implemented only after
HPD low has been detected f
Adds a bit of flexibility to support SoCs without CK/DE pol support
Signed-off-by: Guillaume Ranquet
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediat
dpintf is the displayport interface hardware unit. This unit is similar
to dpi and can reuse most of the code.
This patch adds support for mt8195-dpintf to this dpi driver. Main
differences are:
- Some features/functional components are not available for dpintf
which are now excluded from code
Add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET
register depending on the color format.
Signed-off-by: Guillaume Ranquet
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/
This patch adds audio support to the DP driver for mt8195 with up to 8
channels.
Signed-off-by: Guillaume Ranquet
---
drivers/gpu/drm/mediatek/mtk_dp.c | 712 +-
1 file changed, 693 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c
b/driv
Add flexibility by moving the swap shift value to SoC specific config
Signed-off-by: Guillaume Ranquet
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index
From: Jitao Shi
DP 1.4a Section 2.8.7.1.5.6.1:
A DP Source device shall retry at least seven times upon receiving
AUX_DEFER before giving up the AUX transaction.
Aux should retry to send msg whether how many bytes.
Signed-off-by: Jitao Shi
Signed-off-by: Guillaume Ranquet
---
drivers/gpu/drm
From: Markus Schneider-Pargmann
This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
It supports the mt8195, the embedded DisplayPort units. It offers
DisplayPort 1.4 with up to 4 lanes.
The driver shares its iomap range with the mtk-dp-phy driver using
the regmap/syscon facility.
On 2022-03-27 9:15, Xiaomeng Tong wrote:
The bug is here:
if (!encoder) {
The list iterator value 'encoder' will *always* be set and non-NULL
by list_for_each_entry(), so it is incorrect to assume that the
iterator value will be NULL if the list is empty or no element
is found.
To fix t
Hi Andrey,
On Tue, 1 Mar 2022 22:26:12 -0500 Andrey Grodzovsky
wrote:
>
> On 2022-03-01 20:31, Stephen Rothwell wrote:
> > Hi all,
> >
> > On Thu, 20 Jan 2022 14:26:39 +1100 Stephen Rothwell
> > wrote:
> >> On Wed, 17 Nov 2021 13:49:26 +1100 Stephen Rothwell
> >> wrote:
> >>> After mergi
Hi Paul,
> -Original Message-
> From: dri-devel On Behalf Of Paul
> Menzel
> Sent: Saturday, March 26, 2022 4:11 PM
> To: Liu, Chuansheng
> Cc: linux-fb...@vger.kernel.org; del...@gmx.de; dri-
> de...@lists.freedesktop.org; tzimmerm...@suse.de; jay...@intworks.biz
> Subject: Re: [PATCH]
[AMD Official Use Only]
Hi Harry,
I have been reminded to do some modifications to the patch format. So the 3/25
it's the date I resent the mail v2.
If the mail title usage is not correct, please let me know.
And about the questions:
" This file lives in DC, which is shared code between Windows
On 2022/3/27 20:54, Jiaxun Yang wrote:
在 2022/3/27 12:38, Sui Jingfeng 写道:
Add DT bindings and simple usages for Loongson display controller
found in LS7A1000 bridges chip and LS2k1000 SoC.
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
[...]
+
+ - |
+ #include
+ bus {
+
+
on Sun, 27 Mar 2022 16:59:28 +0100, Emil Velikov wrote:
> On Sun, 27 Mar 2022 at 08:39, Xiaomeng Tong wrote:
> >
> > The bug is here:
> > return encoder;
> >
> > The list iterator value 'encoder' will *always* be set and non-NULL
> > by drm_for_each_encoder_mask(), so it is incorrect to as
On 2022/3/27 22:02, Rob Herring wrote:
On Sun, 27 Mar 2022 19:38:43 +0800, Sui Jingfeng wrote:
Add DT bindings and simple usages for Loongson display controller
found in LS7A1000 bridges chip and LS2k1000 SoC.
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
.../loongson/loongson,displa
The display controller is a pci device, it is used in ls2k1000 SoC and
LS7A1000 bridge. Its PCI vendor id is 0x0014, its PCI device id is 0x7a06.
In order to let the driver to know which chip the DC is contained in,
the compatible of the display controller is named according to the chip's
name.
Fo
This patch introduce three board specific dts and assign different
model property to them according to the board name on the top overlay
of the PCB.
The model property added is used to provide board specific information,
mips kernel use it as machine name. For example:
$ cat /proc/cpuinfo
system
Add DT bindings and simple usages for Loongson display controller
found in LS7A1000 bridge chip and LS2k1000 SoC.
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
.../loongson/loongson,display-controller.yaml | 321 ++
1 file changed, 321 insertions(+)
create mode 100644
Doc
ls3A4000 evb board ship with adv7123 and tfp410 while ls2k1000 PI board
use a DPI panel from FORLINX company and a sii9022 HDMI transmitter.
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
arch/mips/configs/loongson2k_defconfig | 5 +
arch/mips/configs/loongson3_defconfig | 5 +
2 f
There is a display controller in loongson's LS2K1000 SoC and LS7A1000
bridge chip, the display controller is a PCI device in those chips. It
has two display pipes but with only one hardware cursor. Each way has
a DVO interface which provide RGB888 signals, vertical & horizontal
synchronisations, da
This patch add myself as maintainer
My company email is
my personal email is <15330273...@189.cn>
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 10476280acb8..21184d8577f4 100644
--
From: Fei Yang
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalidate the auxiliary table for
all engines because the
This is a workaround for s3 hang for r7340(amdgpu).
When we test s3 with r7340 on arm64 platform, graphics card will hang up,
the error message are as follows:
Mar 4 01:14:11 greatwall-GW-XX-XXX kernel: [1.599374][ 7] [ T291]
amdgpu :02:00.0: fb0: amdgpudrmfb frame buffer device
Mar
Dear Chuansheng,
Am 28.03.22 um 02:58 schrieb Liu, Chuansheng:
-Original Message-
Sent: Saturday, March 26, 2022 4:11 PM
Am 17.03.22 um 06:46 schrieb Chuansheng Liu:
Easily hit the below list corruption:
==
list_add corruption. prev->next should be next (c0ceb090), but
w
This patch series aims to support the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.
This unit supports MIPI Alliance Specification for Display Serial Interface
(DSI) Specification. This unit provides a
solution for transmitting MIPI DSI compliant digital video and
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das
---
v1->v2:
* Added full path for dsi-controller.yaml
* Modeled DSI + D-PHY as single block and updated reg property
* Fixed typo D_PHY->D-PHY
This driver supports the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.
Signed-off-by: Biju Das
---
v1->v2:
* Rework based on dt-binding change (DSI + D-PHY) as single block
* Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
* Replaced rzg2l_mi
Am 26.03.22 um 21:24 schrieb Melissa Wen:
dcn10_validate_bandwidth is only used on dcn10 files, but is declared in
dcn_calcs files. Rename dcn10_* to dcn_* in calcs, remove DC_FP_* wrapper
inside DML folder and create an specific dcn10_validate_bandwidth in
dcn10_resources that calls dcn_validate
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