Calculate the number of pages in the BO's backing storage from
the size. Remove the npage field.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gem.c | 9 +
drivers/gpu/drm/gma500/gem.h | 1 -
drivers/gpu/drm/gma500/gma_display.c |
Inline psb_gtt_restore() into its only caller in power.c.
Perform the GTT restoration in psb_gem_mm_resume(). The restoration
step is part of GEM anyway and will be moved over at some point.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gtt.c | 15 ++-
The GTT init, fini and resume functions contain both, GTT and GEM,
code. Split each into a separate GTT and a GEM function. The GEM
code is responsible for mmap_mutex and the stolen memory area. The
rest of the functionality is left in GTT functions.
Signed-off-by: Thomas Zimmermann
Acked-by: Pat
The semaphore at struct psb_mmu_driver.sem protects access to the MMU
fields. Additional locking with struct psb_gtt.sem is unnecessary. Remove
the field and related code.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gtt.c | 7 ---
drivers/gpu/d
Move the setup code for GTT/GATT memory ranges into a new helper and
call the function from psb_gtt_init() and psb_gtt_resume(). Removes
code duplication.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/gma500/gtt.c | 153 +++
1 file changed, 64 insertions(+)
Acquire the GTT mutex in psb_gtt_{insert,remove}_pages(). Remove
locking from callers. Also remove the GTT locking around the resume
code. Resume does not run concurrently with other GTT operations.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gem.c | 1
Protect concurrent access to struct psb_gem_object by acquiring
the GEM object's reservation lock; as it's supposed to be. The
use of the GTT mutex can now be moved into GTT code.
Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
---
drivers/gpu/drm/gma500/gem.c | 12
1 f
Quoting Vinod Polimera (2022-03-08 08:54:56)
> Kernel clock driver assumes that initial rate is the
> max rate for that clock and was not allowing it to scale
> beyond the assigned clock value.
How? I see ftbl_disp_cc_mdss_mdp_clk_src[] has multiple frequencies and
clk_rcg2_shared_ops so it doesn'
Hi Doug,
Thank you for the patch.
On Tue, Mar 08, 2022 at 11:06:57AM -0800, Douglas Anderson wrote:
> The bindings for bridge chips should also get the same maintainers
> entry so the right people get notified about bindings changes.
>
> Signed-off-by: Douglas Anderson
Reviewed-by: Laurent Pin
Don't populate the read-only array ODValues on the stack but
instead make it static const. Also makes the object code a little
smaller.
Signed-off-by: Colin Ian King
---
drivers/video/fbdev/kyro/STG4000InitDevice.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video
Am 2022-03-08 um 14:11 schrieb David Yat Sin:
Export dmabuf handles for GTT BOs so that their contents can be accessed
using SDMA during checkpoint/restore.
This deserves a minor version bump. The plugin should depend on that
bumped version when it starts using dmabuf handles for GTT BOs.
Re
Quoting Dan Carpenter (2022-03-07 05:31:05)
> These casts need to happen before the shift. The only time it would
> matter would be if "rev.core" is >= 128. In that case the sign bit
> would be extended and we do not want that.
>
> Fixes: afab9d91d872 ("drm/msm/adreno: Expose speedbin to userspac
Quoting Dmitry Baryshkov (2022-03-03 19:21:02)
> MDP5 and DPU1 both provide the driver handling the MDSS region, which
> handles the irq domain and (incase of DPU1) adds some init for the UBWC
> controller. Unify those two pieces of code into a common driver.
>
> Signed-off-by: Dmitry Baryshkov
>
Quoting Dmitry Baryshkov (2022-03-03 19:21:03)
> Since now there is just one mdss subdriver, drop all the indirection,
> make msm_mdss struct completely opaque (and defined inside msm_mdss.c)
> and call mdss functions directly.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Hello Chen-Yu,
Thanks a lot for your patch.
On 3/8/22 17:07, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai
>
> The SSD130x's command to toggle COM scan direction uses bit 3 and only
> bit 3 to set the direction of the scanout. The driver has an incorrect
> GENMASK(3, 2), causing the setting to be se
Quoting Dmitry Baryshkov (2022-03-03 19:21:04)
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 857eefbb8649..c89de88ed2d1 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -255,3 +258,170 @@ struct msm_mdss *msm_mdss_ini
Quoting Dmitry Baryshkov (2022-03-03 19:21:05)
> Let's make the match's data pointer a (sub-)driver's private data. The
> only user currently is the msm_drm_init() function, using this data to
> select kms_init callback. Pass this callback through the driver's
> private data instead.
>
> Signed-off
Quoting Dmitry Baryshkov (2022-03-03 19:21:06)
> MSM DRM driver already allows one to compile out the DP or DSI support.
> Add support for disabling other features like MDP4/MDP5/DPU drivers or
> direct HDMI output support.
>
> Suggested-by: Stephen Boyd
> Signed-off-by: Dmitry Baryshkov
> ---
R
On 3/8/22 17:07, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai
>
> Currently the ssd130x driver only sets the segment remap setting when
> the device tree requests it; it however does not clear the setting if
> it is not requested. This leads to the setting incorrectly persisting
> if the hardware is
Quoting Dmitry Baryshkov (2022-03-03 23:58:58)
> On Fri, 4 Mar 2022 at 07:31, Stephen Boyd wrote:
> >
> > Quoting Dmitry Baryshkov (2022-03-03 20:23:06)
> > > On Fri, 4 Mar 2022 at 01:32, Stephen Boyd wrote:
> > > >
> > > > Quoting Dmitry Baryshkov (2022-02-16 21:55:27)
> > > > > The only clock f
From: Sean Paul
This patch adds the necessary hooks to make amdgpu aware of privacy
screens. On devices with privacy screen drivers (such as thinkpad-acpi),
the amdgpu driver will defer probe until it's ready and then sync the sw
and hw state on each commit the connector is involved and enabled.
On Tue, 8 Mar 2022 at 21:48, Rob Clark wrote:
>
> From: Rob Clark
>
> Avoid going down devfreq paths on devices where devfreq is not
> initialized.
>
> v2: Change has_devfreq() logic [Dmitry]
>
> Reported-by: Linux Kernel Functional Testing
> Reported-by: Anders Roxell
> Signed-off-by: Rob Clar
Export dmabuf handles for GTT BOs so that their contents can be accessed
using SDMA during checkpoint/restore.
Signed-off-by: David Yat Sin
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 12
include/uapi/linux/kfd_ioctl.h | 3 ++-
2 files changed, 10 insertions(+), 5 dele
Am 2022-03-08 um 16:08 schrieb David Yat Sin:
Export dmabuf handles for GTT BOs so that their contents can be accessed
using SDMA during checkpoint/restore.
Signed-off-by: David Yat Sin
Looks good to me. Please also post a link to the user mode change for this.
Note that the user mode code
On 3/8/22 17:21, Maxime Ripard wrote:
On Tue, Mar 08, 2022 at 03:47:22PM +0100, Marek Vasut wrote:
On 3/8/22 14:49, Maxime Ripard wrote:
On Tue, Mar 08, 2022 at 02:27:40PM +0100, Marek Vasut wrote:
On 3/8/22 13:51, Maxime Ripard wrote:
On Tue, Mar 08, 2022 at 11:29:59AM +0100, Marek Vasut wro
Hi,
On 3/8/22 21:56, Sean Paul wrote:
> From: Sean Paul
>
> This patch adds the necessary hooks to make amdgpu aware of privacy
> screens. On devices with privacy screen drivers (such as thinkpad-acpi),
> the amdgpu driver will defer probe until it's ready and then sync the sw
> and hw state on
On 2022-03-08 17:02, Hans de Goede wrote:
> Hi,
>
> On 3/8/22 21:56, Sean Paul wrote:
>> From: Sean Paul
>>
>> This patch adds the necessary hooks to make amdgpu aware of privacy
>> screens. On devices with privacy screen drivers (such as thinkpad-acpi),
>> the amdgpu driver will defer probe u
Hi,
On 3/8/22 23:07, Harry Wentland wrote:
>
>
> On 2022-03-08 17:02, Hans de Goede wrote:
>> Hi,
>>
>> On 3/8/22 21:56, Sean Paul wrote:
>>> From: Sean Paul
>>>
>>> This patch adds the necessary hooks to make amdgpu aware of privacy
>>> screens. On devices with privacy screen drivers (such as
On Tue, Mar 8, 2022 at 11:28 AM Dmitry Osipenko
wrote:
>
> On 3/8/22 19:29, Rob Clark wrote:
> > On Tue, Mar 8, 2022 at 5:17 AM Dmitry Osipenko
> > wrote:
> >>
> >> Hello,
> >>
> >> This patchset introduces memory shrinker for the VirtIO-GPU DRM driver.
> >> During OOM, the shrinker will release
t; In the optimized case, cfb_imageblit() is now ~2x faster than before.
>
> v3:
> * fix commit description (Pekka)
>
> Signed-off-by: Thomas Zimmermann
> Acked-by: Sam Ravnborg
> Reviewed-by: Javier Martinez Canillas
This patch landed recently in linux next-2022
On Sun, Mar 06, 2022 at 08:04:49PM +0200, Laurent Pinchart wrote:
> On Sun, Mar 06, 2022 at 07:39:03PM +0200, Laurent Pinchart wrote:
> > Add a new dt-bindings/media/video-interfaces.h header that defines
> > macros corresponding to the bus types from media/video-interfaces.yaml.
> > This allows av
On 3/9/22 01:24, Rob Clark wrote:
> On Tue, Mar 8, 2022 at 11:28 AM Dmitry Osipenko
> wrote:
>>
>> On 3/8/22 19:29, Rob Clark wrote:
>>> On Tue, Mar 8, 2022 at 5:17 AM Dmitry Osipenko
>>> wrote:
Hello,
This patchset introduces memory shrinker for the VirtIO-GPU DRM driver.
>>>
On Tue, Mar 8, 2022 at 3:36 PM Dmitry Osipenko
wrote:
>
> On 3/9/22 01:24, Rob Clark wrote:
> > On Tue, Mar 8, 2022 at 11:28 AM Dmitry Osipenko
> > wrote:
> >>
> >> On 3/8/22 19:29, Rob Clark wrote:
> >>> On Tue, Mar 8, 2022 at 5:17 AM Dmitry Osipenko
> >>> wrote:
>
> Hello,
>
> >
On Tue, Mar 8, 2022 at 5:17 AM Dmitry Osipenko
wrote:
>
> Add memory shrinker and new madvise IOCTL to the VirtIO-GPU driver.
> Userspace (BO cache manager of Mesa driver) will mark BOs as "don't need"
> using the new IOCTL to let shrinker purge the marked BOs on OOM, thus
> shrinker will lower me
On 3/8/22 2:57 PM, Nick Desaulniers wrote:
On Thu, Mar 3, 2022 at 12:19 PM wrote:
From: Tom Rix
Clang static analysis reports this issue
anx7625.c:876:13: warning: The left operand of '&' is
a garbage value
if (!(bcap & 0xOA01)) {
^
bcap is only set by a successful call
Hi Dave & Daniel,
Follow-up pull req for v5.18 to pull in some important fixes.
The following changes since commit afab9d91d872819f98a792c32c302d9e3261f1a1:
drm/msm/adreno: Expose speedbin to userspace (2022-02-25 13:29:57 -0800)
are available in the Git repository at:
https://gitlab.freed
Hi Daniel:
On 3/8/22 22:04, Daniel Stone wrote:
On Tue, 8 Mar 2022 at 08:42, Andy Yan wrote:
On 3/7/22 21:09, Daniel Stone wrote:
On Mon, 7 Mar 2022 at 12:18, Andy Yan wrote:
When run a weston 10.0.0:
# export XDG_RUNTIME_DIR=/tmp
# weston --backend=drm-backend.so --use-pixma --tty
Patches that fix and enhance the selftest_lrc
Akeem G Abodunrin (1):
drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing
Chris Wilson (7):
drm/i915/selftests: Exercise relative mmio paths to non-privileged
registers
drm/i915/selftests: Exercise cross-process context isolati
From: Chris Wilson
Verify that context isolation is also preserved when accessing
context-local registers with relative-mmio commands.
Signed-off-by: Chris Wilson
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 88 --
1 file changed, 67 inserti
From: Chris Wilson
Verify that one context running on engine A cannot manipulate another
client's context concurrently running on engine B using unprivileged
access.
Signed-off-by: Chris Wilson
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 275 +-
From: Chris Wilson
When testing whether we can get the GPU to leak information about
non-privileged state, we first need to ensure that the output buffer is
set to a known value as the HW may opt to skip the write into memory for
a non-privileged read of a sensitive register. We chose POISON_INUS
From: Chris Wilson
The lrc_isolation test uses two contexts in order to read from one
context while poisoning from a second. The test verifies that the
writes of the second context do not leak into the first context. This is
done by first recording the register state from context A, forcing a
pre
From: Chris Wilson
In order to keep the context image parser simple, we assume that all
commands follow a similar format. A few, especially not MI commands on
the render engines, have fixed lengths not encoded in a length field.
This caused us to incorrectly skip over 3D state commands, and start
From: Chris Wilson
Even though the initial protocontext we load onto HW has the register
cleared, by the time we save it into the default image, BB_OFFSET has
had the enable bit set. Reclear BB_OFFSET for each new context.
Testcase: igt/i915_selftests/gt_lrc
Signed-off-by: Chris Wilson
Cc: Mik
From: Chris Wilson
Ensure that we always signal the semaphore when timing out, so that if it
happens to be stuck waiting for the semaphore we will quickly recover
without having to wait for a reset.
Reported-by: CQ Tang
Signed-off-by: Chris Wilson
cc: Joonas Lahtinen
Signed-off-by: Ramalingam
From: Akeem G Abodunrin
When bit 19 of MI_LOAD_REGISTER_IMM instruction opcode is set on devices
of tgl+, HW does not care about certain register address offsets, but
instead check the following for valid address ranges on specific engines:
RCS && CCS: BITS(0 - 10)
BCS: BITS(0 - 1
On Tue, Mar 8, 2022 at 6:00 PM Benjamin Gaignard
wrote:
>
>
> Le 08/03/2022 à 10:12, Hsin-Yi Wang a écrit :
> > On Fri, Mar 4, 2022 at 7:25 PM Benjamin Gaignard
> > wrote:
> >>
> >> Le 04/03/2022 à 11:15, xinlei@mediatek.com a écrit :
> >>> From: Xinlei Lee
> >>>
> >>> In upstream-v5.8, dsi_
Hi Daniel:
On 3/9/22 10:03, Andy Yan wrote:
Hi Daniel:
On 3/8/22 22:04, Daniel Stone wrote:
On Tue, 8 Mar 2022 at 08:42, Andy Yan wrote:
On 3/7/22 21:09, Daniel Stone wrote:
On Mon, 7 Mar 2022 at 12:18, Andy Yan wrote:
When run a weston 10.0.0:
# export XDG_RUNTIME_DIR=/tmp
# wes
The Renesas RZ/V2L SoC (a.k.a R9A07G054) has a Bifrost Mali-G31 GPU,
add a compatible string for it.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documen
From: Shashank Sharma
This patch adds a work function, which sends a GPU reset
uevent and some contextual infomration, like the PID and
some status flags. This work should be scheduled during
a GPU reset.
The userspace can do some recovery and post-processing work
based on this event and informa
|Acked-by: Nirmoy Das |
On 03/03/2022 11:02, Matthew Auld wrote:
Currently this will enforce both 2M alignment and padding for any LMEM
pages inserted into the GGTT. However, this was only meant to be applied
to the compact-pt layout with the ppGTT. For the GGTT we can reduce the
alignment and p
From: Shashank Sharma
This patch adds a new sysfs event, which will indicate
the userland about a GPU reset, and can also provide
some information like:
- process ID of the process involved with the GPU reset
- process name of the involved process
- the GPU status info (using flags)
This patch a
Hi,
Maybe it would be a good idea to state the intended use-case in the
commit message? And explain why the current (driver-specific IIRC) APIs
aren't enough?
Since this introduces new uAPI, can you point to a user-space patch
which uses the new uAPI? See this link for more info on DRM user-space
Hi Marek,
On Fri, Mar 4, 2022 at 5:55 AM Marek Vasut wrote:
>
> The driver currently hard-codes DSI lane count to two, however the chip
> is capable of operating in 1..4 DSI lanes mode. Parse 'data-lanes' DT
> property and program the result into DSI_CTRL register.
>
> Signed-off-by: Marek Vasut
On Fri, Mar 4, 2022 at 5:55 AM Marek Vasut wrote:
>
> The chip contains fractional PLL, however the driver currently hard-codes
> one specific PLL setting. Implement generic PLL parameter calculation code,
> so any DPI panel with arbitrary pixel clock can be attached to this bridge.
>
> The datash
In __spi_validate, there's a validation that no partial transfers
are accepted (xfer->len % w_size must be zero). When
max_chunk is not a multiple of bpw (e.g.max_chunk = 65535,
bpw = 16), the transfer will be rejected.
This patch clamps max_chunk to the word size, preventing
the transfer from bei
On Fri, 4 Mar 2022 15:46:07 +0100
Maxime Ripard wrote:
> Indeed, while the input buffer uses 0xff for the X component, we'll get
> back 0x00 from the hardware, and thus the hashes are not identical. We
> can force the hardware to always set it to 0xff, but that doesn't seem
> right. It would make
This reverts commit c206c7faeb3263a7cc7b4de443a3877cd7a5e74b.
In order to avoid any probe ordering issues, the I2C based downstream
bridge drivers now register and attach the DSI devices at the probe
instead of doing it on drm_bridge_function.attach().
Examples of those commits are:
commit <6ef7
devm_drm_of_get_bridge is capable of looking up the downstream
bridge and panel and trying to add a panel bridge if the panel
is found.
Replace explicit finding calls with devm_drm_of_get_bridge.
Reviewed-by: Guido Günther
Signed-off-by: Jagan Teki
---
Changes for v3:
- drop panel.h
- collect G
devm_drm_of_get_bridge is capable of looking up the downstream
bridge and panel and trying to add a panel bridge if the panel
is found.
Replace explicit finding calls with devm_drm_of_get_bridge.
Cc: Chun-Kuang Hu
Cc: Philipp Zabel
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
Changes
devm_drm_of_get_bridge is capable of looking up the downstream
bridge and panel and trying to add a panel bridge if the panel
is found.
Replace explicit finding calls with devm_drm_of_get_bridge.
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
Changes for v2:
- split the patch
drivers/gp
devm_drm_of_get_bridge is capable of looking up the downstream
bridge and panel and trying to add a panel bridge if the panel
is found.
Replace explicit finding calls with devm_drm_of_get_bridge.
Signed-off-by: Jagan Teki
---
Changes for v3:
- drop panel.h
Changes for v2:
- split the patch
dri
devm_drm_of_get_bridge is capable of looking up the downstream
bridge and panel and trying to add a panel bridge if the panel
is found.
Replace explicit finding calls with devm_drm_of_get_bridge.
Signed-off-by: Jagan Teki
---
Changes for v3:
- drop panel.h
Changes for v2:
- split the patch
dri
devm_drm_of_get_bridge is capable of looking up the downstream
bridge and panel and trying to add a panel bridge if the panel
is found.
Replace explicit finding calls with devm_drm_of_get_bridge.
Signed-off-by: Jagan Teki
---
Changes for v3:
- drop panel.h
Changes for v2:
- split the patch
dri
devm_drm_of_get_bridge is capable of looking up the downstream
bridge and panel and trying to add a panel bridge if the panel
is found.
Replace explicit finding calls with devm_drm_of_get_bridge.
Cc: Linus Walleij
Signed-off-by: Jagan Teki
---
Changes for v3:
- fix commit head
- drop panel.h
-
Hi,
On 07/03/2022 11:56, Wan Jiabing wrote:
Fix the following coccicheck warning:
./drivers/gpu/drm/omapdrm/omap_overlay.c:89:22-25: ERROR: r_ovl is NULL
but dereferenced.
Here should be ovl->idx rather than r_ovl->idx.
Signed-off-by: Wan Jiabing
---
drivers/gpu/drm/omapdrm/omap_overlay.c |
Hi Daniel:
On 3/7/22 21:09, Daniel Stone wrote:
Hi Andy,
On Mon, 7 Mar 2022 at 12:18, Andy Yan wrote:
On 2/25/22 15:51, Sascha Hauer wrote:
The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
It replaces the VOP unit found in the older Rockchip SoCs.
This driver has been d
Hi Sam and Patrik
Am 07.03.22 um 22:02 schrieb Patrik Jakobsson:
On Mon, Mar 7, 2022 at 8:07 PM Sam Ravnborg wrote:
Hi Thomas,
One comment below.
On Sun, Mar 06, 2022 at 09:36:15PM +0100, Thomas Zimmermann wrote:
The current implementation of psb_gtt_init() also does resume
handling. Move
On 17/02/2022 18:21, Ivaylo Dimitrov wrote:
Hi Tomi,
On 17.02.22 г. 15:03 ч., Tomi Valkeinen wrote:
Hi Ivaylo,
On 19/01/2022 12:23, Ivaylo Dimitrov wrote:
This patch series fixes excessive DMM or CMA usage of GEM buffers
leading to
various runtime allocation failures. The series enables daily
Acked-by: Michal Mrozek
-Original Message-
From: Harrison, John C
Sent: Thursday, March 3, 2022 11:38 PM
To: intel-...@lists.freedesktop.org
Cc: DRI-Devel@Lists.FreeDesktop.Org; Harrison, John C
; Ceraolo Spurio, Daniele
; Mrozek, Michal
Subject: [PATCH v3 4/4] drm/i915: Improve long
On Mon, 7 Mar 2022 21:52:40 +0100
Geert Uytterhoeven wrote:
> Introduce fourcc codes for color-indexed frame buffer formats with two,
> four, and sixteen colors, and provide a mapping from bit per pixel and
> depth to fourcc codes.
>
> As the number of bits per pixel is less than eight, these r
On Mon, 7 Mar 2022 21:52:43 +0100
Geert Uytterhoeven wrote:
> Traditionally, the first channel has been called the "red" channel, but
> the fourcc values for single-channel "red" formats can also be used for
> other light-on-dark displays, like grayscale.
>
> Signed-off-by: Geert Uytterhoeven
Hello Thomas,
On 3/3/22 21:58, Thomas Zimmermann wrote:
> Rework the fbdev deferred-I/O to not interfere with fields of struct
> page. Make the code more flexible and implement GEM SHMEM mmap on top
> of it.
>
> This patchset removes the need for a special shadow framebuffer for
> fbdev mmap when
From: Changcheng Deng
Use min_t() in order to make code cleaner.
Reported-by: Zeal Robot
Signed-off-by: Changcheng Deng
---
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
b/drivers/
On Mon, 7 Mar 2022 21:53:17 +0100
Geert Uytterhoeven wrote:
> Add fourcc codes for color-indexed frame buffer formats with two, four,
> and sixteen colors. Add support for creating buffers using these
> formats.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> include/drm/drm_fourcc.h | 5
On Mon, 7 Mar 2022 21:53:42 +0100
Geert Uytterhoeven wrote:
> DRM formats are defined to be little-endian, unless the
> DRM_FORMAT_BIG_ENDIAN flag is set. Hence writes of multi-byte pixel
> values need to take endianness into account.
>
> Introduce a cpu_to_le32() helper to convert 32-bit valu
On 3/3/22 21:58, Thomas Zimmermann wrote:
> Don't select shadow buffering for the fbdev console explicitly. The
> fbdev emulation's heuristic will enable it for any framebuffer with
> .dirty callback.
>
Indeed it does. Not related to your series but looking at this
patch I noticed that drivers/gpu
On 03/03/2022 22:37, john.c.harri...@intel.com wrote:
From: John Harrison
A workaround was added to the driver to allow OpenCL workloads to run
'forever' by disabling pre-emption on the RCS engine for Gen12.
It is not totally unbound as the heartbeat will kick in eventually
and cause a reset
On 03/03/2022 22:37, john.c.harri...@intel.com wrote:
From: John Harrison
GuC converts the pre-emption timeout and timeslice quantum values into
clock ticks internally. That significantly reduces the point of 32bit
overflow. On current platforms, worst case scenario is approximately
110 seco
Hi Javier
Am 08.03.22 um 10:13 schrieb Javier Martinez Canillas:
Hello Thomas,
On 3/3/22 21:58, Thomas Zimmermann wrote:
Rework the fbdev deferred-I/O to not interfere with fields of struct
page. Make the code more flexible and implement GEM SHMEM mmap on top
of it.
This patchset removes the
An issue[1] related to how the V4L2_FWNODE_BUS_TYPE_PARALLEL flag is mis-used
was found in recent addition to the anx7625 driver.
As used currently CPI (camera parallel interface) and DPI
(display parallel interface) would share the
V4L2_FWNODE_BUS_TYPE_PARALLEL enum. I think that would be perfect
Revert DPI support from binding.
DPI support relies on the bus-type enum which does not yet support
Mipi DPI, since no v4l2_fwnode_bus_type has been defined for this
bus type.
When DPI for anx7625 was initially added, it assumed that
V4L2_FWNODE_BUS_TYPE_PARALLEL was the correct bus type for
repr
This reverts commit 32568ae37596b529628ac09b875f4874e614f63f.
Signed-off-by: Robert Foss
Reviewed-by: Chen-Yu Tsai
Reviewed-by: Laurent Pinchart
---
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-k
On 3/8/22 09:03, Jagan Teki wrote:
Hi,
[...]
@@ -314,7 +321,9 @@ static const struct drm_bridge_funcs chipone_bridge_funcs =
{
static int chipone_parse_dt(struct chipone *icn)
{
struct device *dev = icn->dev;
+ struct device_node *endpoint;
struct drm_panel *panel;
Hi
Am 08.03.22 um 10:31 schrieb Javier Martinez Canillas:
On 3/3/22 21:58, Thomas Zimmermann wrote:
Don't select shadow buffering for the fbdev console explicitly. The
fbdev emulation's heuristic will enable it for any framebuffer with
.dirty callback.
Indeed it does. Not related to your ser
On 3/8/22 10:56, Thomas Zimmermann wrote:
> Hi
>
> Am 08.03.22 um 10:31 schrieb Javier Martinez Canillas:
>> On 3/3/22 21:58, Thomas Zimmermann wrote:
>>> Don't select shadow buffering for the fbdev console explicitly. The
>>> fbdev emulation's heuristic will enable it for any framebuffer with
>>>
Le 08/03/2022 à 10:12, Hsin-Yi Wang a écrit :
On Fri, Mar 4, 2022 at 7:25 PM Benjamin Gaignard
wrote:
Le 04/03/2022 à 11:15, xinlei@mediatek.com a écrit :
From: Xinlei Lee
In upstream-v5.8, dsi_enable will operate panel_enable, but this
modification has been moved in v5.9. In order to
On Mon, 7 Mar 2022 at 16:49, Robert Foss wrote:
>
> On Mon, 7 Mar 2022 at 07:12, Chen-Yu Tsai wrote:
> >
> > On Sun, Mar 06, 2022 at 07:13:30PM +0200, Laurent Pinchart wrote:
> > > Hello Xin,
> > >
> > > (Question for Rob below, and I'm afraid this is urgent as we need to
> > > merge a fix in v5.
On Tue, Mar 8, 2022 at 3:19 PM Marek Vasut wrote:
>
> On 3/8/22 09:03, Jagan Teki wrote:
>
> Hi,
>
> [...]
>
> >> @@ -314,7 +321,9 @@ static const struct drm_bridge_funcs
> >> chipone_bridge_funcs = {
> >> static int chipone_parse_dt(struct chipone *icn)
> >> {
> >> struct device *de
On Mon, Mar 07, 2022 at 10:11:19PM +, David Laight wrote:
> From: Christoph Hellwig
> > Sent: 07 March 2022 15:57
> >
> > On Mon, Mar 07, 2022 at 03:29:35PM +0200, Jarkko Sakkinen wrote:
> > > So what would you suggest to sort out the issue? I'm happy to go with
> > > ioctl if nothing else is
On 3/8/22 09:07, Jagan Teki wrote:
On Fri, Mar 4, 2022 at 5:55 AM Marek Vasut wrote:
The chip contains fractional PLL, however the driver currently hard-codes
one specific PLL setting. Implement generic PLL parameter calculation code,
so any DPI panel with arbitrary pixel clock can be attached
+Cc: Helge
Maybe you can pick this up?
On Fri, Mar 04, 2022 at 09:34:14PM +0200, Andy Shevchenko wrote:
> In the fbtft_init_display() the init sequence is printed for
> the debug purposes. Unfortunately the current code doesn't take
> into account that values in the buffer are of the s16 type.
>
On Tue, 08 Mar 2022, xinlei.lee wrote:
> On Fri, 2022-03-04 at 13:51 +0200, Jani Nikula wrote:
>> Please also prefix cover letters with drm/mediatek if that's the only
>> place you're touching.
>
> Thanks for your review.
> Is your suggestion for me to put the fix id on the cover ?
Heh, it's not
On 3/8/22 11:07, Jagan Teki wrote:
On Tue, Mar 8, 2022 at 3:19 PM Marek Vasut wrote:
On 3/8/22 09:03, Jagan Teki wrote:
Hi,
[...]
@@ -314,7 +321,9 @@ static const struct drm_bridge_funcs chipone_bridge_funcs =
{
static int chipone_parse_dt(struct chipone *icn)
{
struct dev
On Fri, 04 Mar 2022, Matt Roper wrote:
> On Fri, Mar 04, 2022 at 12:13:12PM +0200, Jani Nikula wrote:
>> On Thu, 03 Mar 2022, Matt Roper wrote:
>> > From: Akeem G Abodunrin
>> >
>> > Starting with DG2, preemption can no longer be controlled using userspace
>> > on a per-context basis. Instead, t
On Sun, Feb 13, 2022 at 08:41:39AM +0100, Christophe JAILLET wrote:
> Use devm_add_action_or_reset() instead of devm_add_action()+hand writing
> what is done in the release function, should an error occur.
>
> This is more straightforward and saves a few lines of code.
>
> While at it, remove a u
On Tue, Mar 08, 2022 at 12:18:25PM +0200, Andy Shevchenko wrote:
> +Cc: Helge
>
> Maybe you can pick this up?
>
> On Fri, Mar 04, 2022 at 09:34:14PM +0200, Andy Shevchenko wrote:
You sent this less than a week ago! Please relax, staging driver
patches are way down my list of priorities at the m
On Sun, 13 Feb 2022, Christophe JAILLET wrote:
> Use devm_add_action_or_reset() instead of devm_add_action()+hand writing
> what is done in the release function, should an error occur.
>
> This is more straightforward and saves a few lines of code.
>
> While at it, remove a useless test in devm_
On Fri, 04 Mar 2022, John Harrison wrote:
> On 3/4/2022 03:59, Jani Nikula wrote:
>> On Thu, 24 Feb 2022, john.c.harri...@intel.com wrote:
>> There are a plethora of static inlines in the guc .c files, and this
>> adds more. How about just letting the compiler decide what's the best
>> course of a
On Mon, 28 Feb 2022 19:14:36 +0100, Jernej Skrabec wrote:
> It turns out that DE3 manual has inverted YUV and YVU format numbers for
> P010 and P210. Invert them.
>
> This was tested by playing video decoded to P010 and additionally
> confirmed by looking at BSP driver source.
>
>
> [...]
Appli
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