On 2/18/2022 1:33 PM, john.c.harri...@intel.com wrote:
From: John Harrison
GuC converts the pre-emption timeout and timeslice quantum values into
clock ticks internally. That significantly reduces the point of 32bit
overflow. On current platforms, worst case scenario is approximately
110 sec
On Mon, Feb 21, 2022 at 6:41 AM Akhil P Oommen wrote:
>
> Use a gpu name which is sprintf'ed from the chipid for 7c3 gpu instead of
> hardcoding one. This helps to avoid code churn in case of a gpu rename.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> drivers/gpu/drm/msm/adreno/adreno_device.c |
On Mon, Feb 21, 2022 at 6:41 AM Akhil P Oommen wrote:
>
> This series supercedes [1]. Major change in this series is that it is now
> optional to include a gpu name in the gpu-list. This helps to avoid the
> confusion when we have different SKUs with different gpu names. And also
> I am pretty hap
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as the limit
for how many context ids are available.
I think this could be slightly reworded to make it clear that the
numbers are not changing. Maybe add so
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The LRC descriptor pool is going away. Further, the function that was
populating it was also doing a bunch of logic about the context
registration sequence. So, split that code apart into separate state
setup and try
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined that the actual
registration needs to be delayed and the descriptor would be wiped
out. This is ineff
Thanks for letting me know! I will try for a different solution.
On 2022-02-22 11:24 a.m., Thomas Hellström (Intel) wrote:
Hi, Michael,
On 2/22/22 18:26, Michael Cheng wrote:
This patch removes logic for wbinvd_on_all_cpus and brings in
drm_cache.h. This header has the logic that outputs a war
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The LRC descriptor pool is going away. So, stop naming context ids as
descriptor pool indecies.
While at it, add a bunch of missing line feeds to some error messages.
Signed-off-by: John Harrison
Reviewed-by: Dan
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The CTB registration process changed significantly a while back using
a single KLV based H2G. So drop the original and now obsolete H2G
definitions.
The GuC specs has those defines marked as deprecated since v63 and
On 2/17/2022 3:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Some G2H handlers were reading the context id field from the payload
before checking the payload met the minimum length required.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
While double-che
On 2/11/2022 5:04 PM, john.c.harri...@intel.com wrote:
From: John Harrison
It is possible for reset notifications to arrive for a context that is
in the process of being banned. So don't flag these as an error, just
report it as informational (because it is still useful to know that
resets a
On Tue, Feb 22, 2022 at 09:27:23AM +0100, Jan Kara wrote:
> On Thu 17-02-22 20:10:03, Byungchul Park wrote:
> > [7.009608] ===
> > [7.009613] DEPT: Circular dependency has been detected.
> > [7.009614] 5.17.0-rc1-00014-g8a599299c0cb-dirty
On 2/22/2022 17:39, Ceraolo Spurio, Daniele wrote:
On 2/11/2022 5:04 PM, john.c.harri...@intel.com wrote:
From: John Harrison
It is possible for reset notifications to arrive for a context that is
in the process of being banned. So don't flag these as an error, just
report it as informational
On 2/22/2022 01:52, Tvrtko Ursulin wrote:
On 18/02/2022 21:33, john.c.harri...@intel.com wrote:
From: John Harrison
GuC converts the pre-emption timeout and timeslice quantum values into
clock ticks internally. That significantly reduces the point of 32bit
overflow. On current platforms, worst
On 2/22/2022 16:52, Ceraolo Spurio, Daniele wrote:
On 2/18/2022 1:33 PM, john.c.harri...@intel.com wrote:
From: John Harrison
GuC converts the pre-emption timeout and timeslice quantum values into
clock ticks internally. That significantly reduces the point of 32bit
overflow. On current platfo
On 2/22/2022 01:53, Tvrtko Ursulin wrote:
On 18/02/2022 21:33, john.c.harri...@intel.com wrote:
From: John Harrison
Compute workloads are inherently not pre-emptible on current hardware.
Thus the pre-emption timeout was disabled as a workaround to prevent
unwanted resets. Instead, the hang det
On 09 2月 22 14:53:19, Cai Huoqing wrote:
> The nouveau driver depends on include/linux/list.h instead of
> nvif/list.h, so remove the obstacle-nvif/list.h.
>
> Signed-off-by: Cai Huoqing
> ---
Ping :)
> drivers/gpu/drm/nouveau/include/nvif/list.h | 353
> 1 file changed, 353
e-handling/20220222-212043
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: mips-allmodconfig
(https://download.01.org/0day-ci/archive/20220223/202202231024.8sblrlyr-...@intel.com/config)
compiler: mips-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
From: Evan Quan
[ Upstream commit 0136f5844b006e2286f873457c3fcba8c45a3735 ]
Correct the UMD pstate profiling clocks for Dimgrey Cavefish and Beige
Goby.
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../amd/pm/swsmu/smu11/sie
From: Evan Quan
[ Upstream commit 0136f5844b006e2286f873457c3fcba8c45a3735 ]
Correct the UMD pstate profiling clocks for Dimgrey Cavefish and Beige
Goby.
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../amd/pm/swsmu/smu11/sie
On 2/22/2022 03:19, Tvrtko Ursulin wrote:
On 18/02/2022 21:33, john.c.harri...@intel.com wrote:
From: John Harrison
Compute workloads are inherantly not pre-emptible for long periods on
current hardware. As a workaround for this, the pre-emption timeout
for compute capable engines was disabled
On 19/02/2022 21:33, Rob Clark wrote:
From: Rob Clark
Avoid going down devfreq paths on devices where devfreq is not
initialized.
Reported-by: Linux Kernel Functional Testing
Reported-by: Anders Roxell
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 31 +++
On Tue, Feb 22, 2022 at 09:27:23AM +0100, Jan Kara wrote:
> On Thu 17-02-22 20:10:03, Byungchul Park wrote:
> > [7.009608] ===
> > [7.009613] DEPT: Circular dependency has been detected.
> > [7.009614] 5.17.0-rc1-00014-g8a599299c0cb-dirty
Hi Tvrtko,
>
> On 18/02/2022 03:47, Kasireddy, Vivek wrote:
> > Hi Tvrtko,
> >
> >>
> >> On 17/02/2022 07:50, Vivek Kasireddy wrote:
> >>> While looking for next holes suitable for an allocation, although,
> >>> it is highly unlikely, make sure that the DECLARE_NEXT_HOLE_ADDR
> >>> macro is using
On Tue, Feb 22, 2022 at 11:44:54PM +0100, Linus Walleij wrote:
> On Tue, Feb 22, 2022 at 11:19 PM Douglas Anderson
> wrote:
> >
> > The PM Runtime docs say:
> > Drivers in ->remove() callback should undo the runtime PM changes done
> > in ->probe(). Usually this means calling pm_runtime_disab
Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache. Thanks Tvrtko for the suggestion.
v3 (Michael
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deleti
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range.
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert addi
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
v2(Michael Cheng): Use sizeof(*addr) instead of sizeof(addr) to get the
actual size of the page. Thanks to Matt Roper for
pointing
Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
This will prevent compile errors on non-x86 platforms.
Signed-off-by: Michael Cheng
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_execli
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
v4(Michae
Hey,
> The connector/encoder funcs you do have to pass to
> drm_writeback_connector_init() can't use any of the shared driver
> infrastructure that assume a certain inheritance.
>
> See also my reply to Laurent [1].
>
> > It well might be that we all misunderstand your design. Do you have a
> >
Hi Jiawei,
can you take a look at this? The kernel build robots screaming that this
breaks the V3D build. Probably just a typo or missing include.
I would rather like to push this sooner than later.
Thanks,
Christian.
Am 21.02.22 um 16:51 schrieb kernel test robot:
Hi Jiawei,
Thank you fo
[AMD Official Use Only]
Hi Christian,
I noticed that and it has been fixed with the latest patch.
And I pushed it to amd-staging-drm-next already.
Best regards,
Jiawei
-Original Message-
From: Koenig, Christian
Sent: Wednesday, February 23, 2022 3:12 PM
To: kernel test robot ; Gu, Jia
Well that's bad. This should not be pushed to amd-staging-drm-next at all.
This patch is touching multiple drivers and therefore needs to go
upstream through drm-misc-next.
Alex can you drop that one before you send out a pull request? I'm going
to cherry-pick it over to drm-misc-next.
Than
Dear Qiang,
Am 22.02.22 um 03:46 schrieb Qiang Yu:
Workstation application ANSA/META v21.1.4 get this error dmesg when
running CI test suite provided by ANSA/META:
[drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't update BO_VA (-16)
This is caused by:
1. create a 256MB buffer in invisible VR
On 18/02/2022 14:30, Vinod Polimera wrote:
- Some DPU versions support inline rot90. It is supported only for
limited amount of UBWC formats.
- There are two versions of inline rotators, v1 (present on sm8250 and
sm7250) and v2 (sc7280). These versions differ in the list of supported
formats and
On Wed, Feb 23, 2022 at 3:47 PM Paul Menzel wrote:
>
> Dear Qiang,
>
>
> Am 22.02.22 um 03:46 schrieb Qiang Yu:
> > Workstation application ANSA/META v21.1.4 get this error dmesg when
> > running CI test suite provided by ANSA/META:
> > [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't update BO
201 - 239 of 239 matches
Mail list logo
