Pass negotiated bridge state, which now optionally contains required DSI bus
clock, into dw_mipi_dsi_get_lane_mbps(). The dw_mipi_dsi_get_lane_mbps() is
a misnomer, it is also responsible for configuration of the bridge PLL and
thus also configuration of the clock the bridge outputs on the DSI bus.
Extend struct drm_bus_cfg with a clock field. This makes it possible for an
upstream bridge (further from scanout engine) to indicate to a downstream
bridge which frequency it expects on a link. This is particularly useful in
case of DSI bridges which derive their own internal clock from the DSI HS
The TC358767/TC358867/TC9595 are all capable of operating without RefClk
Xtal in DSI-to-DPI mode. In this mode of operation, the chip PLLs are fed
with clock derived from the DSI HS clock.
The SYSPLL is fed from DSI HS clock divided by 2*7 and the resulting clock
must match the allowed RefClk supp
The bridge_state now contains clock frequency required by the next bridge.
This information is optional, since very few drivers pass this information
now. In case the required clock frequency is part of bridge state, use it
for the DSI bus clock frequency, otherwise fall back to the old guesswork.
The bridge clock configuration should happen in atomic_enable
instead of mode_set callback, since that is where the current
state of the bridge is available. Move the clock configuration
into atomic_enable callback.
Signed-off-by: Marek Vasut
Cc: Laurent Pinchart
Cc: Maxime Ripard
Cc: Neil Arms
Pass the entire struct drm_bus_cfg {} to select_bus_fmt_recursive()
instead of only u32 out_bus_fmt which contains only the pixel format.
This would permit passing more bus format data around during the
bridge-to-bridge format negotiation.
Signed-off-by: Marek Vasut
Cc: Laurent Pinchart
Cc: Maxi
Add new .atomic_get_input_bus_cfgs callback into struct drm_bridge_funcs {}.
This is an extended version of .atomic_get_input_bus_fmts callback which
only returns list of bus formats supported by a bridge and provides no way
to e.g. limit clock frequency required between neighboring bridges.
The n
Quoting Dmitry Baryshkov (2022-02-11 14:40:04)
> It is possible to supply display-connector (bridge) to the DP interface,
> add support for parsing it too.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Stephen Boyd
Hi,
On Thu, Feb 10, 2022 at 3:58 AM Sankeerth Billakanti
wrote:
>
> Add support in the DP driver to utilize the custom eDP panels
> from drm/panels.
>
> An eDP panel is always connected to the platform. So, the eDP
> connector can be reported as always connected. The display mode
> will be source
On Thu, Jan 06, 2022 at 04:55:36PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Similar to AMD commit
874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the
infrastructure added in previous patches, we add basic client info
and GPU engine utilisation for i915.
Example of the
On 2/14/2022 17:11, Daniele Ceraolo Spurio wrote:
Move initialization of submission-related spinlock, lists and workers to
init_early. This fixes an issue where if the GuC init fails we might
still try to get the lock in the context cleanup code. Note that it is
safe to call the GuC context clean
Quoting Dmitry Baryshkov (2022-02-18 14:32:53)
> On 19/02/2022 00:31, Kuogee Hsieh wrote:
> >
> > On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
> >> There is little point in having both connector and root bridge
> >> implementation in the same driver. Move connector's functionality to the
> >> brid
On Sat, Jan 29, 2022 at 2:26 AM Linus Walleij wrote:
> On Mon, Jan 3, 2022 at 12:40 PM Linus Walleij
> wrote:
>
> > A code drop from Sony Mobile reveals that the ACX424 panels are
> > built around the Novatek NT35560 panel controllers so just bite
> > the bullet and rename the driver and all bas
On Sat, Feb 19, 2022 at 12:17:52AM +0530, Ramalingam C wrote:
> From: Ayaz A Siddiqui
>
> Xe-HP and latest devices support Flat CCS which reserved a portion of
> the device memory to store compression metadata, during the clearing of
> device memory buffer object we also need to clear the associa
Quoting Maxime Ripard (2022-01-25 06:15:40)
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 6a98291350b6..2664aaab8068 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -2,6 +2,7 @@
> # common clock types
> obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-
Quoting Maxime Ripard (2022-01-25 06:15:44)
> index 266e8de3cb51..f365dac7be17 100644
> --- a/include/linux/clk.h
> +++ b/include/linux/clk.h
> @@ -1005,6 +1005,17 @@ static inline struct clk *clk_get_optional(struct
> device *dev, const char *id)
> return clk;
> }
>
> +/**
> + * clk_dr
On Sat, 19 Feb 2022 at 03:55, Stephen Boyd wrote:
>
> Quoting Dmitry Baryshkov (2022-02-18 14:32:53)
> > On 19/02/2022 00:31, Kuogee Hsieh wrote:
> > >
> > > On 2/11/2022 2:40 PM, Dmitry Baryshkov wrote:
> > >> There is little point in having both connector and root bridge
> > >> implementation in
Quoting Laurent Pinchart (2022-02-14 01:45:56)
> Hi Maxime and Stephen,
>
> We have recently posted a driver for the BCM2711 Unicam CSI-2 receiver
> (see [1]) which is a perfect candidate for this API, as it needs a
> minimum rate for the VPU clock. Any chance we can get this series merged
> ? :-)
Quoting Maxime Ripard (2022-02-10 02:19:16)
> Hi Stephen,
>
> On Tue, Jan 25, 2022 at 03:15:39PM +0100, Maxime Ripard wrote:
> > Hi,
> >
> > This is a follow-up of the discussion here:
> > https://lore.kernel.org/linux-clk/20210319150355.xzw7ikwdaga2dwhv@gilmour/
> >
> > and here:
> > https://lo
On 2/18/22 18:34, Lucas Stach wrote:
Hi
[...]
drivers/gpu/drm/bridge/tc358767.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/bridge/tc358767.c
b/drivers/gpu/drm/bridge/tc358767.c
index 522c2c4d8514f..01d11adee6c74 100644
--- a/drivers/gpu/
On 19/02/2022 02:56, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-02-11 14:40:02)
In commit 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display
enable and disable") the DP driver received a drm_bridge instance, which
is always attached to the encoder as a root bridge. However it
On 2/18/22 10:35 AM, Felix Kuehling wrote:
Am 2022-02-18 um 12:39 schrieb t...@redhat.com:
From: Tom Rix
Clang static analysis reports this problem
kfd_chardev.c:2327:2: warning: 1st function call argument
is an uninitialized value
kvfree(bo_privs);
^~~~
If the copy_fro
On 2/18/22 18:49, Lucas Stach wrote:
Am Freitag, dem 18.02.2022 um 02:00 +0100 schrieb Marek Vasut:
The TC358767/TC358867/TC9595 are all capable of operating either from
attached Xtal or from DSI clock lane clock. In case the later is used,
all I2C accesses will fail until the DSI clock lane is
Quoting Kuogee Hsieh (2022-02-17 13:36:25)
> The “DP timing” requires the active region to be defined in the
> bottom-right corner of the frame dimensions which is different
> with DSI. Therefore both display_h_end and display_v_end need
> to be adjusted accordingly. However current implementation
Quoting Kuogee Hsieh (2022-02-17 13:36:26)
> To improve code readability, this patch replace BIT(x) with
> correspond register bit define string
>
> Signed-off-by: Kuogee Hsieh
> ---
Reviewed-by: Stephen Boyd
Quoting Kuogee Hsieh (2022-02-17 13:36:27)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 0d315b4..0c22839 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -217,6
Quoting Kuogee Hsieh (2022-02-17 13:36:28)
> Widebus feature will transmit two pixel data per pixel clock to interface.
> This feature now is required to be enabled to easy migrant to higher
s/migrant/migrate/?
> resolution applications in future. However since some legacy chipsets
s/in/in the/
Am 2022-02-18 um 21:34 schrieb Tom Rix:
On 2/18/22 10:35 AM, Felix Kuehling wrote:
Am 2022-02-18 um 12:39 schrieb t...@redhat.com:
From: Tom Rix
Clang static analysis reports this problem
kfd_chardev.c:2327:2: warning: 1st function call argument
is an uninitialized value
kvfree(bo_pr
On 2/18/22 19:38, Lucas Stach wrote:
[...]
@@ -502,8 +548,10 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk,
u32 pixelclock)
/*
* refclk * mul / (ext_pre_div * pre_div)
* should be in
Signed-off-by: Paul Menzel
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 63a089992645..430e56583751 100644
--- a/drivers/gpu/drm/amd/amdgpu/am
On Thu, Feb 17, 2022 at 06:09:53PM +, Matthew Auld wrote:
On Thu, 17 Feb 2022 at 17:55, Lucas De Marchi wrote:
This was useful for early development of lmem, but it's not used
anymore, so remove it.
v2: Remove unneeded fields from struct intel_memory_region
Cc: Chris Wilson
Cc: Matthew
Hi Sascha:
On 2/18/22 16:00, Sascha Hauer wrote:
On Fri, Feb 18, 2022 at 11:50:32AM +0800, Andy Yan wrote:
Hi Sascha:
On 2/17/22 22:06, Heiko Stübner wrote:
Am Donnerstag, 17. Februar 2022, 14:58:23 CET schrieb Sascha Hauer:
Hi Andy,
Please trim the context in your answers to the relevant p
On Fri, Feb 18, 2022 at 11:50:32AM +0800, Andy Yan wrote:
> Hi Sascha:
>
> On 2/17/22 22:06, Heiko Stübner wrote:
> > Am Donnerstag, 17. Februar 2022, 14:58:23 CET schrieb Sascha Hauer:
> > > Hi Andy,
> > >
> > > Please trim the context in your answers to the relevant parts, it makes
> > > it eas
Hi
Am 17.02.22 um 17:12 schrieb Geert Uytterhoeven:
Hi Thomas,
Thanks for your review!
On Thu, Feb 17, 2022 at 3:57 PM Thomas Zimmermann wrote:
Am 15.02.22 um 17:52 schrieb Geert Uytterhoeven:
Add support for color-indexed frame buffer formats with two, four, and
sixteen colors to the DRM f
On 2022-02-17 at 21:39:16 -0800, Lucas De Marchi wrote:
> On Tue, Feb 01, 2022 at 04:11:22PM +0530, Ramalingam C wrote:
> > Details of the 64k pagesize support added as part of DG2 enabling and its
> > implicit impact on the uAPI.
> >
> > v2: improvised the Flat-CCS documentation [Danvet & CQ]
> >
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