While looking for next holes suitable for an allocation, although,
it is highly unlikely, make sure that the DECLARE_NEXT_HOLE_ADDR
macro is using a valid node before it extracts the rb_node from it.
Cc: Tvrtko Ursulin
Cc: Christian König
Signed-off-by: Vivek Kasireddy
---
drivers/gpu/drm/drm_
The first patch is a drm core patch that replaces the for loop in
drm_mm_insert_node_in_range() with the iterator and would not
cause any functional changes. The second patch is a i915 driver
specific patch that also uses the iterator but solves a different
problem.
v2:
- Added a new patch to this
This iterator relies on drm_mm_first_hole() and drm_mm_next_hole()
functions to identify suitable holes for an allocation of a given
size by efficiently traversing the rbtree associated with the given
allocator.
It replaces the for loop in drm_mm_insert_node_in_range() and can
also be used by drm
On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
more framebuffers/scanout buffers results in only one that is mappable/
fenceable. Therefore, pageflipping between these 2 FBs where only one
is mappable/fenceable creates latencies large enough to miss alternate
vblanks thereby
If the previous transfer didn't end with a command without DP_AUX_I2C_MOT,
the next read trasnfer will miss the first byte. But if the command in
previous transfer is requested with length 0, it's a no-op to anx7625
since it can't process this command. anx7625 requires the last command
to be read c
From: Rob Clark
From: Rob Clark
With system suspend using pm_runtime_force_suspend() we can't rely on
the pm_runtime_get_if_in_use() trick to deal with devfreq callbacks
after (or racing with) suspend. So flush any pending idle or boost
work in the suspend path.
Signed-off-by: Rob Clark
---
Without DRM_GEM_CMA_HELPER i.MX8MQ DCSS won't build. This needs to be
there.
Signed-off-by: Rudi Heitbaum
---
drivers/gpu/drm/imx/dcss/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/imx/dcss/Kconfig b/drivers/gpu/drm/imx/dcss/Kconfig
index 7374f1952762..5c2b2277afbf
Add a new dw_hdmi_plat_data struct and new compatible for rk3568.
Signed-off-by: Benjamin Gaignard
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 31 +
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
This is v6 of adding RK356x VOP2 support. Biggest change this time is
that I no longer modify struct drm_encoder, instead the rockchip drivers
now embed struct drm_encoder in a rockchip specific struct.
Sascha
Changes since v5:
- Add new patch to fix dw-hdmi of_graph binding
- Drop "drm/encoder:
"vpll" is a misnomer. A clock input to a device should be named after
the usage in the device, not after the clock that drives it. On the
rk3568 the same clock is driven by the HPLL.
To fix that, this patch renames the vpll clock to ref clock. The clock
name "vpll" is left for compatibility to old
From: Douglas Anderson
Jitter was improved by lowering the MPLL bandwidth to account for high
frequency noise in the rk3288 PLL. In each case MPLL bandwidth was
lowered only enough to get us a comfortable margin. We believe that
lowering the bandwidth like this is safe given sufficient testing.
This enabled the VOP2 display controller along with hdmi and the
required port routes which is enough to get a picture out of the
hdmi port of the board.
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v5:
- Drop reg property from single endpoint node
Changes since v4:
The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
The binding differs slightly from the existing VOP binding, so add a new
binding file for it.
Signed-off-by: Sascha Hauer
Reviewed-by: Rob Herring
---
Notes:
Changes since v5:
- Add Robs Reviewed-by:
Change
Add support for the HDMI port found on RK3568.
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v5:
- Drop unnecessary #size-cells/#address-cells from nodes with only single
endpoint
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 33 +++-
1 file changed, 32 inserti
From: Michael Riesch
Enable the RK356x Video Output Processor (VOP) 2 on the Pine64
Quartz64 Model A.
Signed-off-by: Michael Riesch
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v5:
- Drop reg property from single endpoint node
Changes since v4:
- Sort nodes alphab
The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs needed
for the HDMI port. add support for these to the driver for boards which
have them supplied by switchable regulators.
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++--
1
From: Douglas Anderson
The previous tables for mpll_cfg and curr_ctrl were created using the
20-pages of example settings provided by the PHY vendor. Those
example settings weren't particularly dense, so there were places
where we were guessing what the settings would be for 10-bit and
12-bit (n
The reference clock for the HDMI controller has been renamed to 'ref',
the previous 'vpll' name is only left for compatibility in the driver.
Rename the clock to the new name.
Signed-off-by: Sascha Hauer
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 delet
The rk3568 HDMI has an additional clock that needs to be enabled for the
HDMI controller to work. The purpose of that clock is not clear. It is
named "hclk" in the downstream driver, so use the same name.
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v5:
- Use devm_clk_get_optiona
None of the upstream device tree files has a "unwedge" pinctrl
specified. Make it optional.
Signed-off-by: Sascha Hauer
Acked-by: Rob Herring
---
Notes:
Changes since v4:
- Add Robs Ack
.../devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml | 1 +
1 file changed, 1 insertion
From: Andy Yan
The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
It replaces the VOP unit found in the older Rockchip SoCs.
This driver has been derived from the downstream Rockchip Kernel and
heavily modified:
- All nonstandard DRM properties have been removed
- dropped str
The VOP2 is the display output controller on the RK3568. Add the node
for it to the dtsi file along with the required display-subsystem node
and the iommu node.
Signed-off-by: Sascha Hauer
Acked-by: Rob Herring
---
Notes:
Changes since v4:
- Add Robs Ack
Changes since v3:
-
Current port description doesn't cover all possible cases. It currently
expects one single port with two endpoints.
When the HDMI connector is described in the device tree there can be two
ports, first one going to the VOP and the second one going to the connector.
Also on SoCs which only have a
From: Nickey Yang
add 594Mhz configuration parameters in rockchip_phy_config
Signed-off-by: Nickey Yang
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v3:
- new patch
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/dr
"vpll" is a misnomer. A clock input to a device should be named after
the usage in the device, not after the clock that drives it. On the
rk3568 the same clock is driven by the HPLL.
This patch adds "ref" as a new alternative clock name for "vpll"
Signed-off-by: Sascha Hauer
Acked-by: Rob Herring
The rk3568 HDMI has an additional clock that needs to be enabled for the
HDMI controller to work. The purpose of that clock is not clear. It is
named "hclk" in the downstream driver, so use the same name.
Signed-off-by: Sascha Hauer
Acked-by: Rob Herring
---
Notes:
Changes since v4:
- A
The VOP2 driver needs rockchip specific information for a drm_encoder.
This patch creates a struct rockchip_encoder with a struct drm_encoder
embedded in it. This is used throughout the rockchip driver instead of
struct drm_encoder directly.
The information the VOP2 drivers needs is the of_graph
With upcoming VOP2 support VOP won't be the only choice anymore, so make
the VOP driver optional.
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/Kconfig| 8
drivers/gpu/drm/rockchip/Makefile | 3 ++-
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +-
3 f
The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs
needed for the HDMI port. Add the binding for these supplies.
Signed-off-by: Sascha Hauer
Acked-by: Rob Herring
---
Notes:
Changes since v4:
- Add Robs Ack
.../bindings/display/rockchip/rockchip,dw-hdmi.yaml | 11
The driver checks if the pixel clock of the given mode matches an entry
in the mpll config table. The frequencies in the mpll table are meant as
a frequency range up to which the entry works, not as a frequency that
must match the pixel clock. The downstream Kernel also does not have
this check, so
From: Benjamin Gaignard
Define a new compatible for rk3568 HDMI.
This version of HDMI hardware block needs two new clocks hclk_vio and hclk
to provide phy reference clocks.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Rob Herring
Signed-off-by: Sascha Hauer
---
.../devicetree/bindings/displ
On Thu, Feb 17, 2022 at 04:22:25PM +0800, Hsin-Yi Wang wrote:
> If the previous transfer didn't end with a command without DP_AUX_I2C_MOT,
> the next read trasnfer will miss the first byte. But if the command in
> previous transfer is requested with length 0, it's a no-op to anx7625
> since it can'
On 16/02/2022 15:01, Sui Jingfeng wrote:
>
> On 2022/2/3 16:50, Krzysztof Kozlowski wrote:
>> On Thu, 3 Feb 2022 at 09:26, Sui Jingfeng <15330273...@189.cn> wrote:
>>> From: suijingfeng
>>>
>>> The display controller is a pci device, its vendor id is 0x0014
>>> its device id is 0x7a06.
>> The sam
Hi
Am 16.02.22 um 18:41 schrieb Lucas De Marchi:
First the simplest ones:
- iosys_map_memset(): when abstracting system and I/O memory,
just like the memcpy() use case, memset() also has dedicated
functions to be called for using IO memory.
- iosys_map_memcpy
On 16/02/2022 19:17, Sui Jingfeng wrote:
> From: suijingfeng
>
> The display controller is a pci device, its PCI vendor id is 0x0014
> its PCI device id is 0x7a06.
>
> 1) In order to let the lsdc kms driver to know which chip the DC is
>contained in, we add different compatible for different
On 16/02/2022 19:17, Sui Jingfeng wrote:
> From: suijingfeng
>
> Signed-off-by: suijingfeng
> Signed-off-by: Sui Jingfeng <15330273...@189.cn>
> ---
> MAINTAINERS | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ea3e6c914384..3f5e13a6358b 1006
drm-misc-next has changed this doc comment. Can you rebase your changes?
Any any case, r-b me.
[1]:
https://cgit.freedesktop.org/drm/drm-misc/commit/?id=a3574119826d9a4ef807fb973cf5150c3b90da43
d6ebae3137a51b
>> commit: 7ca6504c36709f35c4cc38ae6acc1c9c3d72136f [4/8] Merge remote-tracking
>> branch 'drm-misc/drm-misc-next' into drm-tip
>> config: mips-buildonly-randconfig-r002-20220217
>> (https://download.01.org/0day-ci/archive/20220217/202202171455.bclm1ybc-...@intel.com/config)
>&
Workstation application ANSA/META get this error dmesg:
[drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't update BO_VA (-16)
This is caused by:
1. create a 256MB buffer in invisible VRAM
2. CPU map the buffer and access it causes vm_fault and try to move
it to visible VRAM
3. force visible VR
On 17/02/2022 07:50, Vivek Kasireddy wrote:
While looking for next holes suitable for an allocation, although,
it is highly unlikely, make sure that the DECLARE_NEXT_HOLE_ADDR
macro is using a valid node before it extracts the rb_node from it.
Was the need for this just a consequence of insuf
: 7ca6504c36709f35c4cc38ae6acc1c9c3d72136f [4/8] Merge remote-tracking
branch 'drm-misc/drm-misc-next' into drm-tip
config: mips-buildonly-randconfig-r002-20220217
(https://download.01.org/0day-ci/archive/20220217/202202171455.bclm1ybc-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/ll
Am 17.02.22 um 10:04 schrieb Qiang Yu:
Workstation application ANSA/META get this error dmesg:
[drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't update BO_VA (-16)
This is caused by:
1. create a 256MB buffer in invisible VRAM
2. CPU map the buffer and access it causes vm_fault and try to move
On 17/02/2022 07:50, Vivek Kasireddy wrote:
On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
more framebuffers/scanout buffers results in only one that is mappable/
fenceable. Therefore, pageflipping between these 2 FBs where only one
is mappable/fenceable creates latencies
On 06/02/2022 09:00, Andreas Kemnade wrote:
> Add a binding for the Electrophoretic Display Controller found at least
> in the i.MX6.
> The timing subnode is directly here to avoid having display parameters
> spread all over the plate.
>
> Supplies are organized the same way as in the fbdev driver
: e141e36b2871c529379f7ec7d5d6ebae3137a51b
commit: 7ca6504c36709f35c4cc38ae6acc1c9c3d72136f [4/8] Merge remote-tracking
branch 'drm-misc/drm-misc-next' into drm-tip
config: mips-buildonly-randconfig-r002-20220217
(https://download.01.org/0day-ci/archive/20220217/202202171455.bclm1ybc-...@intel.com/config)
compi
Vinod,
On 2022-02-10 16:04:23, Vinod Koul wrote:
> When DSC is enabled, we need to configure DSI registers accordingly and
> configure the respective stream compression registers.
>
> Add support to calculate the register setting based on DSC params and
> timing information and configure these re
Hi Mario,
On Wed, Feb 16, 2022 at 10:50:31AM -0600, Limonciello, Mario wrote:
> On 2/16/2022 08:44, Alex Deucher wrote:
> > On Wed, Feb 16, 2022 at 9:34 AM Mika Westerberg
> > wrote:
> > >
> > > Hi all,
> > >
> > > On Tue, Feb 15, 2022 at 01:07:00PM -0600, Limonciello, Mario wrote:
> > > > On 2
On 2/17/22 10:25, Lucas De Marchi wrote:
> On Thu, Feb 17, 2022 at 10:00:42AM +0100, Javier Martinez Canillas wrote:
[snip]
>>> this is now called iosys_map in drm-intel... drm-tip will need a fixup
>>> for the merge.
>>>
>>
>> I thought that the drm-intel tree was only for Intel DRM drivers chan
On Thu, Feb 17, 2022 at 5:15 PM Christian König
wrote:
>
> Am 17.02.22 um 10:04 schrieb Qiang Yu:
> > Workstation application ANSA/META get this error dmesg:
> > [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't update BO_VA (-16)
> >
> > This is caused by:
> > 1. create a 256MB buffer in invisi
On 16/02/2022 18:15, Vinay Belgaumkar wrote:
SLPC unset param H2G only needs one parameter - the id of the
param.
Fixes: 025cb07bebfa ("drm/i915/guc/slpc: Cache platform frequency limits")
How serious is this? Does it need backporting? If so:
Cc: # v5.15+
?
Regards,
Tvrtko
Suggested-b
Hi
Am 17.02.22 um 10:25 schrieb Lucas De Marchi:
[...]
$ git grep "TODO: Use mapping abstraction properly" | wc -l
15
If you point me the proper way, I'll be happy to post a patch to
change it.
It depends what you want to do with the address. There are APIs to copy
from/to. I also added a fe
tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI
head: b56d8d7bad86a9badc1d1b9ea2d1730fa1d3978b
commit: b56d8d7bad86a9badc1d1b9ea2d1730fa1d3978b [1/1] drm/i915: Add DG2 PCI IDs
config: x86_64-randconfig-a011
(https://download.01.org/0day-ci/archive/20220217
On Tue, 15 Feb 2022 17:52:19 +0100
Geert Uytterhoeven wrote:
> Introduce fourcc codes for color-indexed frame buffer formats with two,
> four, and sixteen color, and provide a suitable mapping from bit per
> pixel and depth to fourcc codes.
>
> As the number of bits per pixel is less than eight,
Am 17.02.22 um 10:40 schrieb Qiang Yu:
On Thu, Feb 17, 2022 at 5:15 PM Christian König
wrote:
Am 17.02.22 um 10:04 schrieb Qiang Yu:
Workstation application ANSA/META get this error dmesg:
[drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't update BO_VA (-16)
This is caused by:
1. create a 25
On 2/17/22 10:41, Thomas Zimmermann wrote:
> Hi
>
> Am 17.02.22 um 10:25 schrieb Lucas De Marchi:
> [...]
>>> $ git grep "TODO: Use mapping abstraction properly" | wc -l
>>> 15
>>>
>>> If you point me the proper way, I'll be happy to post a patch to
>>> change it.
>>
>> It depends what you want t
On Tue, 15 Feb 2022 17:52:25 +0100
Geert Uytterhoeven wrote:
> Introduce fourcc codes for single-channel frame buffer formats with two,
> four, and sixteen intensity levels. Traditionally, the first channel
> has been called the "red" channel, but the fourcc can also be used for
> other light-on
On Tue, 15 Feb 2022 17:52:26 +0100
Geert Uytterhoeven wrote:
> Introduce a fourcc code for a single-channel frame buffer format with two
> darkness levels. This can be used for two-level dark-on-light displays.
>
> As the number of bits per pixel is less than eight, this relies on
> proper bloc
Hi,
On Tuesday, February 15th, 2022 at 17:52, Geert Uytterhoeven
wrote:
> Introduce a fourcc code for a single-channel frame buffer format with two
> darkness levels. This can be used for two-level dark-on-light displays.
The previous patches introduce C1 and R1. Do we really need D1? Can't
we
On Thu, Feb 17, 2022 at 5:46 PM Christian König
wrote:
>
> Am 17.02.22 um 10:40 schrieb Qiang Yu:
> > On Thu, Feb 17, 2022 at 5:15 PM Christian König
> > wrote:
> >> Am 17.02.22 um 10:04 schrieb Qiang Yu:
> >>> Workstation application ANSA/META get this error dmesg:
> >>> [drm:amdgpu_gem_va_ioctl
Reviewed-by: Simon Ser
On Wed, 16 Feb 2022 09:39:22 +0100
Geert Uytterhoeven wrote:
> Fix a misspelling of "palette" in a comment.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> include/uapi/linux/fb.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/uapi/linux/fb.h b/include/uapi/lin
Hi Dave & Daniel,
Here is the first drm-intel-gt-next feature PR towards v5.18.
For DG2 adds subplatform G12, missing workarounds and fixes GuC
loading on ARM64. C0/D0 stepping info added for RPL-S.
For uAPI enables support for simple parallel submission with
execlists which was previously enabl
Improve the performance of sys_imageblit() by manually unrolling
the inner blitting loop and moving some invariants out. The compiler
failed to do this automatically. The resulting binary code was even
slower than the cfb_imageblit() helper, which uses the same algorithm,
but operates on I/O memory
Optimize performance of the fbdev console for the common case of
software-based clearing and image blitting.
The commit descripton of each patch contains resuls os a simple
microbenchmark. I also tested the full patchset's effect on the
console output by printing directory listings (i7-4790, FullH
Improve the performance of sys_fillrect() by using word-aligned
32/64-bit mov instructions. While the code tried to implement this,
the compiler failed to create fast instructions. The resulting
binary instructions were even slower than cfb_fillrect(), which
uses the same algorithm, but operates on
Hi Dave, Daniel,
An assortment of fixes for -rc5, mostly display and one for the TTM
backend.
Contains a merge of two trivial GVT fixes as well which came via GVT pull
request.
Regards,
Tvrtko
drm-intel-fixes-2022-02-17:
- GVT kerneldoc cleanup. (Randy Dunlap)
- GVT Kconfig should depend on
Am 17.02.22 um 11:13 schrieb Qiang Yu:
On Thu, Feb 17, 2022 at 5:46 PM Christian König
wrote:
Am 17.02.22 um 10:40 schrieb Qiang Yu:
On Thu, Feb 17, 2022 at 5:15 PM Christian König
wrote:
Am 17.02.22 um 10:04 schrieb Qiang Yu:
Workstation application ANSA/META get this error dmesg:
[drm:
Hi Pekka,
On Thu, Feb 17, 2022 at 11:10 AM Pekka Paalanen wrote:
> On Tue, 15 Feb 2022 17:52:26 +0100
> Geert Uytterhoeven wrote:
> > Introduce a fourcc code for a single-channel frame buffer format with two
> > darkness levels. This can be used for two-level dark-on-light displays.
> >
> > As
Add device pointer so scheduler's printing can use
DRM_DEV_ERROR() instead, which makes life easier under multiple GPU
scenario.
v2: amend all calls of drm_sched_init()
Signed-off-by: Jiawei Gu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
drivers/gpu/drm/etnaviv/etnaviv_sched.c | 2
Hi Marijn,
On 17-02-22, 10:27, Marijn Suijten wrote:
> Vinod,
>
> On 2022-02-10 16:04:23, Vinod Koul wrote:
> > When DSC is enabled, we need to configure DSI registers accordingly and
> > configure the respective stream compression registers.
> >
> > Add support to calculate the register setting
There is a display controller in loongson's LS2K1000 SoC and LS7A1000
bridge chip, it is a PCI device in those chips. It has two display
pipes but with only one hardware cursor. Each way has a DVO interface
which provide RGB888 signals, vertical & horizontal synchronisations,
data enable and the pi
From: suijingfeng
There is a display controller in loongson's LS2K1000 SoC and LS7A1000
bridge chip, it is a PCI device in those chips. It has two display
pipes but with only one hardware cursor. Each way has a DVO interface
which provide RGB888 signals, vertical & horizontal synchronisations,
da
From: suijingfeng
Add DT documentation for loongson display controller found in
LS2K1000, LS2K0500, LS7A1000 and LS7A2000.
v2: DT binding docs and includes should be a separate patch,
fix a warnning because of that.
Signed-off-by: suijingfeng
Signed-off-by: Sui Jingfeng <15330273...@189.cn
From: suijingfeng
v2: Fix warnnings reported by checkpatch script
Signed-off-by: suijingfeng
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ea3e6c914384..abf7a2d6c94d 100644
--- a/MAI
From: suijingfeng
The display controller is a pci device, its PCI vendor id is 0x0014
its PCI device id is 0x7a06.
1) In order to let the driver to know chip which the DC is contained in,
the compatible string is updated according to the chip's name.
2) Add display controller device node for
On 17/02/2022 11:55, Sui Jingfeng wrote:
> From: suijingfeng
>
> Add DT documentation for loongson display controller found in
> LS2K1000, LS2K0500, LS7A1000 and LS7A2000.
>
> v2: DT binding docs and includes should be a separate patch,
> fix a warnning because of that.
>
> Signed-off-by: s
On Thu, Feb 17, 2022 at 6:39 PM Christian König
wrote:
>
>
>
> Am 17.02.22 um 11:13 schrieb Qiang Yu:
> > On Thu, Feb 17, 2022 at 5:46 PM Christian König
> > wrote:
> >> Am 17.02.22 um 10:40 schrieb Qiang Yu:
> >>> On Thu, Feb 17, 2022 at 5:15 PM Christian König
> >>> wrote:
> Am 17.02.22 u
> - for (j = k; j--; ) {
> - shift -= ppw;
> - end_mask = tab[(*src >> shift) & bit_mask];
> - *dst++ = (end_mask & eorx) ^ bgx;
> - if (!shift) {
> - shift = 8;
> -
On 2022/2/17 16:42, Krzysztof Kozlowski wrote:
.../boot/dts/loongson/loongson64-2k1000.dtsi | 8 ++
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 7 +-
4 files changed, 140 insertions(+), 5 deletions(-)
create mode 100644
Documentation/devicetree/bindings/display/loongson/loongson
Hi Marijn,
On 11-12-21, 01:03, Marijn Suijten wrote:
> > +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
> > + int pic_width, int pic_height)
>
> This function - adopted from downstream - does not seem to perform a
> whole lot, especially withou
Hi Dave and Daniel,
here's drm-misc-fixes for this week.
Best regards
Thomas
drm-misc-fixes-2022-02-17:
* drm/cma-helper: Set VM_DONTEXPAND
* drm/atomic: Fix error handling in drm_atomic_set_mode_for_crtc()
The following changes since commit 9da1e9ab82c92d0e89fe44cad2cd7c2d18d64070:
drm/roc
On 2022/2/17 18:57, Krzysztof Kozlowski wrote:
On 17/02/2022 11:55, Sui Jingfeng wrote:
From: suijingfeng
Add DT documentation for loongson display controller found in
LS2K1000, LS2K0500, LS7A1000 and LS7A2000.
v2: DT binding docs and includes should be a separate patch,
fix a warnning
On Thu, 17 Feb 2022 10:21:15 +0100
Krzysztof Kozlowski wrote:
> On 06/02/2022 09:00, Andreas Kemnade wrote:
> > Add a binding for the Electrophoretic Display Controller found at least
> > in the i.MX6.
> > The timing subnode is directly here to avoid having display parameters
> > spread all over
On 17/02/2022 12:31, Andreas Kemnade wrote:
> On Thu, 17 Feb 2022 10:21:15 +0100
> Krzysztof Kozlowski wrote:
>
>> On 06/02/2022 09:00, Andreas Kemnade wrote:
>>> Add a binding for the Electrophoretic Display Controller found at least
>>> in the i.MX6.
>>> The timing subnode is directly here to a
On 10/02/2022 07:19, Thomas Hellström wrote:
It's unclear what reference the initial vma kref refernce refers to.
A vma can have multiple weak references, the object vma list,
the vm's bound list and the GT's closed_list, and the initial vma
reference can be put from lookups of all these lists.
Hi Sascha:
On 2/17/22 16:29, Sascha Hauer wrote:
From: Andy Yan
The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
It replaces the VOP unit found in the older Rockchip SoCs.
This driver has been derived from the downstream Rockchip Kernel and
heavily modified:
- All nonsta
Hi
Am 17.02.22 um 12:05 schrieb Gerd Hoffmann:
- for (j = k; j--; ) {
- shift -= ppw;
- end_mask = tab[(*src >> shift) & bit_mask];
- *dst++ = (end_mask & eorx) ^ bgx;
- if (!shift) {
-
Am 17.02.22 um 11:58 schrieb Qiang Yu:
On Thu, Feb 17, 2022 at 6:39 PM Christian König
wrote:
Am 17.02.22 um 11:13 schrieb Qiang Yu:
On Thu, Feb 17, 2022 at 5:46 PM Christian König
wrote:
Am 17.02.22 um 10:40 schrieb Qiang Yu:
On Thu, Feb 17, 2022 at 5:15 PM Christian König
wrote:
Am 17
17.02.2022 11:29, Sascha Hauer пишет:
> The rk3568 HDMI has an additional clock that needs to be enabled for the
> HDMI controller to work. The purpose of that clock is not clear. It is
> named "hclk" in the downstream driver, so use the same name.
Have you checked that DSI works without the enabl
Hi,
On 19/01/2022 12:23, Ivaylo Dimitrov wrote:
On devices with DMM, all allocations are done through either DMM or TILER.
DMM/TILER being a limited resource means that such allocations will start
to fail before actual free memory is exhausted. What is even worse is that
with time DMM/TILER spac
On Wed, Feb 16, 2022 at 05:01:35PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 16, 2022 at 02:11:54PM +, Hogander, Jouni wrote:
> > On Wed, 2022-02-16 at 12:07 +0200, Ville Syrjälä wrote:
> > > On Wed, Feb 16, 2022 at 09:36:02AM +, Hogander, Jouni wrote:
> > > > On Wed, 2022-02-16 at 10:50 +0
Hi Ivaylo,
On 19/01/2022 12:23, Ivaylo Dimitrov wrote:
This patch series fixes excessive DMM or CMA usage of GEM buffers leading to
various runtime allocation failures. The series enables daily usage of devices
without exausting limited resources like CMA or DMM space if GPU rendering is
needed.
https://bugzilla.kernel.org/show_bug.cgi?id=214621
Kakha (ka...@soft.ge) changed:
What|Removed |Added
CC||ka...@soft.ge
--- Comment #21 fro
On Thu, Feb 17, 2022 at 08:10:03PM +0900, Byungchul Park wrote:
> [7.009608] ===
> [7.009613] DEPT: Circular dependency has been detected.
> [7.009614] 5.17.0-rc1-00014-g8a599299c0cb-dirty #30 Tainted: GW
> [7.009616] -
On Thu, Feb 17, 2022 at 04:20:15PM +0300, Dmitry Osipenko wrote:
> 17.02.2022 11:29, Sascha Hauer пишет:
> > + hdmi->ref_clk = devm_clk_get(hdmi->dev, "ref");
> > + if (PTR_ERR(hdmi->ref_clk) == -ENOENT)
> > + hdmi->ref_clk = devm_clk_get(hdmi->dev, "vpll");
> > +
> > + if (PTR_ERR(
Hi Andy,
Please trim the context in your answers to the relevant parts, it makes
it easier to find the things you said.
On Thu, Feb 17, 2022 at 08:00:11PM +0800, Andy Yan wrote:
> Hi Sascha:
>
> > +
> > + drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask)
> > {
> > +
Hi,
Appearance of ref_tracker library allows to drop custom solution for wakeref
tracking used in i915 and reuse the library.
For this few adjustements has been made to ref_tracker, details in patches.
I hope changes are OK for original author.
The patchset has been rebased on top of drm-tip to a
To have reliable detection of leaks, caller must be able to check under the same
lock both: tracked counter and the leaks. dir.lock is natural candidate for such
lock and unlocked print helper can be called with this lock taken.
As a bonus we can reuse this helper in ref_tracker_dir_exit.
Signed-o
In cases references are taken alternately on multiple exec paths leak
report can grow substantially, sorting and grouping leaks by stack_handle
allows to compact it.
Signed-off-by: Andrzej Hajda
Reviewed-by: Chris Wilson
---
lib/ref_tracker.c | 35 +++
1 file cha
To improve readibility of ref_tracker printing following changes
have been performed:
- added display name for ref_tracker_dir,
- stack trace is printed indented, in the same printk call,
- total number of references is printed every time,
- print info about dropped references.
Signed-off-by: Andr
1 - 100 of 303 matches
Mail list logo
