On Tue, Feb 15, 2022 at 2:56 AM Qing Wang wrote:
>
> From: Wang Qing
>
> Use the helper function time_is_{before,after}_jiffies() to improve
> code readability.
>
> Signed-off-by: Wang Qing
> Acked-by: Srinivas Pandruvada
FWIW, this one is
Acked-by: Benjamin Tissoires
Wang, is there any plan
On Tue, Feb 15, 2022 at 2:57 AM Qing Wang wrote:
>
> From: Wang Qing
>
> Use the helper function time_is_{before,after}_jiffies() to improve
> code readability.
>
> Signed-off-by: Wang Qing
> ---
Reviewed-by: Benjamin Tissoires
Cheers,
Benjamin
> drivers/input/serio/ps2-gpio.c | 4 ++--
> 1
Am 15.02.22 um 02:59 schrieb Qing Wang:
From: Wang Qing
adev should be assigned after a null check
I would rather remove the NULL check altogether.
The caller is supposed to make sure that the context is valid and even
if it isn't that's not a recoverable error here.
Regards,
Christian.
On Wed, 02 Feb 2022, Kuogee Hsieh wrote:
> 1) Add connector_type to debug info to differentiate between eDP and DP
> 2) add more debug info to cover dp Phy
> 3) repalce DRM_DEBUG_DP with drm_debug_dp
In the future, please include the drm/msm/dp prefix also in the cover
letter. Thanks.
BR,
Jani.
>>On Tue, Feb 15, 2022 at 2:56 AM Qing Wang wrote:
>>
>> From: Wang Qing
>>
>> Use the helper function time_is_{before,after}_jiffies() to improve
>> code readability.
>>
>> Signed-off-by: Wang Qing
>> Acked-by: Srinivas Pandruvada
>
>FWIW, this one is
>Acked-by: Benjamin Tissoires
>
>Wang,
On 15/02/2022 01:11, Daniele Ceraolo Spurio wrote:
Move initialization of submission-related spinlock, lists and workers to
init_early. This fixes an issue where if the GuC init fails we might
still try to get the lock in the context cleanup code. Note that it is
What's the worst case impact
From: Changcheng Deng
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use "flexible array members" for these cases. The older
style of one-element or zero-length arrays should no longer
Am 15.02.22 um 10:11 schrieb cgel@gmail.com:
From: Changcheng Deng
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use "flexible array members" for these cases. The older
style
Il 14/02/22 21:55, Alyssa Rosenzweig ha scritto:
mali_kbase hardcodes MAX_PM_DOMAINS (=5 for the mt8192 kernel). I have
no real objection to it but Angelo did. Maybe should've marked this RFC.
Clarifying, the suggested patch was not a big objection, but I think that it
would be a nice preventiv
[Public]
Hi,
Thanks for the patch and it LGTM.
Feel free to add
Reviewed-by: Wayne Lin
> -Original Message-
> From: Yaroslav Bolyukin
> Sent: Sunday, February 13, 2022 9:31 PM
> To: linux-ker...@vger.kernel.org; dri-devel@lists.freedesktop.org;
> amd-...@lists.freedesktop.org
> Cc: Th
The horizontal resolution (640) for the TT High video mode (1280x960) is
definitely bogus. While fixing that, correct the timings to match the
TTM195 service manual.
Signed-off-by: Geert Uytterhoeven
---
Untested on actual hardware.
v3:
- Adjust pixclock from 7761 to 7760 to match 4 * 32.2159
Hi Helge,
This is a small series of miscellaneous fixes for the Atari frame buffer
device driver.
The first patch has been sent before, and is untested, as I have no
access to the hardware.
The other patches have been tested on ARAnyM.
Thanks!
Geert Uytterhoeven (3):
video: fbdev: ata
atafb_probe() overrides the atafb_ops.fb_setcolreg() method to match the
actual graphics hardware. Besides, the shifts by 8 were bogus, as the
individual .fb_setcolreg() implementations already take care of that.
Signed-off-by: Geert Uytterhoeven
---
drivers/video/fbdev/atafb.c | 11 ---
Remove the custom macro up(), and convert the code to use the standard
round_up() helper instead.
Signed-off-by: Geert Uytterhoeven
---
drivers/video/fbdev/atafb.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/video/fbdev/atafb.c b/drivers/video/fbdev/atafb.
On 11.02.22 00:41, Alistair Popple wrote:
> On Thursday, 10 February 2022 10:47:35 PM AEDT David Hildenbrand wrote:
>> On 10.02.22 12:39, Alistair Popple wrote:
>>> On Thursday, 10 February 2022 9:53:38 PM AEDT David Hildenbrand wrote:
On 07.02.22 05:26, Alistair Popple wrote:
> Currently
Greetings everyone,
Padron for joining in so late o/
On Tue, 8 Feb 2022 at 08:42, Hsin-Yi Wang wrote:
>
> drm_dev_register() sets connector->registration_state to
> DRM_CONNECTOR_REGISTERED and dev->registered to true. If
> drm_connector_set_panel_orientation() is first called after
> drm_dev_re
On 2022-02-14 20:31, Alyssa Rosenzweig wrote:
MT8192 requires 5 power domains. Rather than bump MAX_PM_DOMAINS and
waste memory on every supported Panfrost chip, instead dynamically
allocate pm_domain_devs and pm_domain_links. This adds some flexibility;
it seems inevitable a new MediaTek device
On Tue, 15 Feb 2022, Stephen Rothwell wrote:
> Hi all,
>
> After merging the drm-intel tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/gpu/drm/i915/gvt/kvmgt.c: In function 'handle_edid_regs':
> drivers/gpu/drm/i915/gvt/kvmgt.c:595:38: error: implicit declarati
On 11.02.22 17:56, Jason Gunthorpe wrote:
> On Fri, Feb 11, 2022 at 05:49:08PM +0100, David Hildenbrand wrote:
>> On 11.02.22 17:45, Jason Gunthorpe wrote:
>>> On Fri, Feb 11, 2022 at 05:15:25PM +0100, David Hildenbrand wrote:
>>>
... I'm pretty sure we cannot FOLL_PIN DEVICE_PRIVATE pages
>>>
On 11.02.22 18:07, Felix Kuehling wrote:
>
> Am 2022-02-11 um 11:39 schrieb David Hildenbrand:
>> On 11.02.22 17:15, David Hildenbrand wrote:
>>> On 01.02.22 16:48, Alex Sierra wrote:
Device memory that is cache coherent from device and CPU point of view.
This is used on platforms that h
On 2022-02-11 20:27, alyssa.rosenzw...@collabora.com wrote:
From: Alyssa Rosenzweig
From the kernel's perspective, pre-CSF Valhall is more or less
compatible with Bifrost, although they differ to userspace. Add a
compatible for Valhall to the existing Bifrost bindings documentation.
Signed-of
On 15/02/2022 05:31, Ramalingam C wrote:
i915_perf is not enabled for dg2 yet, hence skip the feature
initialization.
Signed-off-by: Ramalingam C
cc: Umesh Nerlige Ramappa
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 4
1 file changed, 4 insertions(+)
diff --gi
On Tue, Feb 15, 2022 at 8:04 PM Emil Velikov wrote:
>
> Greetings everyone,
>
> Padron for joining in so late o/
>
> On Tue, 8 Feb 2022 at 08:42, Hsin-Yi Wang wrote:
> >
> > drm_dev_register() sets connector->registration_state to
> > DRM_CONNECTOR_REGISTERED and dev->registered to true. If
> > d
On Tue, Feb 15, 2022 at 12:03 PM Gabriel Krisman Bertazi
wrote:
>
> Hsin-Yi Wang writes:
>
> > On Tue, Feb 15, 2022 at 9:17 AM Gabriel Krisman Bertazi
> > wrote:
> >>
> >> Hsin-Yi Wang writes:
> >>
> >> > drm_dev_register() sets connector->registration_state to
> >> > DRM_CONNECTOR_REGISTERED a
On 15/02/2022 01:39, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some legacy chipsets
does not support this feature, this featur
On 15/02/2022 07:12, Bjorn Andersson wrote:
On Mon 14 Feb 16:39 CST 2022, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
Timing engine provides driving force for this purpose. This patch base
on HPG (Hardware Programming Guide) to revise timing en
On 15/02/2022 07:33, Bjorn Andersson wrote:
SC8180x has the eDP controller wired up to INTF_5, so add the interrupt
register block for this interface to the list.
Signed-off-by: Bjorn Andersson
Reviewed-by: Dmitry Baryshkov
---
Changes since v1:
- None
drivers/gpu/drm/msm/disp/dpu1/dpu
On 15/02/2022 07:33, Bjorn Andersson wrote:
From: Rob Clark
Add SC8180x to the hardware catalog, for initial support for the
platform. Due to limitations in the DP driver only one of the four DP
interfaces is left enabled.
The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
On 12/02/2022 15:51, Vinod Polimera wrote:
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Just noticed, thank
On Tuesday, February 15th, 2022 at 13:04, Emil Velikov
wrote:
> Greetings everyone,
>
> Padron for joining in so late o/
>
> On Tue, 8 Feb 2022 at 08:42, Hsin-Yi Wang wrote:
> >
> > drm_dev_register() sets connector->registration_state to
> > DRM_CONNECTOR_REGISTERED and dev->registered to true
This patchset targets DPU encoder code, removing unused artifacts (empty
callbacks, MSM bus client id, etc).
Changes since v1:
- Split dp audio fixup from the intf_type patch
- Remove atomic_check() removal, used by the posted WB support
Dmitry Baryshkov (8):
drm/msm/dpu: fix dp audio conditi
We do not use MSM bus client, so drop bus_scaling_client field from
dpu_encoder_virt.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/dr
Both cmd and vid backends provide useless mode_fixup() callback. Drop
it.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 10 --
All physical encoders used by virtual encoder share the same connector,
so pull the connector field from dpu_encoder_phys into dpu_encoder_virt
structure.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++-
drivers/gp
Rather than passing DRM_MODE_ENCODER_* and letting dpu_encoder to guess,
which intf type we mean, pass INTF_DSI/INTF_DP directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 26 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 4 ++--
dri
Make dpu_encoder use atomic_mode_set to receive connector and CRTC
states as arguments rather than finding connector and CRTC by manually
looping through the respective lists.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 37 +
The msm_display_info structure is not used by the rest of msm driver, so
move it into the dpu1 (dpu_encoder.h to be precise).
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 18 ++
drivers/gpu/drm/msm/msm_drv.h
Stop caching msm_dp instance in dpu_encoder_virt since it's not used
now.
Fixes: 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display enable
and disable")
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 -
1 file chan
DP audio enablement code which is comparing intf_type,
DRM_MODE_ENCODER_TMDS (= 2) with DRM_MODE_CONNECTOR_DisplayPort (= 10).
Which would never succeed. Fix it to check for DRM_MODE_ENCODER_TMDS.
Fixes: d13e36d7d222 ("drm/msm/dp: add audio support for Display Port on MSM")
Signed-off-by: Dmitry B
On Tue, 15 Feb 2022 at 13:55, Simon Ser wrote:
>
> On Tuesday, February 15th, 2022 at 13:04, Emil Velikov
> wrote:
>
> > Greetings everyone,
> >
> > Padron for joining in so late o/
> >
> > On Tue, 8 Feb 2022 at 08:42, Hsin-Yi Wang wrote:
> > >
> > > drm_dev_register() sets connector->registrat
On 15/02/2022 07:37, Bjorn Andersson wrote:
It's typical for the bootloader to configure CTL_0 for the boot splash
or EFIFB, but for non-DSI use cases the DPU driver tend to pick another
CTL and the system might end up with two configured data paths producing
data on the same INTF. In particular
On Tue, Feb 15, 2022 at 01:16:43PM +0100, David Hildenbrand wrote:
> > fact, the first version of our patches attempted to add migration
> > support to DEVICE_GENERIC. But we were convinced to create a new
> > ZONE_DEVICE page type for our use case instead.
>
> Do you know if DEVICE_GENERIC page
The access macros BLK_foo are not used by the code, drop them.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/d
On 12.2.2022 3.17, Nanley Chery wrote:
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
From: Matt Roper
DG2 unifies render compression and media compression into a single
format for the first time. The programming and buffer layout is
supposed to match compression on older gen12 platform
On 12.2.2022 3.19, Nanley Chery wrote:
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
From: Mika Kahola
DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.
v2:
Display version is fixed. [I
> -Original Message-
> From: Juha-Pekka Heikkila
> Sent: Tuesday, February 15, 2022 6:56 AM
> To: Nanley Chery ; C, Ramalingam
>
> Cc: intel-gfx ; Chery, Nanley G
> ; Auld, Matthew ; dri-
> devel
> Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format
> modifier for
On Tue 15 Feb 08:44 CST 2022, Dmitry Baryshkov wrote:
> On 15/02/2022 07:37, Bjorn Andersson wrote:
> > It's typical for the bootloader to configure CTL_0 for the boot splash
> > or EFIFB, but for non-DSI use cases the DPU driver tend to pick another
> > CTL and the system might end up with two co
On Tue 15 Feb 08:53 CST 2022, Dmitry Baryshkov wrote:
> The access macros BLK_foo are not used by the code, drop them.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16
> 1 file changed, 16 deletions
On Fri, 11 Feb 2022 15:27:20 -0500, alyssa.rosenzw...@collabora.com wrote:
> From: Alyssa Rosenzweig
>
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/ro
From: Sascha Hauer
[ Upstream commit c0cfbb122275da1b726481de5a8cffeb24e6322b ]
The driver returns an error when devm_phy_optional_get() fails leaving
the previously enabled clock turned on. Change order and enable the
clock only after the phy has been acquired.
Signed-off-by: Sascha Hauer
Sig
From: Mario Limonciello
[ Upstream commit 03ad3093c7c069d6ab4403730009ebafeea9ee37 ]
A number of BIOS versions have a problem with the watermarks table not
being configured properly. This manifests as a very scary looking warning
during resume from s0i3. This should be harmless in most cases a
From: Aaron Liu
[ Upstream commit a072312f43c33ea02ad88bff3375f650684a6f24 ]
Confirmed with hardware team, there is harvesting for gc 10.3.1.
Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
From: Roman Li
[ Upstream commit 328e34a5ad227399391891d454043e5d73e598d2 ]
[Why]
pflip interrupt order are mapped 1 to 1 to otg id.
e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2...
Linux DM registers pflip interrupts per number of crtcs.
In fused pipe case crtc numbers can be
From: Dmytro Laktyushkin
[ Upstream commit 60fdf98a774eee244a4e00c34a9e7729b61d0f44 ]
Fix clamping to match register field size
Reviewed-by: Charlene Liu
Acked-by: Jasdeep Dhillon
Signed-off-by: Dmytro Laktyushkin
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha L
From: Sascha Hauer
[ Upstream commit c0cfbb122275da1b726481de5a8cffeb24e6322b ]
The driver returns an error when devm_phy_optional_get() fails leaving
the previously enabled clock turned on. Change order and enable the
clock only after the phy has been acquired.
Signed-off-by: Sascha Hauer
Sig
From: Mario Limonciello
[ Upstream commit 03ad3093c7c069d6ab4403730009ebafeea9ee37 ]
A number of BIOS versions have a problem with the watermarks table not
being configured properly. This manifests as a very scary looking warning
during resume from s0i3. This should be harmless in most cases a
From: Roman Li
[ Upstream commit 328e34a5ad227399391891d454043e5d73e598d2 ]
[Why]
pflip interrupt order are mapped 1 to 1 to otg id.
e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2...
Linux DM registers pflip interrupts per number of crtcs.
In fused pipe case crtc numbers can be
From: Dmytro Laktyushkin
[ Upstream commit 60fdf98a774eee244a4e00c34a9e7729b61d0f44 ]
Fix clamping to match register field size
Reviewed-by: Charlene Liu
Acked-by: Jasdeep Dhillon
Signed-off-by: Dmytro Laktyushkin
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha L
From: Sascha Hauer
[ Upstream commit c0cfbb122275da1b726481de5a8cffeb24e6322b ]
The driver returns an error when devm_phy_optional_get() fails leaving
the previously enabled clock turned on. Change order and enable the
clock only after the phy has been acquired.
Signed-off-by: Sascha Hauer
Sig
From: Sascha Hauer
[ Upstream commit c0cfbb122275da1b726481de5a8cffeb24e6322b ]
The driver returns an error when devm_phy_optional_get() fails leaving
the previously enabled clock turned on. Change order and enable the
clock only after the phy has been acquired.
Signed-off-by: Sascha Hauer
Sig
On Tue 15 Feb 08:16 CST 2022, Dmitry Baryshkov wrote:
> DP audio enablement code which is comparing intf_type,
> DRM_MODE_ENCODER_TMDS (= 2) with DRM_MODE_CONNECTOR_DisplayPort (= 10).
> Which would never succeed. Fix it to check for DRM_MODE_ENCODER_TMDS.
>
> Fixes: d13e36d7d222 ("drm/msm/dp: ad
On Tue 15 Feb 08:16 CST 2022, Dmitry Baryshkov wrote:
> Stop caching msm_dp instance in dpu_encoder_virt since it's not used
> now.
>
> Fixes: 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display enable
> and disable")
> Reviewed-by: Abhinav Kumar
> Signed-off-by: Dmitry Baryshkov
R
On Tue 15 Feb 08:16 CST 2022, Dmitry Baryshkov wrote:
> We do not use MSM bus client, so drop bus_scaling_client field from
> dpu_encoder_virt.
>
> Reviewed-by: Abhinav Kumar
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |
On Tue 15 Feb 08:16 CST 2022, Dmitry Baryshkov wrote:
> Both cmd and vid backends provide useless mode_fixup() callback. Drop
> it.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 4
> drivers/gpu/drm/msm/dis
On Tue 15 Feb 08:16 CST 2022, Dmitry Baryshkov wrote:
> Rather than passing DRM_MODE_ENCODER_* and letting dpu_encoder to guess,
> which intf type we mean, pass INTF_DSI/INTF_DP directly.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 26 +++---
From: Jiri Kosina
drm_fb_helper_damage() is acquiring spinlock_t (helper->damage_lock),
while it can be called from contexts where raw_spinlock_t is held (e.g.
console_owner lock obtained on vprintk_emit() codepath).
As the critical sections protected by damage_lock are super-tiny, let's
fix
On 2022-02-15 16:43:08 [+0100], Jiri Kosina wrote:
> From: Jiri Kosina
>
> drm_fb_helper_damage() is acquiring spinlock_t (helper->damage_lock),
> while it can be called from contexts where raw_spinlock_t is held (e.g.
> console_owner lock obtained on vprintk_emit() codepath).
>
> As the criti
On 15.2.2022 17.02, Chery, Nanley G wrote:
-Original Message-
From: Juha-Pekka Heikkila
Sent: Tuesday, February 15, 2022 6:56 AM
To: Nanley Chery ; C, Ramalingam
Cc: intel-gfx ; Chery, Nanley G
; Auld, Matthew ; dri-
devel
Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Intr
On 2022-02-15, Sebastian Siewior wrote:
>> From: Jiri Kosina
>>
>> drm_fb_helper_damage() is acquiring spinlock_t (helper->damage_lock),
>> while it can be called from contexts where raw_spinlock_t is held (e.g.
>> console_owner lock obtained on vprintk_emit() codepath).
>>
>> As the critical
It's hard to parse for-loop which has some magic calculations inside.
Much cleaner to use while-loop directly.
Signed-off-by: Andy Shevchenko
---
drivers/gpu/drm/i915/selftests/i915_syncmap.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests
On Tuesday, February 15th, 2022 at 15:38, Emil Velikov
wrote:
> On Tue, 15 Feb 2022 at 13:55, Simon Ser wrote:
> >
> > On Tuesday, February 15th, 2022 at 13:04, Emil Velikov
> > wrote:
> >
> > > Greetings everyone,
> > >
> > > Padron for joining in so late o/
> > >
> > > On Tue, 8 Feb 2022 at
On 2/15/2022 1:09 AM, Tvrtko Ursulin wrote:
On 15/02/2022 01:11, Daniele Ceraolo Spurio wrote:
Move initialization of submission-related spinlock, lists and workers to
init_early. This fixes an issue where if the GuC init fails we might
still try to get the lock in the context cleanup code.
> -Original Message-
> From: Juha-Pekka Heikkila
> Sent: Tuesday, February 15, 2022 8:15 AM
> To: Chery, Nanley G ; Nanley Chery
> ; C, Ramalingam
> Cc: intel-gfx ; Auld, Matthew
> ; dri-devel
> Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format
> modifier for DG2
On 2/11/2022 4:38 PM, Dmitry Baryshkov wrote:
From: Bjorn Andersson
dpu_kms_debugfs_init() is invoked for each minor being registered. Most
of the files created are unrelated to the minor, so there's no reason to
present them per minor.
The exception to this is the DisplayPort code, which en
On 2/15/2022 6:16 AM, Dmitry Baryshkov wrote:
Both cmd and vid backends provide useless mode_fixup() callback. Drop
it.
Thanks for not removing the atomic_check().
BTW, can you please include that in the change log so that others
reviewing it know.
That being said,
Reviewed-by: Abhinav
Introduce fourcc codes for single-channel frame buffer formats with two,
four, and sixteen intensity levels. Traditionally, the first channel
has been called the "red" channel, but the fourcc can also be used for
other light-on-dark displays.
As the number of bits per pixel is less than eight, th
Introduce fourcc codes for color-indexed frame buffer formats with two,
four, and sixteen color, and provide a suitable mapping from bit per
pixel and depth to fourcc codes.
As the number of bits per pixel is less than eight, these rely on proper
block handling for the calculation of bits per pixe
Introduce a fourcc code for a single-channel frame buffer format with two
darkness levels. This can be used for two-level dark-on-light displays.
As the number of bits per pixel is less than eight, this relies on
proper block handling for the calculation of bits per pixel and pitch.
Signed-off-b
The AFBC helpers derive the number of bits per pixel from the deprecated
drm_format_info.cpp[] field, which does not take into account block
sizes.
Fix this by using the actual number of bits per pixel instead.
Signed-off-by: Geert Uytterhoeven
---
Untested.
After adding the missing block info,
Add a helper to retrieve the actual number of bits per pixel for a
plane, taking into account the number of characters and pixels per
block for tiled formats.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/drm_fourcc.c | 19 +++
include/drm/drm_fourcc.h | 1 +
2 files
Hi all,
A long outstanding issue with the DRM subsystem has been the lack of
support for low-color displays, as used typically on older desktop
systems and small embedded displays.
This patch series adds support for color-indexed frame buffer formats
with 2, 4, and 16 colors. It has been
When userspace queries the properties of a frame buffer, the number of
bits per pixel is derived from the deprecated drm_format_info.cpp[]
field, which does not take into account block sizes.
Fix this by using the actual number of bits per pixel instead.
Signed-off-by: Geert Uytterhoeven
---
Unt
When allocating a frame buffer, the number of bits per pixel needed is
derived from the deprecated drm_format_info.cpp[] field. While this
works for formats using less than 8 bits per pixel, it does lead to a
large overallocation.
Reduce memory consumption by using the actual number of bits per p
Add support for color-indexed frame buffer formats with two, four, and
sixteen colors to the DRM framebuffer helper functions:
1. Add support for depths 1/2/4 to the damage helper,
2. For color-indexed modes, the length of the color bitfields must be
set to the color depth, else the logo c
On 2/14/2022 8:33 PM, Bjorn Andersson wrote:
From: Rob Clark
Add SC8180x to the hardware catalog, for initial support for the
platform. Due to limitations in the DP driver only one of the four DP
interfaces is left enabled.
The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag
On Tue, 15 Feb 2022, Andy Shevchenko wrote:
> It's hard to parse for-loop which has some magic calculations inside.
> Much cleaner to use while-loop directly.
I assume you're trying to prove a point following our recent
for-vs-while loop discussion. I really can't think of any other reason
you'd
Hi guys,
in the last set Felix pointed out a severe bug in the iterator
implementation and after investigating I've found that my test case
didn't even exercised this code path.
So after fixing the test case I've found a couple of more minor
problems. This is the resulting patch set with everythi
Not just TT and VRAM.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Tested-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/ttm/ttm_resource.c | 52 +-
include/drm/ttm/ttm_device.h | 2 --
include/drm/ttm/ttm_resource.h | 4 +--
3 files changed, 17
This way we finally fix the problem that new resource are
not immediately evict-able after allocation.
That has caused numerous problems including OOM on GDS handling
and not being able to use TTM as general resource manager.
v2: stop assuming in ttm_resource_fini that res->bo is still valid.
v3:
Those functions are going to become more complex, don't inline them any
more.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 31 +++
include/drm/ttm/ttm_bo_api.h | 30 ++
2 files changed, 33 insertions(+), 28 deletions(-)
Instead of providing the bulk move structure for each LRU update set
this as property of the BO. This should avoid costly bulk move rebuilds
with some games under RADV.
v2: some name polishing, add a few more kerneldoc words.
v3: add some lockdep
v4: fix bugs, handle pin/unpin as well
Signed-off-
We have the BO pointer in the base structure now as well.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Tested-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 49 -
include/drm/ttm/ttm_resource.h | 8
2 files changed, 2
Instead of duplicating that at different places add an iterator over all
the resources in a resource manager.
v2: add lockdep annotation and kerneldoc
v3: fix various bugs pointed out by Felix
Signed-off-by: Christian König
Tested-by: Bas Nieuwenhuizen
Reviewed-by: Daniel Vetter (v3)
---
driv
On Tue 15 Feb 11:14 CST 2022, Abhinav Kumar wrote:
>
>
> On 2/14/2022 8:33 PM, Bjorn Andersson wrote:
> > From: Rob Clark
> >
> > Add SC8180x to the hardware catalog, for initial support for the
> > platform. Due to limitations in the DP driver only one of the four DP
> > interfaces is left en
On 15.2.2022 18.44, Chery, Nanley G wrote:
-Original Message-
From: Juha-Pekka Heikkila
Sent: Tuesday, February 15, 2022 8:15 AM
To: Chery, Nanley G ; Nanley Chery
; C, Ramalingam
Cc: intel-gfx ; Auld, Matthew
; dri-devel
Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Intro
On 10/02/2022 12:03, Yong Wu wrote:
> On Thu, 2022-01-27 at 12:01 -0800, Stephen Boyd wrote:
>> Use an aggregate driver instead of component ops so that we can get
>> proper driver probe ordering of the aggregate device with respect to
>> all
>> the component devices that make up the aggregate devi
There is a regular need in the kernel to provide a way to declare
having a dynamically sized set of trailing elements in a structure.
Kernel code should always use “flexible array members”[1] for these
cases. The older style of one-element or zero-length arrays should
no longer be used[2].
This co
On 2/14/2022 8:22 PM, Bjorn Andersson wrote:
On Mon 14 Feb 16:39 CST 2022, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some
On 2/15/2022 9:28 AM, Bjorn Andersson wrote:
On Tue 15 Feb 11:14 CST 2022, Abhinav Kumar wrote:
On 2/14/2022 8:33 PM, Bjorn Andersson wrote:
From: Rob Clark
Add SC8180x to the hardware catalog, for initial support for the
platform. Due to limitations in the DP driver only one of the fou
Hi Jonathan,
Le dim., févr. 13 2022 at 18:46:16 +, Jonathan Cameron
a écrit :
On Mon, 7 Feb 2022 12:59:21 +
Paul Cercueil wrote:
Hi Jonathan,
This is the V2 of my patchset that introduces a new userspace
interface
based on DMABUF objects to complement the fileio API, and adds
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