We can now add multiple writers to the dma_resv object.
Also enable the check for not adding containers in dma_resv.c again.
Signed-off-by: Christian König
Cc: amd-...@lists.freedesktop.org
---
drivers/dma-buf/dma-resv.c | 6 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h |
Get the write fence using dma_resv_for_each_fence instead of accessing
it manually.
Signed-off-by: Christian König
Cc: amd-...@lists.freedesktop.org
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/
We have previously done that in the individual drivers but it is
more defensive to move that into the common code.
Dynamic attachments should wait for map operations to complete by themselves.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf.c | 18 +++---
Add an usage for submissions independent of implicit sync but still
interesting for memory management.
v2: cleanup the kerneldoc a bit
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c | 2 +-
drivers/dma-buf/st-dma-resv.c| 2 +-
drivers/g
It fixes typo and updates outdated struct and API names that are currently
deprecated or in use but have changed on the kernel documents of DRM section
and comments.
Signed-off-by: Gwan-gyeong Mun
---
Documentation/gpu/drm-mm.rst | 8
drivers/gpu/drm/drm_file.c| 10
Hi,
This patchset adds a driver that will work with most MIPI DBI compatible
SPI panels out there.
Maxime gave[1] a good overview of the situation with these displays and
proposed to make a driver that works with all MIPI DBI compatible
controllers and use a firmware file to provide the controlle
Add a driver that will work with most MIPI DBI compatible SPI panels.
This avoids adding a driver for every new MIPI DBI compatible controller
that is to be used by Linux. The 'compatible' Device Tree property with
a '.bin' suffix will be used to load a firmware file that contains the
controller co
devm_drm_dev_alloc() can't allocate structures that embed a structure
which then again embeds drm_device. Workaround this by adding a
driver_private pointer to struct mipi_dbi_dev which the driver can use for
its additional state.
v3:
- Add documentation
Signed-off-by: Noralf Trønnes
---
includ
Add binding for MIPI DBI compatible SPI panels.
v3:
- Move properties to Device Tree (Maxime)
- Use contains for compatible (Maxime)
- Add backlight property to example
- Flesh out description
v2:
- Fix path for panel-common.yaml
- Use unevaluatedProperties
- Drop properties which are in the allO
On Mon, Jan 31, 2022 at 11:28:38AM +0100, Oleksij Rempel wrote:
> From: Robin van der Gracht
>
> Signed-off-by: Robin van der Gracht
Please write up some commit log. Also your SoB is missing.
Shawn
> ---
> arch/arm/boot/dts/imx6dl-prtvt7.dts | 42 +
> 1 file chan
On Fri, Feb 11, 2022 at 02:04:32PM +0100, Noralf Trønnes wrote:
> Add binding for MIPI DBI compatible SPI panels.
>
> v3:
> - Move properties to Device Tree (Maxime)
> - Use contains for compatible (Maxime)
> - Add backlight property to example
> - Flesh out description
>
> v2:
> - Fix path for p
On Fri, Feb 11, 2022 at 02:04:33PM +0100, Noralf Trønnes wrote:
> devm_drm_dev_alloc() can't allocate structures that embed a structure
> which then again embeds drm_device. Workaround this by adding a
> driver_private pointer to struct mipi_dbi_dev which the driver can use for
> its additional sta
On Fri, Feb 11, 2022 at 02:04:34PM +0100, Noralf Trønnes wrote:
> Add a driver that will work with most MIPI DBI compatible SPI panels.
> This avoids adding a driver for every new MIPI DBI compatible controller
> that is to be used by Linux. The 'compatible' Device Tree property with
> a '.bin' suf
On Mon, 31 Jan 2022 17:47:23 +0100, quentin.sch...@theobroma-systems.com wrote:
> From: Quentin Schulz
>
> The LTK050H3148W-CTA6 is a 5.0" 720x1280 DSI display, whose driving
> controller is a Himax HX8394-F, slightly different from LTK050H3146W by
> its init sequence, mode details and mode flags
The gpio1 0 pin is controlling CAN termination, not USB H1 VBUS. So,
remove wrong regulator and assign this gpio to new DT CAN termnation
property.
Signed-off-by: Oleksij Rempel
---
arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --
Add thermal zones and hwmon connected to the ADC-touchscreen controller.
Signed-off-by: Oleksij Rempel
---
arch/arm/boot/dts/imx6dl-plym2m.dts | 74 -
arch/arm/boot/dts/imx6dl-prtvt7.dts | 57 ++
arch/arm/boot/dts/imx6dl-victgo.dts | 62 +++
changes v3:
- add missing SoB and commit message
changes v2:
- add missing new lines
- rename adc label to adc_ts
- add thermal zones patch
Oleksij Rempel (4):
ARM: dts: imx6dl-prtvt7: Add display and panel nodes
ARM: dts: imx6qdl-vicut1: add CAN termination support
ARM: dts: imx6dl: plym2m
From: Robin van der Gracht
Add missing tvp5150 video decoder node to make composite video input
work.
Signed-off-by: Robin van der Gracht
Signed-off-by: Oleksij Rempel
---
arch/arm/boot/dts/imx6dl-prtvt7.dts | 42 +
1 file changed, 42 insertions(+)
diff --git a/ar
Add Innolux G070Y2-T02 panel to the Protonic VT7 board.
Signed-off-by: Robin van der Gracht
Signed-off-by: Oleksij Rempel
---
arch/arm/boot/dts/imx6dl-prtvt7.dts | 47 +
1 file changed, 47 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts
b/arch/arm/bo
The tsc2046 is an ADC used as touchscreen controller. To share as mach
code as possible, we should use it as actual ADC + virtual touchscreen
controller.
With this patch we make use of the new kernel IIO and HID infrastructure.
Signed-off-by: Oleksij Rempel
---
arch/arm/boot/dts/imx6dl-plym2m.dt
On 2022-02-07 at 08:55:20 -0800, Daniele Ceraolo Spurio wrote:
>
>
> On 1/28/2022 10:52 AM, Ramalingam C wrote:
> > From: Stuart Summers
> >
> > The driver is set currently to fail modprobe when GuC is disabled
> > (enable_guc=0) after GuC has been loaded on a previous modprobe.
> > For GuC dep
On Thu, 10 Feb 2022, Michael Cheng wrote:
> Move wbvind_on_all_cpus to intel_gt.h. This will allow other wbind_on_all_cpus
> calls to benefit from the #define logic, and prevent compiler errors
> when building for non-x86 architectures.
>
> Signed-off-by: Michael Cheng
> ---
> drivers/gpu/drm/i9
On 2022-02-07 at 11:52:48 +, Matthew Auld wrote:
> On 07/02/2022 11:48, Matthew Auld wrote:
> > On Fri, 28 Jan 2022 at 18:52, Ramalingam C wrote:
> > >
> > > An indirect ctx wabb is implemented as per Wa_22011450934 to avoid rcs
> > > restore hang during context restore of a preempted context
Dear Zhouyi,
Am 10.02.22 um 07:58 schrieb Zhouyi Zhou:
In function do_remove_conflicting_framebuffers, if device is NULL, there
will be null pointer reference. The patch add a check to the if expression.
Signed-off-by: Zhouyi Zhou
---
Dear Linux folks
I discover this bug in the PowerPC VM pr
On 11/02/2022 02:31, Abhinav Kumar wrote:
On 2/10/2022 1:32 AM, Dmitry Baryshkov wrote:
On 10/02/2022 03:25, Abhinav Kumar wrote:
On 1/21/2022 1:06 PM, Dmitry Baryshkov wrote:
INTF blocks are not really handled by resource manager, they are
assigned at dpu_encoder_setup_display using dpu_e
Den 11.02.2022 14.27, skrev Maxime Ripard:
> On Fri, Feb 11, 2022 at 02:04:32PM +0100, Noralf Trønnes wrote:
>> Add binding for MIPI DBI compatible SPI panels.
>>
>> v3:
>> - Move properties to Device Tree (Maxime)
>> - Use contains for compatible (Maxime)
>> - Add backlight property to example
This patch series adds a DRM driver for the Solomon OLED SSD1305, SSD1306,
SSD1307 and SSD1309 displays. It is a port of the ssd1307fb fbdev driver.
Using the DRM fbdev emulation, all the tests from Geert Uytterhoeven repo
(https://git.kernel.org/pub/scm/linux/kernel/git/geert/fbtest.git) passes.
Add support to convert from XR24 to reversed monochrome for drivers that
control monochromatic display panels, that only have 1 bit per pixel.
The function does a line-by-line conversion doing an intermediate step
first from XR24 to 8-bit grayscale and then to reversed monochrome.
The drm_fb_gray
Pull the per-line conversion logic into a separate helper function.
This will allow to do line-by-line conversion in other helpers that
convert to a gray8 format.
Suggested-by: Thomas Zimmermann
Signed-off-by: Javier Martinez Canillas
Reviewed-by: Thomas Zimmermann
---
Changes in v5:
- Add Th
The ssd130x driver only provides the core support for these devices but it
does not have any bus transport logic. Add a driver to interface over I2C.
Signed-off-by: Javier Martinez Canillas
Reviewed-by: Andy Shevchenko
---
Changes in v5:
- Add Andy Shevchenko's Reviewed-by tag to patch #4.
Cha
This adds a DRM driver for SSD1305, SSD1306, SSD1307 and SSD1309 Solomon
OLED display controllers.
It's only the core part of the driver and a bus specific driver is needed
for each transport interface supported by the display controllers.
Signed-off-by: Javier Martinez Canillas
---
Changes in
To make sure that tools like the get_maintainer.pl script will suggest
to Cc me if patches are posted for this driver.
Also include the Device Tree binding for the old ssd1307fb fbdev driver
since the new DRM driver was made compatible with the existing binding.
Signed-off-by: Javier Martinez Can
The ssd130x DRM driver also makes use of this Device Tree binding to allow
existing users of the fbdev driver to migrate without the need to change
their Device Trees.
Add myself as another maintainer of the binding, to make sure that I will
be on Cc when patches are proposed for it.
Suggested-by
From: Alyssa Rosenzweig
The IDVS group size feature was missing. It is used on some Bifrost and
Valhall GPUs, and is the last kernel-relevant Bifrost feature we're
missing.
This feature adds an extra IDVS group size field to the JM_CONFIG
register. In kbase, the value is configurable via the dev
On 11/02/2022 14:58, alyssa.rosenzw...@collabora.com wrote:
> From: Alyssa Rosenzweig
>
> The IDVS group size feature was missing. It is used on some Bifrost and
> Valhall GPUs, and is the last kernel-relevant Bifrost feature we're
> missing.
>
> This feature adds an extra IDVS group size field
On Fri, Feb 11, 2022 at 02:05:56PM +0200, Jani Nikula wrote:
> On Fri, 11 Feb 2022, Thomas Zimmermann wrote:
> > Am 11.02.22 um 12:12 schrieb Andy Shevchenko:
> >> On Fri, Feb 11, 2022 at 11:40:13AM +0100, Javier Martinez Canillas wrote:
> >>> On 2/11/22 11:28, Andy Shevchenko wrote:
> On Fri
On Thu, 2022-02-10 at 18:30 -0800, Qing Wang wrote:
> From: Wang Qing
>
> It is better to use time_xxx() directly instead of jiffies judgment
> for understanding.
>
> Signed-off-by: Wang Qing
Acked-by: Srinivas Pandruvada
> ---
> drivers/hid/intel-ish-hid/ipc/ipc.c | 2 +-
> 1 file changed,
On Sun, Feb 06, 2022 at 09:00:11AM +0100, Andreas Kemnade wrote:
> Add a binding for the Electrophoretic Display Controller found at least
> in the i.MX6.
The first version was in i.MX50 (I helped design the register
interface). Is that version compatible?
> The timing subnode is directly here t
On Fri, Feb 11, 2022 at 01:05:57PM +0100, Javier Martinez Canillas wrote:
> On 2/11/22 12:33, Andy Shevchenko wrote:
> > On Fri, Feb 11, 2022 at 10:19:24AM +0100, Javier Martinez Canillas wrote:
...
> >> + * Helper to write command (SSD130X_COMMAND). The fist variadic argument
> >> + * is the com
On Fri, Feb 11, 2022 at 12:50:04PM +0100, Javier Martinez Canillas wrote:
> On 2/11/22 12:10, Andy Shevchenko wrote:
...
> >> + for (xb = 0; xb < pixels; xb++) {
> >> + unsigned int start = 0, end = 8;
> >> + u8 byte = 0x00;
> >
> >> + if (xb == 0 && start_offset)
> >
On Fri, Feb 11, 2022 at 03:33:53PM +0100, Javier Martinez Canillas wrote:
> Pull the per-line conversion logic into a separate helper function.
>
> This will allow to do line-by-line conversion in other helpers that
> convert to a gray8 format.
for-loop vs. while-loop is not critical, so
Reviewed
Thanks for the feedback! Another idea I had that kind of align to what you are
suggesting is adding a wrapper for wbinvd_on_all_cpus within drm_cache.h, then
having it be included in the three files that calls this function. Thoughts on
that?
From: Jani Nikula
On Fri, Feb 11, 2022 at 03:33:54PM +0100, Javier Martinez Canillas wrote:
> Add support to convert from XR24 to reversed monochrome for drivers that
> control monochromatic display panels, that only have 1 bit per pixel.
>
> The function does a line-by-line conversion doing an intermediate step
>
On Fri, Feb 11, 2022 at 03:33:55PM +0100, Javier Martinez Canillas wrote:
> This adds a DRM driver for SSD1305, SSD1306, SSD1307 and SSD1309 Solomon
> OLED display controllers.
>
> It's only the core part of the driver and a bus specific driver is needed
> for each transport interface supported by
On 01.02.22 16:48, Alex Sierra wrote:
> Device memory that is cache coherent from device and CPU point of view.
> This is used on platforms that have an advanced system bus (like CAPI
> or CXL). Any page of a process can be migrated to such memory. However,
> no one should be allowed to pin such me
On 11/02/2022 13:33, Jani Nikula wrote:
On Thu, 10 Feb 2022, Michael Cheng wrote:
Move wbvind_on_all_cpus to intel_gt.h. This will allow other wbind_on_all_cpus
calls to benefit from the #define logic, and prevent compiler errors
when building for non-x86 architectures.
Signed-off-by: Michae
On Fri, 11 Feb 2022, Andy Shevchenko wrote:
> On Fri, Feb 11, 2022 at 02:05:56PM +0200, Jani Nikula wrote:
>> On Fri, 11 Feb 2022, Thomas Zimmermann wrote:
>> > Am 11.02.22 um 12:12 schrieb Andy Shevchenko:
>> >> On Fri, Feb 11, 2022 at 11:40:13AM +0100, Javier Martinez Canillas wrote:
>> >>> On
On Mon, 07 Feb 2022 23:39:11 +0100, David Heidelberg wrote:
> Inherit valid properties from the dsi-controller.
>
> Reviewed-by: Dmitry Osipenko
> Signed-off-by: David Heidelberg
> ---
> v2:
> - added $ref ../dsi-controller.yaml# instead copying properties (Dmitry)
> - additionalProperties ->
On 11.02.22 17:15, David Hildenbrand wrote:
> On 01.02.22 16:48, Alex Sierra wrote:
>> Device memory that is cache coherent from device and CPU point of view.
>> This is used on platforms that have an advanced system bus (like CAPI
>> or CXL). Any page of a process can be migrated to such memory. H
On Fri, Feb 11, 2022 at 05:15:25PM +0100, David Hildenbrand wrote:
> ... I'm pretty sure we cannot FOLL_PIN DEVICE_PRIVATE pages
Currently the only way to get a DEVICE_PRIVATE page out of the page
tables is via hmm_range_fault() and that doesn't manipulate any ref
counts.
Jason
On 11.02.22 17:45, Jason Gunthorpe wrote:
> On Fri, Feb 11, 2022 at 05:15:25PM +0100, David Hildenbrand wrote:
>
>> ... I'm pretty sure we cannot FOLL_PIN DEVICE_PRIVATE pages
>
> Currently the only way to get a DEVICE_PRIVATE page out of the page
> tables is via hmm_range_fault() and that doesn'
On 2/11/2022 10:39 AM, David Hildenbrand wrote:
On 11.02.22 17:15, David Hildenbrand wrote:
On 01.02.22 16:48, Alex Sierra wrote:
Device memory that is cache coherent from device and CPU point of view.
This is used on platforms that have an advanced system bus (like CAPI
or CXL). Any page of a
On Fri, Feb 11, 2022 at 05:49:08PM +0100, David Hildenbrand wrote:
> On 11.02.22 17:45, Jason Gunthorpe wrote:
> > On Fri, Feb 11, 2022 at 05:15:25PM +0100, David Hildenbrand wrote:
> >
> >> ... I'm pretty sure we cannot FOLL_PIN DEVICE_PRIVATE pages
> >
> > Currently the only way to get a DEVICE
Am 2022-02-11 um 11:15 schrieb David Hildenbrand:
On 01.02.22 16:48, Alex Sierra wrote:
Device memory that is cache coherent from device and CPU point of view.
This is used on platforms that have an advanced system bus (like CAPI
or CXL). Any page of a process can be migrated to such memory. H
Am 2022-02-11 um 11:39 schrieb David Hildenbrand:
On 11.02.22 17:15, David Hildenbrand wrote:
On 01.02.22 16:48, Alex Sierra wrote:
Device memory that is cache coherent from device and CPU point of view.
This is used on platforms that have an advanced system bus (like CAPI
or CXL). Any page o
On Wed, 09 Feb 2022 22:55:45 +0100, Michael Riesch wrote:
> From: Alex Bee
>
> The Bifrost GPU in Rockchip RK356x SoCs has a core and a bus clock.
> Reflect this in the SoC specific part of the binding.
>
> Signed-off-by: Alex Bee
> [move the changes to the SoC section]
> Signed-off-by: Michael
On Fri, Feb 11, 2022 at 06:25:17PM +0200, Jani Nikula wrote:
> On Fri, 11 Feb 2022, Andy Shevchenko
> wrote:
> > On Fri, Feb 11, 2022 at 02:05:56PM +0200, Jani Nikula wrote:
> >> On Fri, 11 Feb 2022, Thomas Zimmermann wrote:
> >> > Am 11.02.22 um 12:12 schrieb Andy Shevchenko:
> >> >> On Fri, Fe
Hi Greg
Thanks for the response.
On 2/11/2022 3:09 AM, Greg KH wrote:
On Tue, Feb 08, 2022 at 11:44:32AM -0800, Abhinav Kumar wrote:
There are cases where depending on the size of the devcoredump and the speed
at which the usermode reads the dump, it can take longer than the current 5 mins
tim
Hello Andy,
On 2/11/22 17:13, Andy Shevchenko wrote:
[snip]
>
>> +#define SSD130X_SET_COM_PINS_CONFIG1_MASK GENMASK(4, 4)
>
> BIT(4)
>
>> +#define SSD130X_SET_COM_PINS_CONFIG1_SET(val)
>> FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG1_MASK, (!val))
>> +#define SSD130X_SET_COM_PINS_CONFIG2_M
On Wed, 9 Feb 2022 22:55:44 +0100, Michael Riesch wrote:
> This series aims to bring the GPU support for the RK356x mainline. In
> conjunction with the VOP2/HDMI TX patches v4 [0]) it has been tested
> successfully on a RK3568 EVB1 with weston and glmark2-es2-wayland.
>
> It should be noted that o
On Wed, 9 Feb 2022 22:55:44 +0100, Michael Riesch wrote:
> This series aims to bring the GPU support for the RK356x mainline. In
> conjunction with the VOP2/HDMI TX patches v4 [0]) it has been tested
> successfully on a RK3568 EVB1 with weston and glmark2-es2-wayland.
>
> It should be noted that o
Various drivers in the kernel use `is_thunderbolt` or
`pci_is_thunderbolt_attached` to designate behaving differently
from a device that is internally in the machine. This relies upon checks
for a specific capability only set on Intel controllers.
Non-Intel USB4 designs should also match this desi
This PCI class definition of the USB4 device is currently located only in
the thunderbolt driver.
It will be needed by a few other drivers for upcoming changes. Move it into
the common include file.
Acked-by: Alex Deucher
Acked-by: Mika Westerberg
Signed-off-by: Mario Limonciello
---
drivers/
The `is_thunderbolt` check is currently used to indicate the lack of
command completed support for a number of older Thunderbolt devices.
This however is heavy handed and should have been done via a quirk. Move
the affected devices outlined in commit 493fb50e958c ("PCI: pciehp: Assume
NoCompl+ fo
`pci_bridge_d3_possible` currently checks explicitly for a Thunderbolt
controller to indicate that D3 is possible. As this is used solely
for older Apple systems, move it into a quirk that enumerates across
all Intel TBT controllers.
Suggested-by: Mika Westerberg
Signed-off-by: Mario Limonciello
Currently `pci_is_thunderbolt_attached` is used to indicate a device
is connected externally.
The PCI core now marks such devices as removable and downstream drivers
can use this instead.
Reviewed-by: Macpaul Lin
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2
The root port used for PCIe tunneling should be marked as removable to
ensure that the entire chain is marked removable.
This can be done by looking for the device property specified in
the ACPI tables `usb4-host-interface`.
Suggested-by: Mika Westerberg
Link:
https://docs.microsoft.com/en-us/w
Discrete USB4 controllers won't have ACPI nodes specifying which
PCIe or XHCI port they are linked with.
In order to set the removable attribute appropriately, use the
USB4 DVSEC extended capabability set on these root ports to determine
if they are located on a discrete USB4 controller.
Suggeste
The `is_thunderbolt` attribute is currently a dumping ground for a
variety of things.
Instead use the driver core removable attribute to indicate the
detail a device is attached to a thunderbolt or USB4 chain.
Signed-off-by: Mario Limonciello
---
drivers/pci/probe.c | 20 +++--
Currently `pci_is_thunderbolt_attached` is used to indicate a device
is connected externally.
The PCI core now marks such devices as removable and downstream drivers
can use this instead.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/radeon/radeon_device.c | 4 ++--
drivers/gpu/drm/radeo
Currently `pci_is_thunderbolt_attached` is used to indicate a device
is connected externally.
The PCI core now marks such devices as removable and downstream drivers
can use this instead.
Acked-by: Hans de Goede
Signed-off-by: Mario Limonciello
---
drivers/platform/x86/apple-gmux.c | 2 +-
1 f
USB4 class devices are also removable like Intel Thunderbolt devices.
Drivers of downstream devices use this information to declare functional
differences in how the drivers perform by knowing that they are connected
to an upstream TBT/USB4 port.
Reviewed-by: Macpaul Lin
Signed-off-by: Mario Lim
Currently `pci_is_thunderbolt_attached` is used to indicate a device
is connected externally.
The PCI core now marks such devices as removable and downstream drivers
can use this instead.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/nouveau/nouveau_vga.c | 4 ++--
1 file changed, 2 inse
Currently `pci_is_thunderbolt_attached` is used to indicate a device
is connected externally.
As all drivers now look at the removable attribute, drop this function.
Signed-off-by: Mario Limonciello
---
include/linux/pci.h | 22 --
1 file changed, 22 deletions(-)
diff --git
[Public]
> -Original Message-
> From: Mika Westerberg
> Sent: Friday, February 11, 2022 04:35
> To: Limonciello, Mario
> Cc: Bjorn Helgaas ; Andreas Noever
> ; open list:PCI SUBSYSTEM p...@vger.kernel.org>; open list:THUNDERBOLT DRIVER u...@vger.kernel.org>; open list:RADEON and AMDG
[Public]
> -Original Message-
> From: Mika Westerberg
> Sent: Friday, February 11, 2022 04:24
> To: Limonciello, Mario
> Cc: Bjorn Helgaas ; Andreas Noever
> ; open list:PCI SUBSYSTEM p...@vger.kernel.org>; open list:THUNDERBOLT DRIVER u...@vger.kernel.org>; open list:RADEON and AMDGPU
On 18/01/2022 23:03, Dmitry Baryshkov wrote:
On Tue, 18 Jan 2022 at 22:29, Abhinav Kumar wrote:
On 12/7/2021 2:29 PM, Dmitry Baryshkov wrote:
The DSI subsystem does not fully fall into the pre-enable/enable system
of callbacks, since typically DSI device bridge drivers expect to be
able to
The pull request you sent on Fri, 11 Feb 2022 13:46:47 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2022-02-11
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/c3ee3a9e4fa6b1d249b5abff2d4c7dab5a47d522
Thank you!
--
Deet-doot-dot, I am a bot.
https://k
On 2/11/2022 11:37 AM, Dmitry Baryshkov wrote:
On 18/01/2022 23:03, Dmitry Baryshkov wrote:
On Tue, 18 Jan 2022 at 22:29, Abhinav Kumar
wrote:
On 12/7/2021 2:29 PM, Dmitry Baryshkov wrote:
The DSI subsystem does not fully fall into the pre-enable/enable system
of callbacks, since typica
From: Alyssa Rosenzweig
This patch series adds preliminary support for Mali "Valhall" GPUs into
the Panfrost kernel driver. The series has been tested on the Mali-G57
on a MediaTek MT8192 system. However, that system requires additional
MediaTek-specific patches [1] as well as core mainlining for
From: Alyssa Rosenzweig
>From the kernel's perspective, pre-CSF Valhall is more or less
compatible with Bifrost, although they differ to userspace. Add a
compatible for Valhall to the existing Bifrost bindings documentation.
Signed-off-by: Alyssa Rosenzweig
Cc: devicet...@vger.kernel.org
---
D
From: Alyssa Rosenzweig
Logically, this function is free of side effects, so any pointers it
takes should be const. Needed to avoid a warning in the next patch.
Signed-off-by: Alyssa Rosenzweig
---
drivers/gpu/drm/panfrost/panfrost_issues.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Alyssa Rosenzweig
Some Valhall GPUs require resets when encountering bus faults due to
occlusion query writes. Add the issue bit for this and handle it.
Signed-off-by: Alyssa Rosenzweig
---
drivers/gpu/drm/panfrost/panfrost_device.c | 9 +++--
drivers/gpu/drm/panfrost/panfrost_issues
From: Alyssa Rosenzweig
TTRX_3485 requires the infamous "dummy job" workaround. I have this
workaround implemented in a local branch, but I have not yet hit a case
that requires it so I cannot test whether the implementation is correct.
In the mean time, add the quirk bit so we can document which
From: Alyssa Rosenzweig
Add handling for the HW_ISSUE_TTRX_2968_TTRX_3162 quirk. Logic ported
from kbase. kbase lists this workaround as used on Mali-G57.
Signed-off-by: Alyssa Rosenzweig
---
drivers/gpu/drm/panfrost/panfrost_gpu.c| 3 +++
drivers/gpu/drm/panfrost/panfrost_issues.h | 3 +++
From: Alyssa Rosenzweig
L2_MMU_CONFIG is an implementation-defined register. Different Mali GPUs
define slightly different MAX_READS and MAX_WRITES fields, which
throttle outstanding reads and writes when set to non-zero values. When
left as zero, reads and writes are not throttled.
Both kbase a
From: Alyssa Rosenzweig
Add the HW_FEATURE_CLEAN_ONLY_SAFE bit based on kbase. When I actually
tried to port the logic from kbase, trivial jobs raised Data Invalid
Faults, so this may depend on other coherency details. It's still useful
to have the bit to record the feature bit when adding new mo
From: Alyssa Rosenzweig
Add the features, issues, and GPU ID for Mali-G57, a first-generation
Valhall GPU. Other first- and second-generation Valhall GPUs should be
similar.
Signed-off-by: Alyssa Rosenzweig
---
drivers/gpu/drm/panfrost/panfrost_features.h | 12
drivers/gpu/drm/pan
From: Alyssa Rosenzweig
The most important Valhall-specific quirks have been handled, so add the
Valhall compatible and probe.
Signed-off-by: Alyssa Rosenzweig
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.
Update function name.
Signed-off-by: Andrey Grodzovsky
Reported-by: kernel test robot
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index
On Fri, Feb 11, 2022 at 3:55 PM Andrey Grodzovsky
wrote:
>
> Update function name.
>
> Signed-off-by: Andrey Grodzovsky
> Reported-by: kernel test robot
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> di
On Fri, Feb 11, 2022 at 01:32:39PM -0600, Mario Limonciello wrote:
> This PCI class definition of the USB4 device is currently located only in
> the thunderbolt driver.
>
> It will be needed by a few other drivers for upcoming changes. Move it into
> the common include file.
>
> Acked-by: Alex De
Update subject to something like:
PCI: pciehp: Quirk broken Command Completed support on Intel Thunderbolt
controllers
On Fri, Feb 11, 2022 at 01:32:40PM -0600, Mario Limonciello wrote:
> The `is_thunderbolt` check is currently used to indicate the lack of
> command completed support for a num
On Fri, Feb 11, 2022 at 01:32:41PM -0600, Mario Limonciello wrote:
> `pci_bridge_d3_possible` currently checks explicitly for a Thunderbolt
> controller to indicate that D3 is possible. As this is used solely
> for older Apple systems, move it into a quirk that enumerates across
> all Intel TBT co
On Fri, Feb 11, 2022 at 01:32:43PM -0600, Mario Limonciello wrote:
> The root port used for PCIe tunneling should be marked as removable to
> ensure that the entire chain is marked removable.
>
> This can be done by looking for the device property specified in
> the ACPI tables `usb4-host-interfac
On Fri, Feb 11, 2022 at 01:32:44PM -0600, Mario Limonciello wrote:
> USB4 class devices are also removable like Intel Thunderbolt devices.
Spec reference, please.
> Drivers of downstream devices use this information to declare functional
> differences in how the drivers perform by knowing that th
On 2/11/2022 15:35, Bjorn Helgaas wrote:
On Fri, Feb 11, 2022 at 01:32:41PM -0600, Mario Limonciello wrote:
`pci_bridge_d3_possible` currently checks explicitly for a Thunderbolt
controller to indicate that D3 is possible. As this is used solely
for older Apple systems, move it into a quirk tha
Hi Dave, Daniel,
New stuff for 5.18.
The following changes since commit 4efdddbce7c1329f00c458e85dcaf105aebdc0ed:
Merge tag 'amd-drm-next-5.17-2022-01-12' of
https://gitlab.freedesktop.org/agd5f/linux into drm-next (2022-01-14 15:42:28
+0100)
are available in the Git repository at:
https
Make the subject specific, not just "appropriately." I think you're
marking something *removable*, so include that.
On Fri, Feb 11, 2022 at 01:32:45PM -0600, Mario Limonciello wrote:
> Discrete USB4 controllers won't have ACPI nodes specifying which
> PCIe or XHCI port they are linked with.
>
>
On Thu, Feb 10, 2022 at 04:43:21PM -0600, Mario Limonciello wrote:
> This PCI class definition of the USB4 device is currently located only in
> the thunderbolt driver.
>
> It will be needed by a few other drivers for upcoming changes. Move it into
> the common include file.
>
> Acked-by: Alex De
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