Hi Chen-Yu,
On Mon, Jan 17, 2022 at 05:01:52PM +0800, Chen-Yu Tsai wrote:
> On Sat, Jan 15, 2022 at 7:03 AM Brian Norris wrote:
> >
> > Now that the cdn-dp driver supports plug-change callbacks, let's wire it
> > up.
> >
> > Signed-off-by: Brian Norris
> > ---
> >
> > (no changes since v1)
> >
>
Applied. Thanks!
Alex
On Tue, Jan 18, 2022 at 2:57 AM wrote:
>
> From: Minghao Chi
>
> Return value from amdgpu_bo_create_kernel() directly instead
> of taking this in another redundant variable.
>
> Reported-by: Zeal Robot
> Signed-off-by: Minghao Chi
> Signed-off-by: CGEL ZTE
> ---
> dri
On 1/18/2022 12:01 PM, Dmitry Baryshkov wrote:
On Tue, 18 Jan 2022 at 22:41, Abhinav Kumar wrote:
On 12/7/2021 2:29 PM, Dmitry Baryshkov wrote:
Currently the DSI driver has two separate paths: one if the next device
in a chain is a bridge and another one if the panel is connected
directl
On Tue, Jan 18, 2022 at 01:11:48PM -0600, Gustavo A. R. Silva wrote:
>
>
> On 1/5/22 11:35, Kees Cook wrote:
> > The link_status array was not large enough to read the Adjust Request
> > Post Cursor2 register, so remove the common helper function to avoid
> > an OOB read, found with a -Warray-bou
Quoting Kuogee Hsieh (2022-01-18 10:47:25)
> Current DP drivers have regulators, clocks, irq and phy are grouped
> together within a function and executed not in a symmetric manner.
> This increase difficulty of code maintenance and limited code scalability.
> This patch divides the driver life cyc
After a small fix to error capture code, we now can flush G2H during a
GT reset which simplifies code and seals some extreme corner case races.
v2:
(CI)
- Don't trigger GT reset from G2H handler
Signed-off-by: Matthew Brost
Matthew Brost (3):
drm/i915: Allocate intel_engine_coredump_alloc
Now that the error capture is fully decoupled from fence signalling
(request retirement to free memory, which is turn depends on resets) we
can safely flush the G2H handler during a GT reset. This is eliminates
corner cases where GuC generated G2H (e.g. engine resets) race with a GT
reset.
Signed-
The G2H handler needs to be flushed during a GT reset but a G2H
indicating engine reset failure can trigger a GT reset. Add a worker to
trigger the GT when a engine reset failure is received to break this
circular dependency.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc.
Allocate intel_engine_coredump_alloc with ALLOW_FAIL rather than
GFP_KERNEL do fully decouple the error capture from fence signalling.
Fixes: 8b91cdd4f8649 ("drm/i915: Use __GFP_KSWAPD_RECLAIM in the capture code")
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
1
On 1/18/22 20:00, Javier Martinez Canillas wrote:
> Hello Zack,
>
> On 1/17/22 19:03, Zack Rusin wrote:
>> From: Zack Rusin
>>
>> When sysfb_simple is enabled loading vmwgfx fails because the regions
>> are held by the platform. In that case remove_conflicting*_framebuffers
>> only removes the si
On Tuesday, 18 January 2022 17:58:58 CET Paul Cercueil wrote:
>
> Not at all. If the clock is disabled, the LCD controller is disabled,
> so all the registers read zero, this makes sense. You can only read the
> registers when the clock is enabled. On some SoCs, reading disabled
> registers can ev
The clock and data lanes of the DSI PHY have a calibration circuitry
feature. As per the MSM DSI PHY tuning guidelines, the drive strength
tuning can be done by adjusting rescode offset for hstop/hsbot, and
the drive level tuning can be done by adjusting the LDO output level
for the HSTX drive.
Si
pm_runtime_get_sync() increments the runtime PM usage counter even
when it returns an error code, thus a matching decrement is needed
on the error handling path to keep the counter balanced.
Signed-off-by: Yongzhi Liu
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 3 +++
1 file changed, 3 insertion
Hello,
syzbot found the following issue on:
HEAD commit:a33f5c380c4b Merge tag 'xfs-5.17-merge-3' of git://git.ker..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=17c4eb7fb0
kernel config: https://syzkaller.appspot.com/x/.config?x=dc846445c1d2060e
das
In most cases, the default values of DSI PHY tuning registers should be
sufficient as they are fully optimized. However, in some cases where
extreme board parasitics cause the eye shape to degrade, the override
bits can be used to improve the signal quality.
The general guidelines for DSI PHY tuni
DSI device attach to DSI host will be done with host device's lock
held.
Un-registering host in "device attach" error path (ex: probe retry)
will result in deadlock with below call trace and non operational
DSI display.
Startup Call trace:
[ 35.043036] rt_mutex_slowlock.constprop.21+0x184/0x1b
pm_runtime_get_sync() will increase the rumtime PM counter
even it returns an error. Thus a pairing decrement is needed
to prevent refcount leak. Fix this by replacing this API with
pm_runtime_resume_and_get(), which will not change the runtime
PM counter on error.
Signed-off-by: Yongzhi Liu
---
This series is to add DSI PHY tuning support in Qualcomm Snapdragon
SoCs with 10nm DSI PHY e.g. SC7180
In most cases the default values of DSI PHY tuning registers
should be sufficient as they are fully optimized. However, in
some cases (for example, where extreme board parasitics cause
the eye sh
Add support for MSM DSI PHY tuning configuration. Current design is
to support drive strength and drive level/amplitude tuning for
10nm PHY version, but this can be extended to other PHY versions.
Signed-off-by: Rajeev Nandan
---
Changes in v2:
- New.
- Split into generic code and 10nm-specifi
pm_runtime_get_sync() increments the runtime PM usage counter even
when it returns an error code, thus a matching decrement is needed
on the error handling path to keep the counter balanced.
Signed-off-by: Yongzhi Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 +++-
1 file changed, 3 in
Per VESA DisplayID Standard v2.0: Type VII Timing – Detailed Timing Data
Definitions were already provided as type I, but not used
Signed-off-by: Yaroslav Bolyukin
---
drivers/gpu/drm/drm_edid.c | 26 +-
include/drm/drm_displayid.h | 6 +++---
2 files changed, 20 inser
one>
On 2021-08-17 20:30, abhin...@codeaurora.org wrote:
On 2021-06-17 15:20, Dmitry Baryshkov wrote:
DPU interrupts code allows multiple callbacks per interrut. In reality
/interrupt
none of the interrupts is shared between blocks (and will probably
never
be). Drop support for registering m
On 1/12/2022 21:59, Matthew Brost wrote:
Realized that the GuC multi-lrc fini breadcrumb emit code is very
delicate as the math this code does relies on functions it calls to emit
a certain number of DWs. Add a few GEM_BUG_ONs to assert the math is
correct.
Signed-off-by: Matthew Brost
Looks go
On 1/18/2022 13:43, Matthew Brost wrote:
Allocate intel_engine_coredump_alloc with ALLOW_FAIL rather than
GFP_KERNEL do fully decouple the error capture from fence signalling.
s/do/to/
Fixes: 8b91cdd4f8649 ("drm/i915: Use __GFP_KSWAPD_RECLAIM in the capture code")
Does this really count as a
On 1/18/2022 13:43, Matthew Brost wrote:
The G2H handler needs to be flushed during a GT reset but a G2H
indicating engine reset failure can trigger a GT reset. Add a worker to
trigger the GT when a engine reset failure is received to break this
s/a/an/
circular dependency.
Signed-off-by: Mat
On 1/18/2022 13:43, Matthew Brost wrote:
Now that the error capture is fully decoupled from fence signalling
(request retirement to free memory, which is turn depends on resets) we
s/is/in/
With that fixed:
Reviewed-by: John Harrison
John.
can safely flush the G2H handler during a GT reset.
The 'phandle-array' type is a bit ambiguous. It can be either just an
array of phandles or an array of phandles plus args. Many schemas for
phandle-array properties aren't clear in the schema which case applies
though the description usually describes it.
The array of phandles case boils down to n
For a single pinctrl mode, it is not necessary to define pinctrl
properties as the tools always allow pinctrl properties.
Signed-off-by: Rob Herring
---
.../display/rockchip/rockchip,rk3066-hdmi.yaml | 8
Documentation/devicetree/bindings/input/gpio-keys.yaml | 6 --
.../d
Hey - so, the original issue here was that payloads were not always deleted
when we expected them to be - correct?
If I'm remembering that correctly, then (and I'm not 100% sure on this yet) I
might already have noticed something very possibly wonky in how we handle
payload allocations currently,
On Tue, 2022-01-18 at 20:58 -0500, Lyude Paul wrote:
> Hey - so, the original issue here was that payloads were not always deleted
> when we expected them to be - correct?
>
> If I'm remembering that correctly, then (and I'm not 100% sure on this yet)
> I
> might already have noticed something ver
On Tue, 2022-01-18 at 20:00 +0100, Javier Martinez Canillas wrote:
> Hello Zack,
>
> On 1/17/22 19:03, Zack Rusin wrote:
> > From: Zack Rusin
> >
> > When sysfb_simple is enabled loading vmwgfx fails because the regions
> > are held by the platform. In that case
> > remove_conflicting*_framebuff
On 2022/01/18 18:53, Andy Shevchenko wrote:
On Mon, Jan 17, 2022 at 02:15:48PM +0900, Esaki Tomohito wrote:
On 2022/01/14 23:16, Andy Shevchenko wrote:
On Fri, Jan 14, 2022 at 07:17:52PM +0900, Tomohito Esaki wrote:
The LINEAR modifier is advertised as default if a driver doesn't specify
modif
The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE
parameter's unit is Unit Interval(UI) and the minimum value is 8. Also,
kernel doc of the 'clk_pre' member of struct phy_configure_opts_mipi_dphy
mentions that it should be in UI. However, the dphy core driver wrongly
sets 'clk
On 11/25/2021 6:35 PM, Dmitry Baryshkov wrote:
DPU driver contains code to parse clock items from device tree into
special data struct and then enable/disable/set rate for the clocks
using that data struct. However the DPU driver itself uses only parsing
and enabling/disabling part (the rate sett
On Tue, 18 Jan 2022 16:47:34 +0100, Loic Poulain wrote:
> QCM2290 MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema for DPU device
> tree bindings
>
> Signed-off-by: Loic Poulain
> ---
> .../bindings/display/msm/dpu-qcm2290.yaml
On Wed, 19 Jan 2022 02:08:38 +0530, Rajeev Nandan wrote:
> In most cases, the default values of DSI PHY tuning registers should be
> sufficient as they are fully optimized. However, in some cases where
> extreme board parasitics cause the eye shape to degrade, the override
> bits can be used to imp
pm_runtime_get_sync() will increase the rumtime PM counter
even it returns an error. Thus a pairing decrement is needed
to prevent refcount leak. Fix this by replacing this API with
pm_runtime_resume_and_get(), which will not change the runtime
PM counter on error.
Signed-off-by: Yongzhi Liu
---
pm_runtime_get_sync() will increase the rumtime PM counter
even it returns an error. Thus a pairing decrement is needed
to prevent refcount leak. Fix this by replacing this API with
pm_runtime_resume_and_get(), which will not change the runtime
PM counter on error.
Signed-off-by: Yongzhi Liu
---
Hi,
22. 1. 17. 오후 6:55에 Robert Foss 이(가) 쓴 글:
> Hi Inki,
>
> On Fri, 14 Jan 2022 at 02:18, Inki Dae wrote:
>>
>> Hi Robert,
>>
>> 22. 1. 12. 오후 7:05에 Robert Foss 이(가) 쓴 글:
>>> Thank you again for catching this and submitting a revert.
>>>
>>> Reviewed-by: Robert Foss >>
>>> Applied to drm-misc-n
pm_runtime_get_sync() will increase the rumtime PM counter
even it returns an error. Thus a pairing decrement is needed
to prevent refcount leak. Fix this by replacing this API with
pm_runtime_resume_and_get(), which will not change the runtime
PM counter on error.
Signed-off-by: Yongzhi Liu
---
On Wed, Jan 19, 2022 at 4:18 AM Brian Norris wrote:
>
> Hi Chen-Yu,
>
> On Mon, Jan 17, 2022 at 05:01:52PM +0800, Chen-Yu Tsai wrote:
> > On Sat, Jan 15, 2022 at 7:03 AM Brian Norris
> > wrote:
> > >
> > > Now that the cdn-dp driver supports plug-change callbacks, let's wire it
> > > up.
> > >
>
Hi Paul,
> Am 18.01.2022 um 23:59 schrieb Paul Boddie :
>
> On Tuesday, 18 January 2022 17:58:58 CET Paul Cercueil wrote:
>>
>> Not at all. If the clock is disabled, the LCD controller is disabled,
>> so all the registers read zero, this makes sense. You can only read the
>> registers when the c
Quoting Tvrtko Ursulin (2022-01-17 18:02:50)
>
> On 17/01/2022 15:09, Andi Shyti wrote:
> > The GT has its own properties and in sysfs they should be grouped
> > in the 'gt/' directory.
> >
> > Create a 'gt/' directory in sysfs which will contain gt0...gtN
> > directories related to each tile con
Am 18.01.22 um 11:44 schrieb Arunpravin:
Move the base i915 buddy allocator code into drm
- Move i915_buddy.h to include/drm
- Move i915_buddy.c to drm root folder
- Rename "i915" string with "drm" string wherever applicable
- Rename "I915" string with "DRM" string wherever applicable
- Fix heade
Add some helpers under lib/string_helpers.h so they can be used
throughout the kernel. When I started doing this there were 2 other
previous attempts I know of, not counting the iterations each of them
had:
1) https://lore.kernel.org/all/20191023131308.9420-1-jani.nik...@intel.com/
2)
https://lor
Follow the yes/no logic and add helpers for enabled/disabled and
enable/disable - those are not so common throughout the kernel,
but they give a nice way to reuse the strings to log things as
enabled/disabled or enable/disable.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_utils.h
There are a few implementations of yesno() in the tree. Consolidate them
in include/linux/string_helpers.h. Quite a few users of open coded
yesno() could later be converted to the new function:
$ git grep '?\s*"yes"\s*' | wc -l
286
$ git grep '?\s*"no"\s*' | wc -l
20
The inlined function should
linux/string_helpers.h provides a helper to return "yes"/"no"
strings. Replace the open coded versions with yesno(). The places were
identified with the following semantic patch:
@@
expression b;
@@
- b ? "yes" : "no"
+ yesno(b)
Then the includes were adde
On 19.01.2022 03:37, Liu Ying wrote:
The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE
parameter's unit is Unit Interval(UI) and the minimum value is 8. Also,
kernel doc of the 'clk_pre' member of struct phy_configure_opts_mipi_dphy
mentions that it should be in UI. Howeve
On 19/01/2022 02:50, Rob Herring wrote:
> The 'phandle-array' type is a bit ambiguous. It can be either just an
> array of phandles or an array of phandles plus args. Many schemas for
> phandle-array properties aren't clear in the schema which case applies
> though the description usually describes
On 19/01/2022 02:53, Rob Herring wrote:
> For a single pinctrl mode, it is not necessary to define pinctrl
> properties as the tools always allow pinctrl properties.
>
> Signed-off-by: Rob Herring
> ---
> .../display/rockchip/rockchip,rk3066-hdmi.yaml | 8
> Documentation/devic
On 18-01-22, 19:50, Rob Herring wrote:
> The 'phandle-array' type is a bit ambiguous. It can be either just an
> array of phandles or an array of phandles plus args. Many schemas for
> phandle-array properties aren't clear in the schema which case applies
> though the description usually describes
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