Remove a hack required because schedule disable done G2H was received
before context reset G2H in GuC firmware 62.0.0. Since we have upgraded
69.0.3, this is no longer required.
Also revive selftest which proves this works before / after change.
v2:
- Address John Harrion's comments
Signed-off
Add a cancel request selftest that results in an engine reset to cancel
the request as it is non-preemptable. Also insert a NOP request after
the cancelled request and confirm that it completes successfully.
v2:
(Tvrtko)
- Skip test if preemption timeout compiled out
- Skip test if engine res
In the i915 there are several hacks in place to make request cancellation
work with an old version of the GuC which delivered the G2H indicating
schedule disable is done before G2H indicating a context reset. Version
69 fixes this, so we can remove these hacks.
v2:
(Checkpatch)
- s/cancelation/
Applied. Thanks!
Alex
On Thu, Jan 13, 2022 at 8:38 AM Chen, Guchun wrote:
>
> Series is:
> Reviewed-by: Guchun Chen
>
> Regards,
> Guchun
>
> -Original Message-
> From: Yang Li
> Sent: Thursday, January 13, 2022 3:12 PM
> To: airl...@linux.ie; Chen, Guchun
> Cc: dan...@ffwll.ch; Deuc
On 1/13/2022 10:13, Matthew Brost wrote:
Add a cancel request selftest that results in an engine reset to cancel
the request as it is non-preemptable. Also insert a NOP request after
the cancelled request and confirm that it completes successfully.
v2:
(Tvrtko)
- Skip test if preemption tim
On Fri, Nov 12, 2021 at 11:47 AM Jagan Teki wrote:
>
> Replace atomic version of the enable/disable operations to
> continue the transition to the atomic API.
>
> Also added default drm atomic operations for duplicate, destroy
> and reset state API's in order to have smooth transition on
> atomic
Quoting Kuogee Hsieh (2022-01-13 09:51:42)
>
> On 1/12/2022 8:13 PM, Stephen Boyd wrote:
> - if (dp->usbpd->orientation == ORIENTATION_CC2)
> - flip = true;
> + dp_power_init(dp->power, false);
> + dp_ctrl_reset_irq_ctrl(dp->ctrl, true);
> +
Hi Biju,
On Thu, Jan 13, 2022 at 2:45 PM Biju Das wrote:
>
> Hi All,
>
> RZ/G2{H, M, N} SoC has dw_hdmi IP and it was working ok(colour) till the
> commit
> 7cd70656d1285b79("drm/bridge: display-connector: implement bus fmts
> callbacks").
>
> After this patch, the screen becomes greenish(may b
Hi Maxime,
I love your patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-intel/for-linux-next v5.16 next-20220113]
[cannot apply to anholt/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting
On 1/13/2022 11:47 AM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-01-13 09:51:42)
On 1/12/2022 8:13 PM, Stephen Boyd wrote:
- if (dp->usbpd->orientation == ORIENTATION_CC2)
- flip = true;
+ dp_power_init(dp->power, false);
+ dp_ctrl_reset_irq_ctrl(dp->ctrl,
Quoting Maxime Ripard (2022-01-12 03:46:52)
> Hi Stephen,
>
> Thanks for your answer
>
> On Tue, Jan 11, 2022 at 07:37:15PM -0800, Stephen Boyd wrote:
> > Sorry for being super delayed on response here. I'm buried in other
> > work. +Jerome for exclusive clk API.
> >
> > Quoting Maxime Ripard (2
Group below 4 dp driver related patches into one series.
Kuogee Hsieh (4):
drm/msm/dp: do not initialize phy until plugin interrupt received
drm/msm/dp: populate connector of struct dp_panel
drm/msm/dp: add support of tps4 (training pattern 4) for HBR3
drm/msm/dp: stop link training afte
Current DP drivers have regulators, clocks, irq and phy are grouped
together within a function and executed not in a symmetric manner.
This increase difficulty of code maintenance and limited code scalability.
This patch divides the driver life cycle of operation into four states,
resume (including
DP CTS test case 4.2.2.6 has valid edid with bad checksum on purpose
and expect DP source return correct checksum. During drm edid read,
correct edid checksum is calculated and stored at
connector::real_edid_checksum.
The problem is struct dp_panel::connector never be assigned, instead the
connect
From: Kuogee Hsieh
Some DP sinkers prefer to use tps4 instead of tps3 during training #2.
This patch will use tps4 to perform link training #2 if sinker's DPCD
supports it.
Changes in V2:
-- replace dp_catalog_ctrl_set_pattern() with
dp_catalog_ctrl_set_pattern_state_bit()
Changes in V3:
--
Each DP link training contains link training 1 followed by link
training 2. There is maximum of 5 retries of DP link training
before declared link training failed. It is required to stop link
training at end of link training 2 if it is failed so that next
link training 1 can start freshly. This pa
Quoting Kuogee Hsieh (2022-01-13 12:44:16)
>
> On 1/13/2022 11:47 AM, Stephen Boyd wrote:
> > Quoting Kuogee Hsieh (2022-01-13 09:51:42)
> >> On 1/12/2022 8:13 PM, Stephen Boyd wrote:
> >> - if (dp->usbpd->orientation == ORIENTATION_CC2)
> >> - flip = true;
> >> +
Helge Deller writes:
> I may have missed some discussions, but I'm objecting against this patch:
>
> b3ec8cdf457e5 ("fbdev: Garbage collect fbdev scrolling acceleration,
> part 1 (from TODO list)")
>
> Can we please (partly) revert it and restore the scrolling behaviour,
> where fbcon uses
On 1/13/2022 1:52 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-01-13 12:44:16)
On 1/13/2022 11:47 AM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-01-13 09:51:42)
On 1/12/2022 8:13 PM, Stephen Boyd wrote:
- if (dp->usbpd->orientation == ORIENTATION_CC2)
- flip =
Reviewed-by: Robert Foss
Applied to drm-misc-next.
On Thu, 13 Jan 2022 at 20:43, Jagan Teki wrote:
>
> On Fri, Nov 12, 2021 at 11:47 AM Jagan Teki
> wrote:
> >
> > Replace atomic version of the enable/disable operations to
> > continue the transition to the atomic API.
> >
> > Also added defa
Quoting Kuogee Hsieh (2022-01-13 14:14:27)
>
> On 1/13/2022 1:52 PM, Stephen Boyd wrote:
> > Quoting Kuogee Hsieh (2022-01-13 12:44:16)
> >> On 1/13/2022 11:47 AM, Stephen Boyd wrote:
> >>> Quoting Kuogee Hsieh (2022-01-13 09:51:42)
> On 1/12/2022 8:13 PM, Stephen Boyd wrote:
> -
On Thu, Jan 13, 2022 at 5:05 AM Christian König
wrote:
> Am 13.01.22 um 14:00 schrieb Ruhl, Michael J:
> >> -Original Message-
> >> From: dri-devel On Behalf Of
> >> Ruhl, Michael J
> >>> -Original Message-
> >>> From: dri-devel On Behalf Of
> >>> guangming@mediatek.com
> >>>
Group below 4 dp driver related patches into one series.
Kuogee Hsieh (4):
drm/msm/dp: do not initialize phy until plugin interrupt received
drm/msm/dp: populate connector of struct dp_panel
drm/msm/dp: add support of tps4 (training pattern 4) for HBR3
drm/msm/dp: stop link training afte
Current DP drivers have regulators, clocks, irq and phy are grouped
together within a function and executed not in a symmetric manner.
This increase difficulty of code maintenance and limited code scalability.
This patch divides the driver life cycle of operation into four states,
resume (including
DP CTS test case 4.2.2.6 has valid edid with bad checksum on purpose
and expect DP source return correct checksum. During drm edid read,
correct edid checksum is calculated and stored at
connector::real_edid_checksum.
The problem is struct dp_panel::connector never be assigned, instead the
connect
Each DP link training contains link training 1 followed by link
training 2. There is maximum of 5 retries of DP link training
before declared link training failed. It is required to stop link
training at end of link training 2 if it is failed so that next
link training 1 can start freshly. This pa
From: Kuogee Hsieh
Some DP sinkers prefer to use tps4 instead of tps3 during training #2.
This patch will use tps4 to perform link training #2 if sinker's DPCD
supports it.
Changes in V2:
-- replace dp_catalog_ctrl_set_pattern() with
dp_catalog_ctrl_set_pattern_state_bit()
Changes in V3:
--
On Thu, Jan 13, 2022 at 6:19 PM Philippe Cornu
wrote:
>
> DRM DRIVERS FOR STI
> -M: Benjamin Gaignard
> L: dri-devel@lists.freedesktop.org
> S: Maintained
> T: git git://anongit.freedesktop.org/drm/drm-misc
If there is no longer a maintainer, I suppose it should also be marke
Hi Robert,
22. 1. 12. 오후 7:05에 Robert Foss 이(가) 쓴 글:
> Thank you again for catching this and submitting a revert.
>
> Reviewed-by: Robert Foss
> Applied to drm-misc-next.
>
Trivial thing I think but just notice. With this applying - original patch set
and revert one, merge conflict may happe
Hi Daniel-san,
Thank you for your comments.
On 2022/01/13 22:44, Daniel Stone wrote:
Hi Esaki-san,
On Thu, 13 Jan 2022 at 09:44, Tomohito Esaki wrote:
Some drivers whose planes only support linear layout fb do not support format
modifiers.
These drivers should support modifiers, however the
Hi,
Thank you for your comment.
On 2022/01/14 2:56, Bas Nieuwenhuizen wrote:
I think we'll also want to do a conditional disable for DC
(drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c) since it only
enables modifiers on newer HW. Something like "if (modifiers == NULL)
fb_modifiers_not_suppo
Quoting Kuogee Hsieh (2022-01-13 15:53:36)
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index 7cc4d21..b3c5404 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -83,6 +83,7 @@ struct dp_display_privat
The chip register layout has nothing to do with MIPI DCS, the registers
incorrectly marked as MIPI DCS in the driver are regular chip registers
often with completely different function.
Fill in the actual register names and bits from [1] and [2] and add the
entire register layout, since the docume
Use the atomic version of the enable/disable operations to continue
the transition to the atomic API, started with the introduction of
.atomic_get_input_bus_fmts(). This will be needed to access the mode
from the atomic state.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Robert Foss
Cc: Sam Ra
Retrieve display mode structure from panel or atomic state in
bridge_to_mode(). This completes the transition to the atomic
API.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Robert Foss
Cc: Sam Ravnborg
Cc: Thomas Zimmermann
To: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/bridge/chi
The HFP_HSW_HBP_HI register must be programmed with 2 LSbits of each
Horizontal Front Porch/Sync/Back Porch. Currently the driver programs
this register to 0, which breaks displays with either value above 255.
The HFP_MIN register must be set to the same value as HFP_LI, otherwise
there is visible
The chip is capable of swapping DPI RGB channels. The driver currently
does not implement support for this functionality. Write the MIPI_PN_SWAP
register to 0 to assure the color swap is disabled.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Robert Foss
Cc: Sam Ravnborg
Cc: Thomas Zimmermann
The chip contains fractional PLL, however the driver currently hard-codes
one specific PLL setting. Implement generic PLL parameter calculation code,
so any DPI panel with arbitrary pixel clock can be attached to this bridge.
The datasheet for this bridge is not available, the PLL behavior has bee
The ICN6211 chip starts in I2C configuration mode after cold boot.
Implement support for configuring the chip via I2C in addition to
the current DSI LP command mode configuration support. The later
seems to be available only on chips which have additional MCU on
the panel/bridge board which preconf
The driver currently hard-codes DSI lane count to two, however the chip
is capable of operating in 1..4 DSI lanes mode. Parse 'data-lanes' DT
property and program the result into DSI_CTRL register.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Robert Foss
Cc: Sam Ravnborg
Cc: Thomas Zimmermann
Rename function ICN6211_DSI() to chipone_writeb() to keep all function
names lower-case. No functional change.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Robert Foss
Cc: Sam Ravnborg
Cc: Thomas Zimmermann
To: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/bridge/chipone-icn6211.c | 5
The DSI burst mode is more energy efficient than the DSI sync pulse mode,
make use of the burst mode since the chip supports it as well. Disable the
generation of EoT packet, the chip ignores it, so no point in emitting it.
Enable transmission of data in LP mode, otherwise register read via DSI
doe
Implement .atomic_get_input_bus_fmts callback, which sets up the
input (DSI-end) format, and that format can then be used in pipeline
format negotiation between the DSI-end of this bridge and the other
component closer to the scanout engine.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Robert F
The driver currently hard-codes HS/VS polarity to active-low and DE to
active-high, which is not correct for a lot of supported DPI panels.
Add the missing mode flag handling for HS/VS/DE polarity.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Robert Foss
Cc: Sam Ravnborg
Cc: Thomas Zimmermann
Both example code [1], [2] as well as one provided by custom panel vendor
set register SYS_CTRL_1 to 0x88. What exactly does the value mean is unknown
due to unavailable datasheet. Align this register value with example code.
[1]
https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/
Read out the Vendor/Chip/Version ID registers from the chip before
performing any configuration, and validate that the registers have
correct values. This is mostly a simple test whether DSI register
access does work, since that tends to be broken on various bridges.
Signed-off-by: Marek Vasut
Cc
On Fri, 2022-01-07 at 10:23 +0100, AngeloGioacchino Del Regno wrote:
> Il 06/01/22 10:13, Chunfeng Yun ha scritto:
> > On Mon, 2022-01-03 at 15:53 +0100, AngeloGioacchino Del Regno
> > wrote:
> > > Use the dev_err_probe() helper to simplify error handling during
> > > probe.
> > >
> > > Signed-off
Hi, Nancy:
On Mon, 2022-01-10 at 16:46 +0800, Nancy.Lin wrote:
> Add drm ovl_adaptor sub driver. Bring up ovl_adaptor sub driver if
> the component exists in the path.
>
> Signed-off-by: Nancy.Lin
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 16
> drivers/gpu/drm/mediatek/mtk_
ctx->next_bridge is checked for NULL twice in a row. The second
conditional is redundant, so remove it.
Signed-off-by: Drew Davenport
---
drivers/gpu/drm/bridge/ite-it66121.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ite-it66121.c
b/drivers/gpu/drm/bridge/ite-
Am 14.01.22 um 00:26 schrieb John Stultz:
On Thu, Jan 13, 2022 at 5:05 AM Christian König
wrote:
Am 13.01.22 um 14:00 schrieb Ruhl, Michael J:
-Original Message-
From: dri-devel On Behalf Of
Ruhl, Michael J
-Original Message-
From: dri-devel On Behalf Of
guangming@mediat
The VOP in Rockchip SoCs that support YUV planes also support swapping
of the U and V elements. Supporting the swapped variants, especially
NV21, would be beneficial for multimedia applications, as the hardware
video decoders only output NV21, and supporting this pixel format in
the display pipelin
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