Hi,
the first of the two patches concludes the first stage of
refactoring which makes the use of intel_gt on the different
subsystem. It's taken from Matt's series and it has alread been
reviewed. The patch has just been replaced before any multitile
patches and I think it can be already pushed.
From: Michał Winiarski
We now support a per-gt uncore, yet we're not able to infer which GT
we're operating upon. Let's store a backpointer for now.
Signed-off-by: Michał Winiarski
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel
Starting from a patch from Matt to_root_gt() returns the
reference to the root tile in order to abstract the root tile
from th callers.
Being the root tile identified as tile '0', embed the id in the
name so that i915->gt becomes i915->gt0.
The renaming has been mostly done with the following com
After 5fa6863ba692 ("spi: Check we have a spi_device_id for each DT
compatible") we need the following to make the SPI core happy.
Works for me with a SH1106-based OLED display.
Signed-off-by: Heiner Kallweit
---
drivers/staging/fbtft/fbtft.h | 7 +++
1 file changed, 7 insertions(+)
diff -
On 11/27/21 5:05 PM, Jonathan Cameron wrote:
Non-coherent mapping with no cache sync:
- fileio:
read: 156 MiB/s
write: 123 MiB/s
- dmabuf:
read: 234 MiB/s (capped by sample rate)
write: 182 MiB/s
Non-coherent reads with no cache sync + write-combine writes:
https://bugzilla.kernel.org/show_bug.cgi?id=205089
--- Comment #30 from David Nichols (da...@qore.org) ---
The amdgpu problems in my system were completely and definitively resolved with
a memcpy() patch to glibc:
https://gist.github.com/jnettlet/f6f8b49bb7c731255c46f541f875f436
The SoC I'm using
Hi Tzung-Bi,
Thanks for the reviews.
On Thu, 2021-11-18 at 13:55 +0800, Tzung-Bi Shih wrote:
> On Wed, Nov 17, 2021 at 02:41:56PM +0800, jason-jh.lin wrote:
>
> Typo in the commit title "mialbox: move cmdq suspend,resume and
> remove after cmdq_mbox_flush".
>
> s/mialbox/mailbox/
--
I'll fix t
Hi Tzung-Bi,
Thanks, I'll fix it.
On Thu, 2021-11-18 at 13:54 +0800, Tzung-Bi Shih wrote:
> On Wed, Nov 17, 2021 at 02:41:55PM +0800, jason-jh.lin wrote:
> > Subject: [PATCH 0/3] Fix drm suspend and resume issue
>
> You have 2 Subjects. The first one takes precedence.
--
Regards,
Jason-JH Lin
Hi Chun-Kuang,
Thanks for the reviews.
On Fri, 2021-11-19 at 08:01 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin 於 2021年11月17日 週三 下午2:42寫道:
> >
> > CMDQ driver will occupy GCE clock to execute the task in GCE
> > thread.
> >
> > So call cmdq_mbox_flush to clear all task in GCE thr
Hi Tzung-Bi,
Thanks for the reviews.
> From: Linux-mediatek On
> Behalf Of Tzung-Bi Shih
> Sent: Thursday, November 18, 2021 1:55 PM
> To: Jason-JH Lin (林睿祥)
> Cc: Chun-Kuang Hu ; Philipp Zabel <
> p.za...@pengutronix.de>; Matthias Brugger ;
> Jassi Brar ; David Airlie linux-media...@lists.inf
Hi Tzung-Bi,
Thanks for the reviews.
> From: Linux-mediatek On
> Behalf Of Tzung-Bi Shih
> Sent: Thursday, November 18, 2021 1:55 PM
> To: Jason-JH Lin (林睿祥)
> Cc: Chun-Kuang Hu ; Philipp Zabel <
> p.za...@pengutronix.de>; Matthias Brugger ;
> Jassi Brar ; David Airlie >; Daniel Vetter ; dri-d
'kfd->gtt_sa_bitmap' is a bitmap. So use 'bitmap_zalloc()' to simplify
code, improve the semantic and avoid some open-coded arithmetic in
allocator arguments.
Also change the corresponding 'kfree()' into 'bitmap_free()' to keep
consistency.
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 12 +++
All uses of the 'kfd->gtt_sa_bitmap' bitmap are protected with the
'kfd->gtt_sa_lock' mutex.
So:
- prefer the non-atomic '__set_bit()' function
- use the non-atomic 'bitmap_[set|clear]()' functions instead of
equivalent 'for' loops. These functions can work on several bits at a
tim
Hi Dave & Daniel,
A few fixes for v5.16.
The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf:
Linux 5.16-rc1 (2021-11-14 13:56:52 -0800)
are available in the Git repository at:
https://gitlab.freedesktop.org/drm/msm.git drm-msm-fixes-2021-11-28
for you to fetch cha
https://bugzilla.kernel.org/show_bug.cgi?id=214921
--- Comment #7 from Paul Gover (pmw.go...@yahoo.co.uk) ---
Kernel 5.15.5 (which IIUC contains the patch or equivalent) works for me.
--
You may reply to this email to add a comment.
You are receiving this mail because:
You are watching the assi
The only usage of cooling_ops is to pass its address to
thermal_of_cooling_device_register(), which takes a pointer to const
struct thermal_cooling_device_ops as input. Make it const to allow the
compiler to put it in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/etnaviv/
28.11.2021 08:47, Michał Mirosław пишет:
> On Sun, Nov 14, 2021 at 10:34:08PM +0300, Dmitry Osipenko wrote:
>> Add runtime power management and support generic power domains.
> [...]
>> @@ -104,10 +127,17 @@ static int gr2d_open_channel(struct tegra_drm_client
>> *client,
>>
28.11.2021 08:40, Michał Mirosław пишет:
> On Sun, Nov 14, 2021 at 10:33:56PM +0300, Dmitry Osipenko wrote:
>> This series adds runtime PM support to Tegra drivers and enables core
>> voltage scaling for Tegra20/30 SoCs, resolving overheating troubles.
>>
>> All patches in this series are interdepe
Hi,
On 25/11/2021 18:09, AngeloGioacchino Del Regno wrote:
Since commit 8f59ee9a570c ("drm/msm/dsi: Adjust probe order"), the
DSI host gets initialized earlier, but this caused unability to probe
the entire stack of components because they all depend on interrupts
coming from the main `mdss` nod
This series adds support for multi hardware decode into mtk-vcodec, by first
adding use
of_platform_populate to manage each hardware information: interrupt, clock,
register
bases and power. Secondly add core work queue to deal with core hardware
message,
at the same time, add msg queue for diffe
Different platform may has different numbers of register bases. Gets the
numbers of register bases from DT (sizeof(u32) * 4 bytes for each).
Reviewed-by: Tzung-Bi Shih
Signed-off-by: Yunfei Dong
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 37 ++-
1 file changed, 28 insert
Using the needed param for pm init/release function and remove unused
param mtkdev in 'struct mtk_vcodec_pm'.
Reviewed-by: Tzung-Bi Shih
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Yunfei Dong
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 6 ++---
.../platform/mtk-vcodec/mtk
Vdec and venc can use the same function to wake up interrupt event.
Reviewed-by: Tzung-Bi Shih
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Yunfei Dong
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 9 +
drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h |
From: Yunfei Dong
Adds MT8192's compatible "mediatek,mt8192-vcodec-dec".
Adds MT8192's device private data mtk_lat_sig_core_pdata.
Signed-off-by: Yunfei Dong
---
.../media/platform/mtk-vcodec/mtk_vcodec_dec.h | 1 +
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 4
.../mtk-vcodec/
Register each hardware as platform device, need to call pm functions
to open/close power and clock from module mtk-vcodec-dec, export these
functions.
Signed-off-by: Yunfei Dong
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/dr
Separate decoder and encoder document for the dts are big difference.
Reviewed-by: Rob Herring
Signed-off-by: Yunfei Dong
---
.../media/mediatek,vcodec-decoder.yaml| 176 +
.../media/mediatek,vcodec-encoder.yaml| 187 ++
.../bindings/media/mediatek
Add work queue to process core hardware information.
First, get lat_buf from message queue, then call core
hardware of each codec(H264/VP9/AV1) to decode, finally
puts lat_buf back to the message.
Signed-off-by: Yunfei Dong
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 16 +++-
.../pla
Adds irq interface for multi hardware.
Signed-off-by: Yunfei Dong
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 33 ---
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.c | 2 +-
.../platform/mtk-vcodec/mtk_vcodec_drv.h | 25 ++
.../platform/mtk-vcodec/mtk_vcod
Separates different architecture for hardware: pure_sin_core
and lat_sin_core. MT8183 is pure single core. Uses .hw_arch to
distinguish.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
.../platform/mtk-vcodec/mtk_vcodec_dec_stateful.c | 1 +
.../platform/mtk-vcodec
There are more than two hardwares for decoder: LAT0, LAT1 and CORE. In order to
manage these hardwares, register each hardware as independent platform device
for the larbs are different.
Each hardware module controls its own information which includes
interrupt/power/
clocks/registers.
Calling o
Add core dec and dec end ipi msg: AP_IPIMSG_DEC_CORE/AP_IPIMSG_DEC_CORE_END.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
.../media/platform/mtk-vcodec/vdec_ipi_msg.h | 4
.../media/platform/mtk-vcodec/vdec_vpu_if.c| 12
.../media/platform/mtk
Adds decoder dt-bindings for mt8192.
Signed-off-by: Yunfei Dong
---
Change example dtsi node.
Add more information for hardware block diagram.
---
.../media/mediatek,vcodec-subdev-decoder.yaml | 266 ++
1 file changed, 266 insertions(+)
create mode 100644
Documentation/devicetr
Generalizes power and clock on/off interfaces to support different hardware.
Signed-off-by: Yunfei Dong
---
.../platform/mtk-vcodec/mtk_vcodec_dec_drv.c | 6 +-
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.c | 2 +-
.../platform/mtk-vcodec/mtk_vcodec_dec_hw.h | 4 +
.../platform/mtk-vcodec/
For lat and core architecture, lat thread will send message to core
thread when lat decode done. Core hardware will use the message
from lat to decode, then free message to lat thread when decode done.
Signed-off-by: Yunfei Dong
---
drivers/media/platform/mtk-vcodec/Makefile| 1 +
.../plat
Use the dma_set_mask_and_coherent helper to set vdec
DMA bit mask to support 34bits iova space(16GB) that
the mt8192 iommu HW support.
Whole the iova range separate to 0~4G/4G~8G/8G~12G/12G~16G,
regarding which iova range VDEC actually locate, it
depends on the dma-ranges property of vdec dtsi nod
For add new hardware, not only need to lock lat hardware, also
need to lock core hardware in case of different instance start
to decoder at the same time.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c | 4 ++--
dri
There are only two lines in mtk_vcodec_release_enc_pm, using
pm_runtime_disable and put_device instead directly.
Move pm_runtime_enable outside mtk_vcodec_release_enc_pm to symmetry with
pm_runtime_disable, after that, rename mtk_vcodec_init_enc_pm to *_clk since
it only has clock operations now.
There are only two lines in mtk_vcodec_release_dec_pm, using
pm_runtime_disable and put_device instead directly.
Move pm_runtime_enable outside mtk_vcodec_init_dec_pm to symmetry with
pm_runtime_disable, after that, rename mtk_vcodec_init_dec_pm to *_clk since
it only has clock operations now.
Si
There is just one core thread, in order to separate different
hardware, using codec type to separeate it in scp driver.
Signed-off-by: Yunfei Dong
Reviewed-by: AngeloGioacchino Del Regno
---
.../media/platform/mtk-vcodec/vdec_ipi_msg.h | 12 ---
.../media/platform/mtk-vcodec/vdec_vpu_if.c
Mark 'tidss_pm_ops' as __maybe_unused to avoid
the warning: unused variable 'tidss_pm_ops'
Fixes: 6e120594631f ("drm/tidss: Make use of the helper macro
SET_RUNTIME_PM_OPS()")
Signed-off-by: Cai Huoqing
---
drivers/gpu/drm/tidss/tidss_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
If a dma_fence_array is reported signaled by a call to
dma_fence_is_signaled(), it may leak the PENDING_ERROR status.
Fix this by clearing the PENDING_ERROR status if we return true in
dma_fence_array_signaled().
Fixes: 1f70b8b812f3 ("dma-fence: Propagate errors to dma-fence-array container")
Cc:
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