https://bugzilla.kernel.org/show_bug.cgi?id=215003
--- Comment #6 from Xiaolei Yu (dreifachst...@gmail.com) ---
(In reply to Lukas Wunner from comment #5)
> Hm, why are runtime services disabled? Are you using "noefi" or
> "efi=noruntime" on the command line or is this perhaps an RT kernel? Could
https://bugzilla.kernel.org/show_bug.cgi?id=215003
--- Comment #7 from Lukas Wunner (lu...@wunner.de) ---
The gpu-switch utility I've linked to above has macOS and Windows versions. You
could try using it from one of those OSes to switch to the iGPU on next boot,
then boot into Linux.
Perhaps you
On Thu, Nov 11, 2021 at 03:02:04PM -0700, Jim Cromie wrote:
> Sean Paul proposed, in:
> https://patchwork.freedesktop.org/series/78133/
> drm/trace: Mirror DRM debug logs to tracefs
>
> His patchset's objective is to be able to independently steer some of
> the drm.debug stream to an alternate tra
This patch series deals with async migration and async vram management.
It still leaves an important part out, which is async unbinding which
will reduce latency further, at least when trying to migrate already active
objects.
Patches 1/6 and 2/6 deal with accessing and waiting for the TTM moving
From: Maarten Lankhorst
We want to get rid of i915_vma tracking to simplify the code and
lifetimes. Add a way to set/put the moving fence, in preparation for
removing the tracking.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 37 ++
driv
Move the i915_gem_obj_copy_ttm() function to i915_gem_ttm_move.h.
This will help keep a number of functions static when introducing
async moves.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 47 ---
drivers/gpu/drm/i915/gem/i915_gem_ttm.h |
From: Maarten Lankhorst
For now, we will only allow async migration when TTM is used,
so the paths we care about are related to TTM.
The mmap path is handled by having the fence in ttm_bo->moving,
when pinning, the binding only becomes available after the moving
fence is signaled, and pinning a
There is an interesting refcounting loop:
struct intel_memory_region has a struct ttm_resource_manager,
ttm_resource_manager->move may hold a reference to i915_request,
i915_request may hold a reference to intel_context,
intel_context may hold a reference to drm_i915_gem_object,
drm_i915_gem_object
Don't wait sync while migrating, but rather make the GPU blit await the
dependencies and add a moving fence to the object.
This also enables asynchronous VRAM management in that on eviction,
rather than waiting for the moving fence to expire before freeing VRAM,
it is freed immediately and the fen
Update the copy function i915_gem_obj_copy_ttm() to be asynchronous for
future users and update the only current user to sync the objects
as needed after this function.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 40 ++--
drivers/gpu/drm/i91
https://bugzilla.kernel.org/show_bug.cgi?id=213823
--- Comment #6 from Bruno Pagani (bruno.n.pag...@gmail.com) ---
So while I still don’t have time to setup bisecting, I’m now affected even on
LTS kernel. Also, I’ve been in touch with other users having a similar laptop
(the XPS version instead of
On Tue, Nov 09, 2021 at 08:05:23AM -0800, Randy Dunlap wrote:
On 11/8/21 11:54 PM, Pavel Machek wrote:
Hi!
This series is truncated .. I only got first patches. Similary, 5.10
series is truncated, [PATCH AUTOSEL 5.10 035/101] media: s5p-mfc: Add
checking to s5p_mfc_probe... is last one I got.
+CC: Ville Syrjälä
+CC: Daniel Vetter
On Sat, Nov 13, 2021 at 08:27:30PM +0100, Claudio Suarez wrote:
> The prefered way to log connectors is [CONNECTOR:id:name]. Change it in
> drm core programs.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Claudio Suarez
> ---
> drivers/gpu/drm/drm_
On Sat, Nov 13, 2021 at 08:27:30PM +0100, Claudio Suarez wrote:
> The prefered way to log connectors is [CONNECTOR:id:name]. Change it in
> drm core programs.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Claudio Suarez
> ---
> drivers/gpu/drm/drm_client_modeset.c | 51 ++
On Sat, Nov 13, 2021 at 09:39:46PM +0100, Sam Ravnborg wrote:
> Hi Claudio,
>
> On Sat, Nov 13, 2021 at 08:27:30PM +0100, Claudio Suarez wrote:
> > The prefered way to log connectors is [CONNECTOR:id:name]. Change it in
> > drm core programs.
> >
> > Suggested-by: Ville Syrjälä
> > Signed-off-by
This series adds runtime PM support to Tegra drivers and enables core
voltage scaling for Tegra20/30 SoCs, resolving overheating troubles.
All patches in this series are interdependent and should go via Tegra tree
for simplicity.
Changelog:
v15: - Added r-b from Ulf Hansson to "soc/tegra: Enable
Only couple drivers need to get the -ENODEV error code and majority of
drivers need to explicitly initialize the performance state. Add new
common helper which sets up OPP table for these drivers.
Reviewed-by: Ulf Hansson
Signed-off-by: Dmitry Osipenko
---
include/soc/tegra/common.h | 15 ++
GENPD core now can set up domain's performance state properly while device
is RPM-suspended. Runtime PM of a device must be enabled during setup
because GENPD checks whether device is suspended and check doesn't work
while RPM is disabled. Instead of replicating the boilerplate RPM-enable
code arou
Previously we assumed that devm_tegra_core_dev_init_opp_table() will
be used only by drivers that will always have device with OPP table,
but this is not true anymore. For example now Tegra30 will have OPP table
for PWM, but Tegra20 not and both use the same driver. Hence let's not
print the error
Memory Client should be blocked before hardware reset is asserted in order
to prevent memory corruption and hanging of memory controller.
Document Memory Client resets of Host1x, GR2D and GR3D hardware units.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../bindings/display/tegr
The Clock-and-Reset controller resides in a core power domain on NVIDIA
Tegra SoCs. In order to support voltage scaling of the core power domain,
we hook up DVFS-capable clocks to the core GENPD for managing of the
GENPD's performance state based on the clock changes.
Some clocks don't have any s
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on pre-Tegra186
SoCs.
Reviewed-by: Ulf Hansson
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Add runtime PM and OPP support to the Host1x driver. For the starter we
will keep host1x always-on because dynamic power management require a major
refactoring of the driver code since lot's of code paths are missing the
RPM handling and we're going to remove some of these paths in the future.
Rev
The HDMI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now HDMI driver must use
OPP API for driving the controller's clock rate because OPP API takes
care of reconfiguring the domain's performance state based on HDMI clock
rate. Add OPP suppo
Add runtime power management and support generic power domains.
Reviewed-by: Ulf Hansson
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/
Document sub-nodes which describe Tegra SoC clocks that require a higher
voltage of the core power domain in order to operate properly on a higher
clock rates. Each node contains a phandle to OPP table and power domain.
The root PLLs and system clocks don't have any specific device dedicated
to t
Add runtime power management and support generic power domains.
Reviewed-by: Ulf Hansson
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/
Document new DVFS OPP table and power domain properties of the Host1x bus
and devices sitting on the bus.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../display/tegra/nvidia,tegra20-host1x.txt | 49 +++
1 file changed, 49 insertions(+)
diff --git
a/Documenta
Add host1x_channel_stop() which waits till channel becomes idle and then
stops the channel hardware. This is needed for supporting suspend/resume
by host1x drivers since the hardware state is lost after power-gating,
thus the channel needs to be stopped before client enters into suspend.
Tested-by
Runtime PM is now universally available, make it mandatory by removing
the pm_runtime_enabled() checks.
Reviewed-by: Ulf Hansson
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/submit.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/te
The Tegra USB controller belongs to the core power domain and we're going
to enable GENPD support for the core domain. Now USB controller must be
resumed using runtime PM API in order to initialize the USB power state.
We already support runtime PM for the CI device, but CI's PM is separated
from t
Use resource-managed helpers to make code cleaner and more correct,
properly releasing all resources in case of driver probe error.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/fuse/fuse-tegra.c | 32 ++
drivers/soc/tegra/fuse/fuse-tegra20.c | 33 +++
The FUSE controller is enabled at a boot time. Reset it in order to put
hardware and clock into clean and disabled state.
Reviewed-by: Ulf Hansson
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/fuse/fuse-tegra.c | 25 +
drivers/soc/tegra/fuse/fuse.h | 1 +
2
Depending on hardware version, Tegra SoC may require a higher voltages
during resume from system suspend, otherwise hardware will crash. Set
SoC voltages to a nominal levels during suspend.
Link:
https://lore.kernel.org/all/a8280b5b-7347-8995-c97b-10b798cdf...@gmail.com/
Reviewed-by: Ulf Hansson
Currently driver supports legacy power domain API, this patch adds generic
power domain support. This allows us to utilize a modern GENPD API for
newer device-trees.
Reviewed-by: Ulf Hansson
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00
The GMI bus on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now GMI must be resumed using
runtime PM API in order to initialize the GMI power state. Add runtime PM
and OPP support to the GMI driver.
Reviewed-by: Ulf Hansson
Signed-off-by: Dmi
Runtime PM auto-suspension doesn't work without pm_runtime_mark_last_busy(),
add it.
Reviewed-by: Ulf Hansson
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/submit.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/tegra/submit.c b/drivers/gpu/drm/tegra/submit.c
ind
The PWM on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now PWM must be resumed using
runtime PM API in order to initialize the PWM power state. The PWM clock
rate must be changed using OPP API that will reconfigure the power domain
performance
CORE power domain uses name of device-tree node, which is inconsistent with
the names of PMC domains. Set the name to "core" to make it consistent.
Reviewed-by: Ulf Hansson
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
OPP table name now should start with "opp-table" and OPP entries
shouldn't contain commas and @ signs in accordance to the new schema
requirement. Reorganize CPU and EMC OPP table device-tree nodes.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra124-apalis-emc.dtsi| 4 +-
.../ar
All device drivers got runtime PM and OPP support. Flip the core domain
support status for Tegra20 and Tegra30 SoCs.
Reviewed-by: Ulf Hansson
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/tegra/pmc.
CDMA must be stopped before hardware is suspended. Add channel stopping
to RPM suspend callback. Add system level suspend-resume callbacks.
Runtime PM initialization is moved to host1x client init phase because
RPM callback now uses host1x channel that is available only when host1x
client is regis
Document new OPP table and power domain properties of the video decoder
hardware.
Reviewed-by: Rob Herring
Acked-by: Hans Verkuil
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/media/nvidia,tegra-vde.yaml | 12
1 file changed, 12 insertions(+)
diff --git a/Documentat
Convert NVIDIA Tegra video decoder binding to schema.
Reviewed-by: Rob Herring
Acked-by: Hans Verkuil
Signed-off-by: Dmitry Osipenko
---
.../bindings/media/nvidia,tegra-vde.txt | 64 ---
.../bindings/media/nvidia,tegra-vde.yaml | 107 ++
2 files changed, 107
The SDHCI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now SDHCI must be resumed using
runtime PM API in order to initialize the SDHCI power state. The SDHCI
clock rate must be changed using OPP API that will reconfigure the power
domain per
The NAND on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now NAND must be resumed using
runtime PM API in order to initialize the NAND power state. Add runtime PM
and OPP support to the NAND driver.
Reviewed-by: Ulf Hansson
Acked-by: Miquel R
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra20 SoC.
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20
Signed-off-by: Dmitry Osipenko
---
.../boot/dts/tegra20-acer-a500-picasso.dts| 1 +
arch/arm/boot/dts/tegra
Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Peter Geis # Ouya T30
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry O
Device-tree schema doesn't allow domain name to start with a number.
We don't use 3d domain yet in device-trees, so rename it to the name
used by Tegra TRMs: TD, TD2.
Reported-by: David Heidelberg
Reviewed-by: Ulf Hansson
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 8
The SPI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now SPI driver must use OPP
API for driving the controller's clock rate because OPP API takes care
of reconfiguring the domain's performance state in accordance to the
rate. Add OPP suppor
Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20
Signed-off-by:
Extend memory OPPs with 500MHz entry. This clock rate is used by ASUS
Transformer tablets.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30-peripherals-opp.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
b/a
MPE, VI, EPP and ISP were never used and we don't have drivers for them.
Since these modules are enabled by default in a device-tree, a device is
created for them, blocking voltage scaling because there is no driver to
bind, and thus, state of PMC driver is never synced. Disable them.
Signed-off-b
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra30 SoC.
Tested-by: Peter Geis # Ouya T30
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-trimslice.dts |2 +-
.../tegra30-asus-nexus7-group
CDMA must be stopped before hardware is suspended. Add channel stopping
to RPM suspend callback. Add system level suspend-resume callbacks.
Runtime PM initialization is moved to host1x client init phase because
RPM callback now uses host1x channel that is available only when host1x
client is regis
From: Svyatoslav Ryhel
Add definition of the HannStar HSD101PWW2 Rev0-A00/A01 LCD
SuperIPS+ HD panel.
Signed-off-by: Svyatoslav Ryhel
---
drivers/gpu/drm/panel/panel-simple.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
Add support for HannStar HSD101PWW2 display panel used by ASUS Transformer
TF201T tablet device.
Svyatoslav Ryhel (2):
dt-bindings: display: simple: Add HannStar HSD101PWW2
drm/panel: simple: Add support for HannStar HSD101PWW2 panel
.../bindings/display/panel/panel-simple.yaml | 2 ++
dri
From: Svyatoslav Ryhel
Add HannStar HSD101PWW2 10.1" WXGA (1280x800) TFT-LCD LVDS panel
to the list of compatibles.
Signed-off-by: Svyatoslav Ryhel
---
.../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree
From: Anton Bambura
LQ101R1SX03 is compatible with LQ101R1SX01, document it.
Signed-off-by: Anton Bambura
---
.../devicetree/bindings/display/panel/sharp,lq101r1sx01.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/display/panel/sh
Add support for Sharp LQ101R1SX03 display panel used by ASUS Transformer
TF701T tablet device.
Anton Bambura (2):
dt-bindings: sharp,lq101r1sx01: Add compatible for LQ101R1SX03
drm/panel: sharp: lq101r1sx01: Support LQ101R1SX03
.../devicetree/bindings/display/panel/sharp,lq101r1sx01.yaml |
From: Anton Bambura
LQ101R1SX03 is compatible with LQ101R1SX01, add compatible to the driver.
Signed-off-by: Anton Bambura
---
drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c
b/drivers/gpu/drm/
https://bugzilla.kernel.org/show_bug.cgi?id=214921
spassw...@web.de changed:
What|Removed |Added
Kernel Version|5.15, 5.15.1|5.15, 5.15.1,
|
On Sat, 13 Nov 2021 at 06:16, Linus Torvalds
wrote:
>
> On Thu, Nov 11, 2021 at 7:25 PM Dave Airlie wrote:
> >
> > I missed a drm-misc-next pull for the main pull last week. It wasn't
> > that major and isn't the bulk of this at all. This has a bunch of
> > fixes all over, a lot for amdgpu and i9
On Sun, Nov 14, 2021 at 1:00 PM Dave Airlie wrote:
>
> i915 will no longer be x86-64 only in theory, since Intel now produces
> PCIe graphics cards using the same hw designs.
Well, at least in my tree, it still has the "depends on X86", along
with several other x86-only things (like "select INTEL
Yunfei,
On Thu, 11 Nov 2021 at 01:15, Yunfei Dong wrote:
>
> Adds decoder dt-bindings for mt8192.
>
> Signed-off-by: Yunfei Dong
> ---
> .../media/mediatek,vcodec-subdev-decoder.yaml | 261 ++
> 1 file changed, 261 insertions(+)
> create mode 100644
> Documentation/devicetree/
Hi Yunfei,
On Thu, 11 Nov 2021 at 01:15, Yunfei Dong wrote:
>
> This series adds support for multi hardware decode into mtk-vcodec, by first
> adding use
> of_platform_populate to manage each hardware information: interrupt, clock,
> register
> bases and power. Secondly add core work queue to d
https://bugzilla.kernel.org/show_bug.cgi?id=215025
Bug ID: 215025
Summary: [amdgpu] Thinkpad A275 hangs on shutdown / screen does
not turn on after reboot
Product: Drivers
Version: 2.5
Kernel Version: 5.15.2
Hardware: A
https://bugzilla.kernel.org/show_bug.cgi?id=215025
--- Comment #1 from Bjoern Franke (b...@nord-west.org) ---
BTW, iommu is enabled:
[0.739887] perf/amd_iommu: Detected AMD IOMMU #0 (2 banks, 4
counters/bank).
--
You may reply to this email to add a comment.
You are receiving this mail beca
https://bugzilla.kernel.org/show_bug.cgi?id=215025
--- Comment #2 from Bjoern Franke (b...@nord-west.org) ---
Tested 5.14.16 - ok
Tried 5.15.0 and 5.15.1 -> don't even boot, the first 3 lines look misarranged.
I will try to bisect between 5.14.16 and 5.15.2.
--
You may reply to this email to ad
https://bugzilla.kernel.org/show_bug.cgi?id=211277
--- Comment #73 from kolAflash (kolafl...@kolahilft.de) ---
(In reply to Jerome C from comment #72)
> Hi James,
>
> I noticed the patch that you asked us to try from comment 52 were also
> submitted to kernel 5.14.7
>
> tested it, all is good fo
In function amdgpu_get_xgmi_hive, when kobject_init_and_add failed
There is a potential memleak if not call kobject_put.
Signed-off-by: Bernard Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/driver
Convert function-like macro comments to kernel-doc notation and
fix other kernel-doc warnings:
drivers/video/backlight/ili922x.c:85: warning: This comment starts with '/**',
but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* START_BYTE(id, rs, rw)
drivers/video/bac
In function xen_drm_front_gem_import_sg_table, if in error branch,
there maybe potential memleak if not call gem_free_pages_array.
Signed-off-by: Bernard Zhao
---
drivers/gpu/drm/xen/xen_drm_front_gem.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/x
Fix fallthrough warnings in sh776fb.c:
../drivers/video/fbdev/sh7760fb.c: In function 'sh7760fb_get_color_info':
../drivers/video/fbdev/sh7760fb.c:138:23: warning: this statement may fall
through [-Wimplicit-fallthrough=]
138 | lgray = 1;
../drivers/video/fbdev/sh7760fb.c:143:23
On Sun, Nov 14, 2021 at 10:32:57PM -0800, Randy Dunlap wrote:
> Fix fallthrough warnings in sh776fb.c:
>
> ../drivers/video/fbdev/sh7760fb.c: In function 'sh7760fb_get_color_info':
> ../drivers/video/fbdev/sh7760fb.c:138:23: warning: this statement may fall
> through [-Wimplicit-fallthrough=]
>
This change is to cleanup the code style a bit.
Signed-off-by: Bernard Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 04cf9
This change is to remove useless break after return.
Signed-off-by: Bernard Zhao
---
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index b200b9e722d9..8318ee8339f1 100644
On 11/14/21 22:19, Linus Torvalds wrote:
On Sun, Nov 14, 2021 at 1:00 PM Dave Airlie wrote:
i915 will no longer be x86-64 only in theory, since Intel now produces
PCIe graphics cards using the same hw designs.
Well, at least in my tree, it still has the "depends on X86", along
with several o
This change is to cleanup the code a bit.
Signed-off-by: Bernard Zhao
---
drivers/gpu/drm/exynos/exynos_drm_fimc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
index ecfd82d0afb7..023f
Am 12.11.21 um 17:10 schrieb Michel Dänzer:
On 2021-11-12 16:03, Christian König wrote:
Am 12.11.21 um 15:30 schrieb Michel Dänzer:
On 2021-11-12 15:29, Michel Dänzer wrote:
On 2021-11-12 13:47, Christian König wrote:
Anyway this unfortunately turned out to be work for Harray and Nicholas. In
On Sun, 2021-11-14 at 23:14 -0800, Bernard Zhao wrote:
> This change is to remove useless break after return.
[]
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
[]
> @@ -2092,22 +2092,18 @@ static int dce_v8_0_pick_dig_encoder(struct
> drm_encoder *e
Hello,
I'm getting some fence refcounting related panics with the current
Linus's master branch:
It happens immediately whenever I start Xorg or sway.
Anyone has any ideas where to start looking? It works fine with v5.15.
(sorry for the interleaved log, it's coming from multiple CPUs at once
I
Hello,
the backlight control no longer works on my ASUS UM325 (Ryzen 5700U)
OLED laptop. I have bisected the breakage to commit 7fd13baeb7a3a48.
commit 7fd13baeb7a3a48cae12c36c52f06bf4e9e7d728 (HEAD, refs/bisect/bad)
Author: Alex Deucher
Date: Thu Jul 8 16:31:10 2021 -0400
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