The load tracker was initially designed to report and warn about a load
too high for the HVS. To do so, it computes for each plane the impact
it's going to have on the HVS, and will warn (if it's enabled) if we go
over what the hardware can process.
While the limits being used are a bit irrelevant
It turns out the encoder retrieval code, in addition to being
unnecessarily complicated, has a bug when only the planes and crtcs are
affected by a given atomic commit.
Indeed, in such a case, either drm_atomic_get_old_connector_state or
drm_atomic_get_new_connector_state will return NULL and thus
The encoder retrieval code has been a source of bugs and glitches in the
past and the crtc <-> encoder association been wrong in a number of
different ways.
Add some logging to quickly spot issues if they occur.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 6 ++
1 file
Depending on a given HVS output (HVS to PixelValves) and input (planes
attached to a channel) load, the HVS needs for the core clock to be
raised above its boot time default.
Failing to do so will result in a vblank timeout and a stalled display
pipeline.
Signed-off-by: Maxime Ripard
---
driver
If we have a state already and disconnect/reconnect the display, the
SCDC messages won't be sent again since we didn't go through a disable /
enable cycle.
In order to fix this, let's call the vc4_hdmi_enable_scrambling function
in the detect callback if there is a mode and it needs the scrambler
Now that we have the infrastructure in place, we can raise the maximum
pixel rate we can reach for HDMI0 on the BCM2711.
HDMI1 is left untouched since its pixelvalve has a smaller FIFO and
would need a clock faster than what we can provide to support the same
modes.
Acked-by: Thomas Zimmermann
R
On 25/10/2021 12:32, Wan Jiabing wrote:
Fix following coccicheck warning:
./drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:3117:15-22: WARNING:
ERR_CAST can be used with eb->requests[i].
Signed-off-by: Wan Jiabing
Pushed to drm-intel-gt-next. Thanks.
---
drivers/gpu/drm/i915/gem/i915_gem_
On Mon, Oct 25, 2021 at 3:28 AM Christian König
wrote:
>
> "i" can be used uninitialized in one of the error branches. Fix this.
>
> Signed-off-by: Christian König
> Reported-by: kernel test robot
Acked-by: Alex Deucher
> ---
> drivers/dma-buf/st-dma-resv.c | 3 ++-
> 1 file changed, 2 inser
On 25-10-21, 17:40, Dmitry Baryshkov wrote:
> On 20/10/2021 09:57, Vinod Koul wrote:
> > On 14-10-21, 16:50, Dmitry Baryshkov wrote:
> > > On 14/10/2021 16:41, Dmitry Baryshkov wrote:
> > > > On 07/10/2021 10:08, Vinod Koul wrote:
> > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
>
On 25-10-21, 17:37, Dmitry Baryshkov wrote:
> On 14/10/2021 17:13, Dmitry Baryshkov wrote:
> > On 07/10/2021 10:08, Vinod Koul wrote:
> > > @@ -572,8 +574,22 @@ static struct msm_display_topology
> > > dpu_encoder_get_topology(
> > > topology.num_enc = 0;
> > > topology.num_intf = intf
From: Chun-Kuang Hu
CMDQ is used to update display register in vblank period, so
it should be execute in next vblank. If it fail to execute
in next 2 vblank, tiemout happen.
Signed-off-by: Chun-Kuang Hu
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 17 +
hi
The driver is not able to find the vbios image which is required for
the driver to properly enumerate the hardware. I would guess it's a
platform issue. Is there a newer sbios image available for your
platform?
...
I would start with an sbios update is possible.
not that i'm aware.
thi
Hide the guc_id and tail fields, for request trace points, behind
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option. Trace points
are ABI (maybe?) so don't change them without kernel developers Kconfig
options.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/i915_trace.h | 27 ++
From: Yongqiang Niu
In cmdq mode, packet may be flushed before it is executed, so
the pending flag should be cleared after cmdq packet is done.
Signed-off-by: Yongqiang Niu
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 51 ++---
1 file changed,
Hi Maxime,
On Mon, Oct 25, 2021 at 05:16:36PM +0200, Maxime Ripard wrote:
> Hi Sam,
>
> On Thu, Oct 21, 2021 at 05:22:55PM +0200, Sam Ravnborg wrote:
> > Hi Maxime,
> >
> > > Let me know what you think,
> >
> > apply the lot to drm-misc-next. Maybe wait for an r-b or a-b on the kirin
> > patch
From: Chun-Kuang Hu
rx_callback is a standard mailbox callback mechanism and could cover the
function of proprietary cmdq_task_cb, so use the standard one instead of
the proprietary one.
Signed-off-by: Chun-Kuang Hu
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 16
On 10/25/2021 02:37, Joonas Lahtinen wrote:
Quoting Matthew Brost (2021-10-22 19:42:19)
On Fri, Oct 22, 2021 at 12:35:04PM +0300, Joonas Lahtinen wrote:
Hi Matt & John,
Can you please queue patches with the right Fixes: references to convert
all the GuC tracepoints to be protected by the LOW_L
From: Chun-Kuang Hu
In mailbox rx_callback, it pass struct mbox_client to callback
function, but it could not map back to mtk_drm_crtc instance
because struct cmdq_client use a pointer to struct mbox_client:
struct cmdq_client {
struct mbox_client client;
struct mbox_chan *chan;
On Mon, Oct 25, 2021 at 03:23:00PM +0300, Joonas Lahtinen wrote:
> Quoting Thomas Hellström (2021-10-21 08:39:48)
> > On Wed, 2021-10-20 at 12:21 -0700, Matthew Brost wrote:
>
>
>
> > > Fixes: 1a52faed31311 ("drm/i915/guc: Take engine PM when a context is
> > > pinned with GuC submission")
> > >
These refinements include using standard mailbox callback interface,
timeout detection, and a fixed cmdq_handle.
Change in v3:
1. Revert "drm/mediatek: clear pending flag when cmdq packet is done"
and add it after the CMDQ refinement pathes.
2. Change the remove of struct cmdq_client to remove
On 10/23/2021 11:36, Thomas Hellström wrote:
On 10/23/21 20:18, Matthew Brost wrote:
On Sat, Oct 23, 2021 at 07:46:48PM +0200, Thomas Hellström wrote:
On 10/22/21 20:09, John Harrison wrote:
And to be clear, the engine reset is not supposed to fail. Whether
issued by GuC or i915, the GDRST reg
When DRM_CHIPONE_ICN6211 is selected, and DRM_KMS_HELPER is not selected,
Kbuild gives the following warning:
WARNING: unmet direct dependencies detected for DRM_PANEL_BRIDGE
Depends on [n]: HAS_IOMEM [=y] && DRM_BRIDGE [=y] && DRM_KMS_HELPER [=n]
Selected by [y]:
- DRM_CHIPONE_ICN6211 [=y]
Hi Julian,
Thank you for the patch.
On Mon, Oct 25, 2021 at 01:42:02PM -0400, Julian Braha wrote:
> When DRM_CHIPONE_ICN6211 is selected, and DRM_KMS_HELPER is not selected,
> Kbuild gives the following warning:
>
> WARNING: unmet direct dependencies detected for DRM_PANEL_BRIDGE
> Depends on
sbios settings
any of these raise a suspicion?
screenshot from the ASRockRack X470D4U's BIOS setup:
https://imgur.com/a/rdhGQNy
Hi
Am 25.10.21 um 14:13 schrieb Naresh Kamboju:
Regression found on arm gcc-11 built with multi_v5_defconfig
Following build warnings / errors reported on linux next 20211025.
metadata:
git_describe: next-20211025
git_repo: https://gitlab.com/Linaro/lkft/mirrors/next/linux-next
On 25/10/2021 19:10, Vinod Koul wrote:
On 25-10-21, 17:40, Dmitry Baryshkov wrote:
On 20/10/2021 09:57, Vinod Koul wrote:
On 14-10-21, 16:50, Dmitry Baryshkov wrote:
On 14/10/2021 16:41, Dmitry Baryshkov wrote:
On 07/10/2021 10:08, Vinod Koul wrote:
diff --git a/drivers/gpu/drm/msm/disp/dp
On 10/23/2021 9:00 AM, Rob Clark wrote:
From: Rob Clark
We know the upper bound on # of mixers (ie. two), so lets just allocate
this on the stack.
Fixes:
BUG: sleeping function called from invalid context at
include/linux/sched/mm.h:201
in_atomic(): 1, irqs_disabled(): 128, non_block
On Monday, October 25, 2021 1:47:35 PM EDT you wrote:
> Hi Julian,
>
> Thank you for the patch.
>
> On Mon, Oct 25, 2021 at 01:42:02PM -0400, Julian Braha wrote:
> > When DRM_CHIPONE_ICN6211 is selected, and DRM_KMS_HELPER is not selected,
> > Kbuild gives the following warning:
> >
> > WARNING:
Do a sanity check on pixclock value before using it as a divisor.
Syzkaller reported a divide error in cirrusfb_check_pixclock.
divide error: [#1] SMP KASAN PTI
CPU: 0 PID: 14938 Comm: cirrusfb_test Not tainted 5.15.0-rc6 #1
Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.11.0-
On Mon, Oct 25, 2021 at 02:01:30PM -0500, George Kennedy wrote:
> Do a sanity check on pixclock value before using it as a divisor.
>
> Syzkaller reported a divide error in cirrusfb_check_pixclock.
>
> divide error: [#1] SMP KASAN PTI
> CPU: 0 PID: 14938 Comm: cirrusfb_test Not tainted 5.15.
Adding back Daniel (somehow he got off the addresses list) and Chris who
worked a lot in this area.
On 2021-10-21 2:34 a.m., Christian König wrote:
Am 20.10.21 um 21:32 schrieb Andrey Grodzovsky:
On 2021-10-04 4:14 a.m., Christian König wrote:
The problem is a bit different.
The callback
On 10/25/2021 3:07 PM, Greg KH wrote:
On Mon, Oct 25, 2021 at 02:01:30PM -0500, George Kennedy wrote:
Do a sanity check on pixclock value before using it as a divisor.
Syzkaller reported a divide error in cirrusfb_check_pixclock.
divide error: [#1] SMP KASAN PTI
CPU: 0 PID: 14938 Comm:
The `drm_mode_config_init` was deprecated since c3b790e commit, and it's
being replaced by the `drmm_mode_config_init`.
Signed-off-by: Igor Torrente
---
V2: Change the code style(Thomas Zimmermann).
---
drivers/gpu/drm/vkms/vkms_drv.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
d
Currently, the memory to the composition frame is being allocated using
the kzmalloc. This comes with the limitation of maximum size of one
page size(which in the x86_64 is 4Kb and 4MB for default and hugepage
respectively).
Somes test of igt (e.g. kms_plane@pixel-format) uses more than 4MB when
t
The `map` vector at `vkms_composer` uses a hardcoded value to define its
size.
If someday the maximum number of planes increases, this hardcoded value
can be a problem.
This value is being replaced with the DRM_FORMAT_MAX_PLANES macro.
Signed-off-by: Igor Torrente
---
drivers/gpu/drm/vkms/vkms
This will be useful to write tests that depends on these formats.
ARGB format is already used as the universal format for internal uses.
Here we are just exposing it to the user space.
XRGB follows the a similar implementation of the former format.
Just overwriting the alpha channel.
Signed-off-
Adds this common format to vkms.
This commit also adds new helper macros to deal with fixed-point
arithmetic.
It was done to improve the precision of the conversion to ARGB16161616
since the "conversion ratio" is not an integer.
Signed-off-by: Igor Torrente
---
drivers/gpu/drm/vkms/vkms_compos
In general I'm all there to get this fixed, but there is one major
problem: Drivers don't expect the lock to be dropped.
What we could do is to change all drivers so they call always call the
dma_fence_signal functions and drop the _locked variants. This way we
could move calling the callback
Quoting Philip Chen (2021-10-21 14:05:59)
> Fit ps8640 driver into runtime power management framework:
>
> First, break _poweron() to 3 parts: (1) turn on power and wait for
> ps8640's internal MCU to finish init (2) check panel HPD (which is
> proxied by GPIO9) (3) the other configs. As runtime_re
Quoting Philip Chen (2021-10-21 14:06:00)
> diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c
> b/drivers/gpu/drm/bridge/parade-ps8640.c
> index 220ca3b03d24..f99a2e0808b7 100644
> --- a/drivers/gpu/drm/bridge/parade-ps8640.c
> +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
> @@ -149,6 +150,23 @@
Hi,
On 25.10.2021 13:21, Laurent Pinchart wrote:
Hello,
On Mon, Oct 25, 2021 at 01:00:10PM +0200, Andrzej Hajda wrote:
On 21.10.2021 22:21, Sam Ravnborg wrote:
On Thu, Oct 21, 2021 at 12:29:01PM -0700, Douglas Anderson wrote:
Right now, the chaining order of
pre_enable/enable/disable/post_di
On 10/25/2021 09:34, Matthew Brost wrote:
Hide the guc_id and tail fields, for request trace points, behind
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option. Trace points
are ABI (maybe?) so don't change them without kernel developers Kconfig
options.
The i915 sw arch team have previously har
On 2021-10-21 11:44, Stephen Boyd wrote:
Quoting Krishna Manikandan (2021-10-20 06:58:53)
From: Sankeerth Billakanti
Add edp controller and phy DT nodes for sc7280.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Krishna Manikandan
Some comments below
Reviewed-by: Stephen Boyd
Ch
Hi George,
On Mon, Oct 25, 2021 at 03:33:43PM -0400, George Kennedy wrote:
>
>
> On 10/25/2021 3:07 PM, Greg KH wrote:
> > On Mon, Oct 25, 2021 at 02:01:30PM -0500, George Kennedy wrote:
> > > Do a sanity check on pixclock value before using it as a divisor.
> > >
> > > Syzkaller reported a div
Hi Julian,
On Mon, Oct 25, 2021 at 02:51:47PM -0400, Julian Braha wrote:
> On Monday, October 25, 2021 1:47:35 PM EDT you wrote:
> > On Mon, Oct 25, 2021 at 01:42:02PM -0400, Julian Braha wrote:
> > > When DRM_CHIPONE_ICN6211 is selected, and DRM_KMS_HELPER is not selected,
> > > Kbuild gives the
Just resubmitting this patch series from AMD with _very_ minor changes
(just a typo and fixing a debug message) so that this can be pushed
upstream with a proper patchwork link. Will be pushing this into a topic
branch and submitting to airlied in a moment.
Bhawanpreet Lakha (3):
drm: Remove slo
From: Bhawanpreet Lakha
This code path is used during commit, and we dont expect things to fail
during the commit stage, so remove this.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Lyude Paul
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_dp_mst_topology.c | 6 +-
1 file changed, 1
From: Bhawanpreet Lakha
8b/10b encoding format requires to reserve the first slot for
recording metadata. Real data transmission starts from the second slot,
with a total of available 63 slots available.
In 128b/132b encoding format, metadata is transmitted separately
in LLCP packet before MTP.
From: Fangzhi Zuo
[Why]
configure/call DC interface for DP2 mst support. This is needed to make DP2
mst work.
[How]
- add encoding type, logging, mst update/reduce payload functions
Use the link encoding to determine the DP type (1.4 or 2.0) and add a
flag to dc_stream_update to determine wheth
From: Bhawanpreet Lakha
[Why]
Add DP2 MST and debugfs support
[How]
Update the slot info based on the link encoding format
Reviewed-by: "Lin, Wayne"
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Fangzhi Zuo
Signed-off-by: Lyude Paul
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29
Fix a division by zero in `vgacon_resize' with a backtrace like:
vgacon_resize
vc_do_resize
vgacon_init
do_bind_con_driver
do_unbind_con_driver
fbcon_fb_unbind
do_unregister_framebuffer
do_register_framebuffer
register_framebuffer
__drm_fb_helper_initial_config_and_unlock
drm_helper_hpd_irq_event
From: Bhawanpreet Lakha
This code path is used during commit, and we dont expect things to fail
during the commit stage, so remove this.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Lyude Paul
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_dp_mst_topology.c | 6 +-
1 file changed, 1
From: Bhawanpreet Lakha
8b/10b encoding format requires to reserve the first slot for
recording metadata. Real data transmission starts from the second slot,
with a total of available 63 slots available.
In 128b/132b encoding format, metadata is transmitted separately
in LLCP packet before MTP.
From: Fangzhi Zuo
[Why]
configure/call DC interface for DP2 mst support. This is needed to make DP2
mst work.
[How]
- add encoding type, logging, mst update/reduce payload functions
Use the link encoding to determine the DP type (1.4 or 2.0) and add a
flag to dc_stream_update to determine wheth
From: Bhawanpreet Lakha
[Why]
Add DP2 MST and debugfs support
[How]
Update the slot info based on the link encoding format
Reviewed-by: "Lin, Wayne"
Signed-off-by: Bhawanpreet Lakha
Signed-off-by: Fangzhi Zuo
Signed-off-by: Lyude Paul
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29
(Sorry for the noise, had to resend because I typo'd amd's mailing list
email address by accident)
Just resubmitting this patch series from AMD with _very_ minor changes
(just a typo and fixing a debug message) so that this can be pushed
upstream with a proper patchwork link. Will be pushing this
This series adds runtime PM support to Tegra drivers and enables core
voltage scaling for Tegra20/30 SoCs, resolving overheating troubles.
All patches in this series are interdependent and should go via Tegra tree
for simplicity.
Changelog:
v14: - Fixed missing runtime PM syncing on removal of d
GENPD core now can set up domain's performance state properly while device
is RPM-suspended. Runtime PM of a device must be enabled during setup
because GENPD checks whether device is suspended and check doesn't work
while RPM is disabled. Instead of replicating the boilerplate RPM-enable
code arou
The Clock-and-Reset controller resides in a core power domain on NVIDIA
Tegra SoCs. In order to support voltage scaling of the core power domain,
we hook up DVFS-capable clocks to the core GENPD for managing of the
GENPD's performance state based on the clock changes.
Some clocks don't have any s
Only couple drivers need to get the -ENODEV error code and majority of
drivers need to explicitly initialize the performance state. Add new
common helper which sets up OPP table for these drivers.
Signed-off-by: Dmitry Osipenko
---
include/soc/tegra/common.h | 15 +++
1 file changed,
Document new DVFS OPP table and power domain properties of the Host1x bus
and devices sitting on the bus.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../display/tegra/nvidia,tegra20-host1x.txt | 49 +++
1 file changed, 49 insertions(+)
diff --git
a/Documenta
The Tegra USB controller belongs to the core power domain and we're going
to enable GENPD support for the core domain. Now USB controller must be
resumed using runtime PM API in order to initialize the USB power state.
We already support runtime PM for the CI device, but CI's PM is separated
from t
The HDMI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now HDMI driver must use
OPP API for driving the controller's clock rate because OPP API takes
care of reconfiguring the domain's performance state based on HDMI clock
rate. Add OPP suppo
CDMA must be stopped before hardware is suspended. Add channel stopping
to RPM suspend callback. Add system level suspend-resume callbacks.
Runtime PM initialization is moved to host1x client init phase because
RPM callback now uses host1x channel that is available only when host1x
client is regis
Add host1x_channel_stop() which waits till channel becomes idle and then
stops the channel hardware. This is needed for supporting suspend/resume
by host1x drivers since the hardware state is lost after power-gating,
thus the channel needs to be stopped before client enters into suspend.
Tested-by
Runtime PM auto-suspension doesn't work without pm_runtime_mark_last_busy(),
add it.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/submit.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/tegra/submit.c b/drivers/gpu/drm/tegra/submit.c
index 3bbd8de5711c..6d6dd8c35
Document sub-nodes which describe Tegra SoC clocks that require a higher
voltage of the core power domain in order to operate properly on a higher
clock rates. Each node contains a phandle to OPP table and power domain.
The root PLLs and system clocks don't have any specific device dedicated
to t
Runtime PM is now universally available, make it mandatory by removing
the pm_runtime_enabled() checks.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/submit.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/tegra/submit.c b/drivers/gpu
Add runtime power management and support generic power domains.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr2d.c | 184 +++
Memory Client should be blocked before hardware reset is asserted in order
to prevent memory corruption and hanging of memory controller.
Document Memory Client resets of Host1x, GR2D and GR3D hardware units.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../bindings/display/tegr
The NAND on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now NAND must be resumed using
runtime PM API in order to initialize the NAND power state. Add runtime PM
and OPP support to the NAND driver.
Acked-by: Miquel Raynal
Signed-off-by: Dmit
Previously we assumed that devm_tegra_core_dev_init_opp_table() will
be used only by drivers that will always have device with OPP table,
but this is not true anymore. For example now Tegra30 will have OPP table
for PWM, but Tegra20 not and both use the same driver. Hence let's not
print the error
The GMI bus on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now GMI must be resumed using
runtime PM API in order to initialize the GMI power state. Add runtime PM
and OPP support to the GMI driver.
Signed-off-by: Dmitry Osipenko
---
drivers
The SDHCI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now SDHCI must be resumed using
runtime PM API in order to initialize the SDHCI power state. The SDHCI
clock rate must be changed using OPP API that will reconfigure the power
domain per
Add runtime PM and OPP support to the Host1x driver. For the starter we
will keep host1x always-on because dynamic power management require a major
refactoring of the driver code since lot's of code paths are missing the
RPM handling and we're going to remove some of these paths in the future.
Tes
The PWM on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now PWM must be resumed using
runtime PM API in order to initialize the PWM power state. The PWM clock
rate must be changed using OPP API that will reconfigure the power domain
performance
Add runtime power management and support generic power domains.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr3d.c | 363 +++
CDMA must be stopped before hardware is suspended. Add channel stopping
to RPM suspend callback. Add system level suspend-resume callbacks.
Runtime PM initialization is moved to host1x client init phase because
RPM callback now uses host1x channel that is available only when host1x
client is regis
Document new OPP table and power domain properties of the video decoder
hardware.
Reviewed-by: Rob Herring
Acked-by: Hans Verkuil
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/media/nvidia,tegra-vde.yaml | 12
1 file changed, 12 insertions(+)
diff --git a/Documentat
Device-tree schema doesn't allow domain name to start with a number.
We don't use 3d domain yet in device-trees, so rename it to the name
used by Tegra TRMs: TD, TD2.
Reported-by: David Heidelberg
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 8
1 file changed, 4 inserti
Convert NVIDIA Tegra video decoder binding to schema.
Reviewed-by: Rob Herring
Acked-by: Hans Verkuil
Signed-off-by: Dmitry Osipenko
---
.../bindings/media/nvidia,tegra-vde.txt | 64 ---
.../bindings/media/nvidia,tegra-vde.yaml | 107 ++
2 files changed, 107
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on pre-Tegra186
SoCs.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar #
Depending on hardware version, Tegra SoC may require a higher voltages
during resume from system suspend, otherwise hardware will crash. Set
SoC voltages to a nominal levels during suspend.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/regulators-tegra20.c | 99
driv
Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20
Signed-off-by:
Currently driver supports legacy power domain API, this patch adds generic
power domain support. This allows us to utilize a modern GENPD API for
newer device-trees.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-b
All device drivers got runtime PM and OPP support. Flip the core domain
support status for Tegra20 and Tegra30 SoCs.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra20 SoC.
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20
Signed-off-by: Dmitry Osipenko
---
.../boot/dts/tegra20-acer-a500-picasso.dts| 1 +
arch/arm/boot/dts/tegra
Use resource-managed helpers to make code cleaner and more correct,
properly releasing all resources in case of driver probe error.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/fuse/fuse-tegra.c | 32 ++
drivers/soc/tegra/fuse/fuse-tegra20.c | 33 +++
CORE power domain uses name of device-tree node, which is inconsistent with
the names of PMC domains. Set the name to "core" to make it consistent.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/tegra/pmc
Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Peter Geis # Ouya T30
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry O
Extend memory OPPs with 500MHz entry. This clock rate is used by ASUS
Transformer tablets.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30-peripherals-opp.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
b/a
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra30 SoC.
Tested-by: Peter Geis # Ouya T30
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-trimslice.dts |2 +-
.../tegra30-asus-nexus7-group
MPE, VI, EPP and ISP were never used and we don't have drivers for them.
Since these modules are enabled by default in a device-tree, a device is
created for them, blocking voltage scaling because there is no driver to
bind, and thus, state of PMC driver is never synced. Disable them.
Signed-off-b
The SPI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now SPI driver must use OPP
API for driving the controller's clock rate because OPP API takes care
of reconfiguring the domain's performance state in accordance to the
rate. Add OPP suppor
OPP table name now should start with "opp-table" and OPP entries
shouldn't contain commas and @ signs in accordance to the new schema
requirement. Reorganize CPU and EMC OPP table device-tree nodes.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra124-apalis-emc.dtsi| 4 +-
.../ar
The FUSE controller is enabled at a boot time. Reset it in order to put
hardware and clock into clean and disabled state.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/fuse/fuse-tegra.c | 25 +
drivers/soc/tegra/fuse/fuse.h | 1 +
2 files changed, 26 inserti
Hi Christian,
On Mon, Oct 25, 2021 at 09:28:35AM +0200, Christian König wrote:
> "i" can be used uninitialized in one of the error branches. Fix this.
>
> Signed-off-by: Christian König
> Reported-by: kernel test robot
> ---
> drivers/dma-buf/st-dma-resv.c | 3 ++-
> 1 file changed, 2 insertio
Hi, Nancy:
Nancy.Lin 於 2021年10月4日 週一 下午2:21寫道：
>
> Add ovl_adaptor driver for MT8195.
> Ovl_adaptor is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> l
This series is from discussion we had on reordering the device lists for
drm shutdown paths[1]. I've introduced an 'aggregate' bus that we put
the aggregate device onto and then we probe the aggregate device once
all the components are probed and call component_add(). The probe/remove
hooks are whe
Replace 'struct master' with 'struct aggregate_device' and then rename
'master' to 'adev' everywhere in the code. While we're here, put a
struct device inside the aggregate device so that we can register it
with a bus_type in the next patch.
The diff is large but that's because this is mostly a re
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