Hi Thomas,
On Fri, Oct 22, 2021 at 03:28:20PM +0200, Thomas Zimmermann wrote:
> Enable FB_DAMAGE_CLIPS with simpledrm for improved performance and/or
> less overhead. With this in place, add support for virtual screens
> (i.e., framebuffers that are larger than the display resolution). This
> also
Hi Thomas,
On Fri, Oct 22, 2021 at 03:28:21PM +0200, Thomas Zimmermann wrote:
> Provide a function that computes the offset into a blit destination
> buffer. This will allow to move destination-buffer clipping into the
> format-helper callers.
>
> Signed-off-by: Thomas Zimmermann
> ---
> driver
Hi Jani,
On Mon, Oct 18, 2021 at 01:00:01PM +0300, Jani Nikula wrote:
> On Sat, 16 Oct 2021, Len Baker wrote:
> > Hi Daniel and Jani,
> >
> > On Wed, Oct 13, 2021 at 01:51:30PM +0200, Daniel Vetter wrote:
> >> On Wed, Oct 13, 2021 at 02:24:05PM +0300, Jani Nikula wrote:
> >> > On Mon, 11 Oct 2021
Hi,
On 10/23/21 4:14 AM, Flora Fu wrote:
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index d9bac2710494..074b0cf24c44 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -24,6 +24,24 @@ config MTK_APU_PM
APU power domain shall be
On Fri, Oct 22, 2021 at 12:15 PM Jessica Zhang wrote:
>
> On 10/22/2021 10:20 AM, Rob Clark wrote:
> > From: Rob Clark
> >
> > We know the upper bound on # of mixers (ie. two), so lets just allocate
> > this on the stack.
> >
> > Fixes:
> >
> > BUG: sleeping function called from invalid conte
From: Rob Clark
Signed-off-by: Rob Clark
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index e91568d4f09a..0ae397044310 100644
From: Rob Clark
We know the upper bound on # of mixers (ie. two), so lets just allocate
this on the stack.
Fixes:
BUG: sleeping function called from invalid context at
include/linux/sched/mm.h:201
in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/0
INFO: lockde
Remove the error message when gce clk is defer.
Signed-off-by: jason-jh.lin
---
drivers/mailbox/mtk-cmdq-mailbox.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
b/drivers/mailbox/mtk-cmdq-mailbox.c
index fd5576a9f8b4..684b8aa1e445 1
Add new document for APU power controller.
Signed-off-by: Flora Fu
---
.../soc/mediatek/mediatek,apu-pwr.yaml| 88 +++
1 file changed, 88 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pwr.yaml
diff --git
a/Documentation/d
Remove legacy PWM interface (pwm_config, pwm_enable, pwm_disable) and
replace it for the atomic PWM API.
Signed-off-by: Maíra Canal
---
drivers/video/backlight/lp855x_bl.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/video/backlight/lp855x_bl.c
Add apu power node.
Signed-off-by: Flora Fu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 62
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d5e417a512a7..c505c6926839 100644
---
From: Yong Wu
Add APU-IOMMI nodes
Signed-off-by: Yong Wu
Signed-off-by: Flora Fu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 7014082637b0..d
Add command for APU SMC call.
The tinyys start and stop sequence will porcess in ATF.
Signed-off-by: Flora Fu
---
include/linux/soc/mediatek/mtk_sip_svc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h
b/include/linux/soc/mediatek/mtk_sip_svc.h
in
Add node for APU tinysys.
Signed-off-by: Flora Fu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index c505c6926839..8108084a3f6f 10064
APU middleware is responsible to receive all user's requests
and control command and device related flow.
In Kernel side, the middleware use the IPI to send command
to remote tinysys to dispatch commands to AI engines in APU.
Signed-off-by: JB Tsai
Signed-off-by: Flora Fu
---
drivers/soc/mediat
Add new document for APU tinysys.
Signed-off-by: Flora Fu
---
.../soc/mediatek/mediatek,apu-rv.yaml | 140 ++
1 file changed, 140 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-rv.yaml
diff --git
a/Documentation/devicetree
Add Support for MediaTek MT8192 APU.
The MediaTek AI Processing Unit (APU) is a proprietary hardware
in the SoC to support AI functions.
The patches support the MT8192 APU running on internal microprocess.
Software packages contins power control, tinysys controller and middleware.
This series is
APU power driver support for subsys clock and
regulator controller. It has device link to iommu-apu
and apusys-rv tinysys driver to ensure the power state is
ready for hardware in sub modules.
Signed-off-by: Flora Fu
---
drivers/soc/mediatek/apusys/Makefile | 4 +
drivers/soc/mediatek/apu
Add regulator for mt8192 evb board.
Signed-off-by: Flora Fu
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 5d9e108e41f5..431008466d77 100644
Add driver for control APU tinysys
APU integrated subsystem having MD32RV33 (MD32) that runs tinysys
The tinsys is running on a micro processor in APU.
Its firmware is load and boot from Kernel side. Kernel and tinysys use
IPI to tx/rx messages.
Signed-off-by: Flora Fu
---
drivers/soc/mediatek/
Add apu core driver.
The core driver will init the reset part of apu functions.
Signed-off-by: Flora Fu
---
drivers/soc/mediatek/Kconfig | 18 +
drivers/soc/mediatek/apusys/Makefile | 3 +
drivers/soc/mediatek/apusys/apu-core.c | 91 ++
drivers/soc/mediat
APU IOMMU is a new iommu HW. it use a new pagetable.
Add support for mt8192 apu iommu.
Signed-off-by: Yong Wu
Signed-off-by: Flora Fu
---
drivers/iommu/mtk_iommu.c | 57 +++
include/dt-bindings/memory/mt8192-larb-port.h | 4 ++
2 files changed, 61 insertions
Add mt8192 apu iommu bindings.
Signed-off-by: Flora Fu
---
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
On 10/22/21 20:09, John Harrison wrote:
And to be clear, the engine reset is not supposed to fail. Whether
issued by GuC or i915, the GDRST register is supposed to self clear
according to the bspec. If we are being sent the G2H notification for
an engine reset failure then the assumption is t
An error capture allocates memory, memory allocations depend on resets,
and resets need to flush the G2H handlers to seal several races. If the
error capture is done from the G2H handler this creates a circular
dependency. To work around this, do a error capture in a work queue
asynchronously from
Rather allocating an error capture in nowait context to break a lockdep
splat [1], do the error capture async compared to the G2H processing.
v2: Fix Docs warning
v3: Rebase, resend for CI
v4: Resend for CI
v5: Fix CI splat:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21428/fi-rkl-guc/igt@
It isn't safe to scrub for missing G2H or continue with the reset until
all G2H processing is complete. Flush the G2H work queue during reset to
ensure it is done running. No need to call the IRQ handler directly
either as the scrubbing code can deal with any missing G2H.
Signed-off-by: Matthew Br
From: John Harrison
When i915 receives a context reset notification from GuC, it triggers
an error capture before resetting any outstanding requsts of that
context. Unfortunately, the error capture is not a time bound
operation. In certain situations it can take a long time, particularly
when mul
On Sat, Oct 23, 2021 at 07:46:48PM +0200, Thomas Hellström wrote:
>
> On 10/22/21 20:09, John Harrison wrote:
> > And to be clear, the engine reset is not supposed to fail. Whether
> > issued by GuC or i915, the GDRST register is supposed to self clear
> > according to the bspec. If we are being s
On 10/23/21 20:18, Matthew Brost wrote:
On Sat, Oct 23, 2021 at 07:46:48PM +0200, Thomas Hellström wrote:
On 10/22/21 20:09, John Harrison wrote:
And to be clear, the engine reset is not supposed to fail. Whether
issued by GuC or i915, the GDRST register is supposed to self clear
according to
> On Oct 21, 2021, at 11:30 AM, Kim Phillips wrote:
>
> This reverts commit aae74ff9caa8de9a45ae2e46068c417817392a26,
> since it prevents my AMD Milan system from booting, with:
>
> [ 27.189558] BUG: kernel NULL pointer dereference, address:
> [ 27.197506] #PF: supervisor
https://bugzilla.kernel.org/show_bug.cgi?id=211807
Matt Berry (matthew.william.be...@gmail.com) changed:
What|Removed |Added
CC||matthew.wil
On 10/17/21 7:40 PM, Sam Ravnborg wrote:
Hi Marek,
Hi,
On Sun, Oct 17, 2021 at 07:29:51PM +0200, Marek Vasut wrote:
On 10/17/21 6:49 PM, Sam Ravnborg wrote:
[...]
+ /*
+* Encoder might sample data on different clock edge than the display,
+* for example OnSemi FIN338
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