Heureka, that's finally not used any more.
Signed-off-by: Christian König
---
include/linux/dma-resv.h | 26 --
1 file changed, 26 deletions(-)
diff --git a/include/linux/dma-resv.h b/include/linux/dma-resv.h
index 6761512ba662..3e6ffba0af70 100644
--- a/include/linux/dm
Instead of hand rolling the logic.
Signed-off-by: Christian König
---
drivers/gpu/drm/etnaviv/etnaviv_gem.c | 27 +--
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c
b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
index 8f1b5a
We certainly hold the reservation lock here, no need for the RCU dance.
Signed-off-by: Christian König
---
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
b/drivers/gpu/drm/etnaviv/etna
On 9/16/21 4:43 AM, Jani Nikula wrote:
On Thu, 16 Sep 2021, Tvrtko Ursulin wrote:
On 15/09/2021 20:23, Tim Gardner wrote:
In capture_vma() Coverity complains of a possible buffer overrun. Even
though this is a static function where all call sites can be checked,
limiting the copy length cou
Hi Abhinav,
On Wed, Sep 15, 2021 at 11:22 PM wrote:
> Are you not using DPU or are you not using mdp4/mdp5 as well? Even if
> you are using any of mdps, kms should
> not be NULL. Hence wanted to check the test case.
I am running i.MX53, which is an NXP SoC, not Qualcomm's.
It does not use DPU,
Christoph Hellwig writes:
> On Wed, Sep 15, 2021 at 07:18:34PM +0200, Christophe Leroy wrote:
>> Could you please provide more explicit explanation why inlining such an
>> helper is considered as bad practice and messy ?
>
> Because now we get architectures to all subly differ. Look at the mess
>
Hi Dave, Daniel,
please pull those etnaviv changes as fixes for the 5.15 release
series.
Fixes a very annoying issue where the driver view of the MMU state gets
out of sync with the actual hardware state across a runtime PM cycle,
so we end up restarting the GPU with the wrong (potentially alrea
On Thu, Sep 16, 2021 at 10:50 AM Christian König
wrote:
> Am 14.09.21 um 19:04 schrieb Daniel Vetter:
> > On Fri, Sep 10, 2021 at 10:26:42AM +0200, Christian König wrote:
> >> Abstract the complexity of iterating over all the fences
> >> in a dma_resv object.
> >>
> >> The new loop handles the wh
On Thu, Sep 16, 2021 at 01:30:17PM +0200, Christian König wrote:
> Abstract the complexity of iterating over all the fences
> in a dma_resv object.
>
> The new loop handles the whole RCU and retry dance and
> returns only fences where we can be sure we grabbed the
> right one.
>
> v2: fix accessi
https://bugzilla.kernel.org/show_bug.cgi?id=214431
Bug ID: 214431
Summary: [AMDGPU] Graphic lockups and various ECC errors on
Radeon VII
Product: Drivers
Version: 2.5
Kernel Version: 5.14.0
Hardware: x86-64
https://bugzilla.kernel.org/show_bug.cgi?id=214431
--- Comment #1 from Anthony Rabbito (ted...@gmail.com) ---
Created attachment 298839
--> https://bugzilla.kernel.org/attachment.cgi?id=298839&action=edit
AMDGPU lockup when waking up from monitor sleep
--
You may reply to this email to add a c
https://bugzilla.kernel.org/show_bug.cgi?id=214431
Anthony Rabbito (ted...@gmail.com) changed:
What|Removed |Added
Severity|high|normal
--
You may r
On Wed, Aug 18, 2021 at 06:56:41PM +0100, Melissa Wen wrote:
> Add support to attach generic extensions on job submission.
> This patch is a second prep work to enable multiple syncobjs on job
> submission. With this work, when the job submission interface needs
> to be extended to accomodate a new
On Wed, 15 Sep 2021 16:38:31 -0400, Sean Paul wrote:
> From: Sean Paul
>
> This patch adds the bindings for the MSM DisplayPort HDCP registers
> which are required to write the HDCP key into the display controller as
> well as the registers to enable HDCP authentication/key
> exchange/encryption.
On Wed, Sep 15, 2021 at 12:05:30PM +0200, Christian König wrote:
> Am 14.09.21 um 15:50 schrieb Daniel Vetter:
> > On Thu, Sep 09, 2021 at 09:10:39AM +0200, Christian König wrote:
> > > Am 08.09.21 um 20:27 schrieb Daniel Vetter:
> > > > On Tue, Sep 07, 2021 at 11:28:23AM +0200, Christian König wro
In capture_vma() Coverity complains of a possible buffer overrun. Even
though this is a static function where all call sites can be checked,
limiting the copy length could save some future grief.
CID 93300 (#1 of 1): Copy into fixed size buffer (STRING_OVERFLOW)
4. fixed_size_dest: You might overr
On Wed, Sep 15, 2021 at 10:45:36AM +0300, Oded Gabbay wrote:
> On Tue, Sep 14, 2021 at 7:12 PM Jason Gunthorpe wrote:
> >
> > On Tue, Sep 14, 2021 at 04:18:31PM +0200, Daniel Vetter wrote:
> > > On Sun, Sep 12, 2021 at 07:53:07PM +0300, Oded Gabbay wrote:
> > > > Hi,
> > > > Re-sending this patch-
On Thu, Sep 16, 2021 at 3:31 PM Daniel Vetter wrote:
>
> On Wed, Sep 15, 2021 at 10:45:36AM +0300, Oded Gabbay wrote:
> > On Tue, Sep 14, 2021 at 7:12 PM Jason Gunthorpe wrote:
> > >
> > > On Tue, Sep 14, 2021 at 04:18:31PM +0200, Daniel Vetter wrote:
> > > > On Sun, Sep 12, 2021 at 07:53:07PM +0
Am 16.09.21 um 14:14 schrieb Daniel Vetter:
On Thu, Sep 16, 2021 at 10:50 AM Christian König
wrote:
Am 14.09.21 um 19:04 schrieb Daniel Vetter:
On Fri, Sep 10, 2021 at 10:26:42AM +0200, Christian König wrote:
Abstract the complexity of iterating over all the fences
in a dma_resv object.
The
On Wed, Sep 15, 2021 at 04:38:31PM -0400, Sean Paul wrote:
> From: Sean Paul
>
> This patch adds the bindings for the MSM DisplayPort HDCP registers
> which are required to write the HDCP key into the display controller as
> well as the registers to enable HDCP authentication/key
> exchange/encry
Op 14-09-2021 om 15:54 schreef Daniel Vetter:
> On Tue, Sep 14, 2021 at 02:43:02PM +0200, Maarten Lankhorst wrote:
>> Op 14-09-2021 om 08:50 schreef Peter Zijlstra:
>>> On Mon, Sep 13, 2021 at 10:42:36AM +0200, Maarten Lankhorst wrote:
>>>
> +/**
> + * ww_mutex_trylock - tries to acquire th
On Thu, Sep 16, 2021 at 02:31:34PM +0200, Daniel Vetter wrote:
> On Wed, Sep 15, 2021 at 10:45:36AM +0300, Oded Gabbay wrote:
> > On Tue, Sep 14, 2021 at 7:12 PM Jason Gunthorpe wrote:
> > >
> > > On Tue, Sep 14, 2021 at 04:18:31PM +0200, Daniel Vetter wrote:
> > > > On Sun, Sep 12, 2021 at 07:53:
On Thu, Sep 16, 2021 at 3:44 PM Oded Gabbay wrote:
>
> On Thu, Sep 16, 2021 at 3:31 PM Daniel Vetter wrote:
> >
> > Maybe I got the device security model all wrong, but I thought Guadi is
> > single user, and the only thing it protects is the system against the
> > Gaudi device trhough iommu/devi
Hi,
On 9/16/21 5:20 AM, Stephen Boyd wrote:
> Quoting Hans de Goede (2021-08-17 14:52:01)
>> diff --git a/drivers/usb/typec/altmodes/displayport.c
>> b/drivers/usb/typec/altmodes/displayport.c
>> index aa669b9cf70e..c1d8c23baa39 100644
>> --- a/drivers/usb/typec/altmodes/displayport.c
>> +++ b/dr
On Thu, Sep 16, 2021 at 03:00:39PM +0200, Maarten Lankhorst wrote:
> > For merge logistics, can we pls have a stable branch? I expect that the
> > i915 patches will be ready for 5.16.
> >
> > Or send it in for -rc2 so that the interface change doesn't cause needless
> > conflicts, whatever you thi
This code has two bugs:
1) "cnt" is 255 but the size of the buffer is 256 so the last byte is
not used.
2) If we try to print more than 255 characters then "cnt" will be
negative and that will trigger a WARN() in snprintf(). The fix for
this is to use scnprintf() instead of snprintf().
We
Hi Dave & Daniel -
Fixes for v5.15-rc2. Looks like our CI is currently unhealthy. It's a
wip, but these don't seem to make matters worse, so I think better get
them moving than holding on.
drm-intel-fixes-2021-09-16:
drm/i915 fixes for v5.15-rc2:
- Propagate DP link training error returns
- Us
Changes in v3:
- Fixed build error [1], due to missing EXPORT_SYMBOL_GPL in patch-3
[1] https://patchwork.freedesktop.org/series/94696/#rev2
Changes in v2:
- Fixed compilation error [1] due to typo in patch-3 (stack_depot_print
used in place of stack_depot_snprint)
This compilation error
stack_depot_save allocates slabs that will be used for storing
objects in future.If this slab allocation fails we may get to
a situation where space allocation for a new stack_record fails,
causing stack_depot_save to return 0 as handle.
If user of this handle ends up invoking stack_depot_fetch wit
To print a stack entries, users of stackdepot, first
use stack_depot_fetch to get a list of stack entries
and then use stack_trace_print to print this list.
Provide a helper in stackdepot to print stack entries
based on stackdepot handle.
Also change above mentioned users to use this helper.
Signe
To print stack entries into a buffer, users of stackdepot,
first get a list of stack entries using stack_depot_fetch
and then print this list into a buffer using stack_trace_snprint.
Provide a helper in stackdepot for this purpose.
Also change above mentioned users to use this helper.
Signed-off-b
https://bugzilla.kernel.org/show_bug.cgi?id=214427
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
On Mon, Sep 06, 2021 at 09:35:19AM +0200, Hans de Goede wrote:
> Add support for eDP panels with a built-in privacy screen using the
> new drm_privacy_screen class.
>
> One thing which stands out here is the addition of these 2 lines to
> intel_atomic_commit_tail:
>
> for_each_new_connector
On Wed, 2021-09-15 at 19:59 +0100, Matthew Auld wrote:
> For cached objects we can allocate our pages directly in shmem. This
> should make it possible(in a later patch) to utilise the existing
> i915-gem shrinker code for such objects. For now this is still
> disabled.
>
> Signed-off-by: Matthew
This is a note to let you know that I've just added the patch titled
drm/mgag200: Select clock in PLL update functions
to the 5.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-
This is a note to let you know that I've just added the patch titled
drm/mgag200: Select clock in PLL update functions
to the 5.13-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-
On Thu, Sep 16, 2021 at 06:56:32PM +0800, Cai Huoqing wrote:
> When possible use dev_err_probe help to properly deal with the
> PROBE_DEFER error, the benefit is that DEFER issue will be logged
> in the devices_deferred debugfs file.
> And using dev_err_probe() can reduce code size, the error value
On Thu, Sep 16, 2021 at 06:56:24PM +0800, Cai Huoqing wrote:
> When possible use dev_err_probe help to properly deal with the
> PROBE_DEFER error, the benefit is that DEFER issue will be logged
> in the devices_deferred debugfs file.
> And using dev_err_probe() can reduce code size, the error value
This is a note to let you know that I've just added the patch titled
drm/mgag200: Select clock in PLL update functions
to the 5.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-
On Wed, Sep 15, 2021 at 07:58:36PM +0200, Jernej Skrabec wrote:
> Recent rework, which made HDMI PHY driver a platform device, inadvertely
> reversed clock setup order. HW is very touchy about it. Proper way is to
> handle controllers resets and clocks first and HDMI PHYs second.
>
> Currently, wi
On Wed, Sep 15, 2021 at 11:23:45AM -0400, Rodrigo Vivi wrote:
> On Wed, Sep 15, 2021 at 08:11:54AM -0700, Daniele Ceraolo Spurio wrote:
> >
> >
> > On 9/14/2021 12:13 PM, Rodrigo Vivi wrote:
> > > On Fri, Sep 10, 2021 at 08:36:22AM -0700, Daniele Ceraolo Spurio wrote:
> > > > From: "Huang, Sean Z
On Thu, Sep 16, 2021 at 02:06:56PM +0300, Jani Nikula wrote:
> On Wed, 15 Sep 2021, Rodrigo Vivi wrote:
> > On Wed, Sep 15, 2021 at 04:53:35PM +0300, Jani Nikula wrote:
> >> On Fri, 10 Sep 2021, Daniele Ceraolo Spurio
> >> wrote:
> >> > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> >> > b
On Thu, Sep 16, 2021 at 12:40:11PM +0300, Jani Nikula wrote:
>
> Cc: Ville for input here, see question inline.
>
> On Mon, 06 Sep 2021, Hans de Goede wrote:
> > Add support for eDP panels with a built-in privacy screen using the
> > new drm_privacy_screen class.
> >
> > One thing which stands o
Hi Dave, Daniel,
Fixes for 5.15.
The following changes since commit 6880fa6c56601bb8ed59df6c30fd390cc5f6dd8f:
Linux 5.15-rc1 (2021-09-12 16:28:37 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-5.15-2021-09-16
for you to fe
On Thu, Sep 16, 2021 at 02:49:26PM +0200, Christian König wrote:
> Am 16.09.21 um 14:14 schrieb Daniel Vetter:
> > On Thu, Sep 16, 2021 at 10:50 AM Christian König
> > wrote:
> > > Am 14.09.21 um 19:04 schrieb Daniel Vetter:
> > > > On Fri, Sep 10, 2021 at 10:26:42AM +0200, Christian König wrote:
On 9/14/21 6:39 PM, Rob Herring wrote:
On Fri, Sep 10, 2021 at 01:42:45PM +0300, Mikko Perttunen wrote:
Add YAML device tree bindings for NVDEC, now in a more appropriate
place compared to the old textual Host1x bindings.
Signed-off-by: Mikko Perttunen
---
v5:
* Changed from nvidia,instance to
On Thu, Sep 16, 2021 at 01:39:49PM +0300, Mikko Perttunen wrote:
> On 9/16/21 12:44 PM, Thierry Reding wrote:
> > From: Thierry Reding
> > ...
> > diff --git a/drivers/gpu/drm/tegra/uapi.c b/drivers/gpu/drm/tegra/uapi.c
> > index 794c400c38b1..66fe8717e747 100644
> > --- a/drivers/gpu/drm/tegra/ua
On Wed, Sep 15, 2021 at 10:26:06AM -0700, Kuppuswamy, Sathyanarayanan wrote:
> I have a Intel variant patch (please check following patch). But it includes
> TDX changes as well. Shall I move TDX changes to different patch and just
> create a separate patch for adding intel_cc_platform_has()?
Yes,
On Thu, 2021-09-16 at 09:59 -0400, Rodrigo Vivi wrote:
> On Thu, Sep 16, 2021 at 02:06:56PM +0300, Jani Nikula wrote:
> > On Wed, 15 Sep 2021, Rodrigo Vivi wrote:
> > > On Wed, Sep 15, 2021 at 04:53:35PM +0300, Jani Nikula wrote:
> > > > On Fri, 10 Sep 2021, Daniele Ceraolo Spurio
> > > > wrote
16.09.2021 17:13, Mikko Perttunen пишет:
> The size property is not always populated, while the gem.size
> property is.
>
> Fixes: d7c591bc1a3f ("drm/tegra: Implement new UAPI")
> Signed-off-by: Mikko Perttunen
> ---
> drivers/gpu/drm/tegra/uapi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 dele
On 9/16/21 6:56 PM, Dmitry Osipenko wrote:
16.09.2021 17:13, Mikko Perttunen пишет:
The size property is not always populated, while the gem.size
property is.
Fixes: d7c591bc1a3f ("drm/tegra: Implement new UAPI")
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/uapi.c | 2 +-
1 file
Hi Fabio
Thanks for confirming.
Although I have no issues with your change, I am curious why even msm is
probing and/or binding.
Your device tree should not be having any mdp/dpu nodes then.
Thanks
Abhinav
On 2021-09-16 04:42, Fabio Estevam wrote:
Hi Abhinav,
On Wed, Sep 15, 2021 at 11:22
From: Thomas Zimmermann
commit 147696720eca12ae48d020726208b9a61cdd80bc upstream.
Put the clock-selection code into each of the PLL-update functions to
make them select the correct pixel clock. Instead of copying the code,
introduce a new helper WREG_MISC_MASKED, which does masked writes into
.
HI Dexuan, thanks for confirming. Could you please add this as a
comment to the function.
Reviewed-by: Deepak Rawat
On Tue, Sep 14, 2021 at 11:59 PM Dexuan Cui wrote:
>
> > From: Deepak Rawat
> > Sent: Tuesday, September 14, 2021 8:59 AM
> > ...
> > > +/* Send mouse pointer info to host */
> >
Hi Abhinav,
On Thu, Sep 16, 2021 at 1:15 PM wrote:
>
> Hi Fabio
>
> Thanks for confirming.
>
> Although I have no issues with your change, I am curious why even msm is
> probing and/or binding.
> Your device tree should not be having any mdp/dpu nodes then.
The i.MX53 does have the following GPU
Don't blow up on a GEM_WARN_ON in __i915_gem_object_is_lmem if the
object is pinned (not evictable).
Signed-off-by: Matthew Brost
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem
From: Venkata Sandeep Dhanalakota
Defining vma on stack can cause stack overflow, if
vma gets populated with new fields.
v2:
(Daniel Vetter)
- Add kerneldoc for new field
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Matthew Brost
Minimum set of patches to enable GuC submission on DG1 and enable it by
default.
A little difficult to test as IGTs do not work with DG1 due to a bunch
of uAPI features being disabled (e.g. relocations, caching memory
options, etc...) and CI for DG1 isn't all that useful yet. Tested quite
thorough
Enable GuC submission by default on DG1
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 86c318516e14..2fef3b0bbe95 10064
From: Daniele Ceraolo Spurio
The firmware binary has to be loaded from lmem and the recommendation is
to put all other objects in there as well. Note that we don't fall back
to system memory if the allocation in lmem fails because all objects are
allocated during driver load and if we have issues
From: Daniele Ceraolo Spurio
Add DG1 GuC / HuC firmware defs
Signed-off-by: Matthew Brost
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
From: Thomas Zimmermann
commit 147696720eca12ae48d020726208b9a61cdd80bc upstream.
Put the clock-selection code into each of the PLL-update functions to
make them select the correct pixel clock. Instead of copying the code,
introduce a new helper WREG_MISC_MASKED, which does masked writes into
.
Hi Fabio
Ah, I did not realize that amd compatible is present in the list and its
quite a surprise.
/*
* We don't know what's the best binding to link the gpu with the drm
device.
* Fow now, we just hunt for all the possible gpus that we support, and
add them
* as components.
*/
static
[+cc Huacai, linux-pci]
On Wed, May 19, 2021 at 09:57:23PM +0800, Kai-Heng Feng wrote:
> Commit 3d42f1ddc47a ("vgaarb: Keep adding VGA device in queue") assumes
> the first device is an integrated GPU. However, on AMD platforms an
> integrated GPU can have higher PCI device number than a discrete
On 09/16, Iago Toral wrote:
> I think this looks good overall, I have a few questions/commments
> below:
>
> On Wed, 2021-08-18 at 18:57 +0100, Melissa Wen wrote:
> > Using the generic extension support set in the previous patch, this
> > patch enables more than one in/out binary syncobj per job s
On Thu, 2021-09-16 at 11:06 +0200, Hans de Goede wrote:
> Hi,
>
> On 9/15/21 10:26 PM, Lyude Paul wrote:
> > On Mon, 2021-09-06 at 09:35 +0200, Hans de Goede wrote:
> > > Add support for privacy-screen consumers to register a notifier to
> > > be notified of external (e.g. done by the hw itself on
From: Thomas Zimmermann
commit 147696720eca12ae48d020726208b9a61cdd80bc upstream.
Put the clock-selection code into each of the PLL-update functions to
make them select the correct pixel clock. Instead of copying the code,
introduce a new helper WREG_MISC_MASKED, which does masked writes into
.
On Fri, 2020-08-21 at 15:41 +0200, Stefan Agner wrote:
> Hi Matthias,
>
> On 2020-08-20 12:58, Matthias Schiffer wrote:
> > The PIXCLK needs to be enabled in SCFG before accessing the DCU on LS1021A,
> > or the access will hang.
>
> Hm, this seems a rather ad-hoc access to SCFG from the DCU. We d
Hello,
syzbot found the following issue on:
HEAD commit:78e709522d2c Merge tag 'for_linus' of git://git.kernel.org..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=16029aed30
kernel config: https://syzkaller.appspot.com/x/.config?x=2150ebd7e72fa695
das
The MODULE_DEVICE_TABLE already creates proper alias for platform
driver. Having another MODULE_ALIAS causes the alias to be duplicated.
Signed-off-by: Krzysztof Kozlowski
---
drivers/video/fbdev/s3c-fb.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/video/fbdev/s3c-fb.c b/drivers/
The MODULE_DEVICE_TABLE already creates proper alias for platform
driver. Having another MODULE_ALIAS causes the alias to be duplicated.
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/armada/armada_drv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/armada/armada_dr
On Thu, 2021-09-16 at 09:28 -0700, Matthew Brost wrote:
> Don't blow up on a GEM_WARN_ON in __i915_gem_object_is_lmem if the
> object is pinned (not evictable).
>
> Signed-off-by: Matthew Brost
> Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
> ---
> drivers/gpu/drm/i915/gem/i915_gem_lmem
Hi Cai,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tegra/for-next]
[also build test ERROR on v5.15-rc1 next-20210916]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as doc
Hi,
On Tue, Sep 14, 2021 at 4:14 AM Heiko Stübner wrote:
>
> Hi,
>
> Am Mittwoch, 8. September 2021, 15:53:56 CEST schrieb Chris Morgan:
> > From: Chris Morgan
> >
> > After commit 928f9e268611 ("clk: fractional-divider: Hide
> > clk_fractional_divider_ops from wide audience") was merged it appe
> From: Deepak Rawat
> Sent: Thursday, September 16, 2021 9:17 AM
> To: Dexuan Cui
> Cc: Haiyang Zhang ; David Airlie ;
> Daniel Vetter ; Thomas Zimmermann
> ; dri-devel@lists.freedesktop.org;
> linux-hyp...@vger.kernel.org; linux-ker...@vger.kernel.org
> Subject: Re: [PATCH] drm/hyperv: Fix doub
On 9/16/2021 09:28, Matthew Brost wrote:
Enable GuC submission by default on DG1
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/
The size property is not always populated, while the gem.size
property is.
Fixes: d7c591bc1a3f ("drm/tegra: Implement new UAPI")
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/uapi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tegra/uapi.c b/driv
Add devm_arch_phys_wc_add() and devm_arch_io_reserve_memtype_wc() for
automatic cleanup of writecombine setup.
Several DRM drivers use the non-managed functions for setting their
framebuffer memory to write-combine access. Convert ast, mgag200 and
vboxvideo. Remove rsp clean-up code form drivers.
Add devm_arch_io_reserve_memtype_wc() as managed wrapper around
arch_io_reserve_memtype_wc(). Useful for several grahpics drivers
that set framebuffer memory to write combining.
Signed-off-by: Thomas Zimmermann
---
include/linux/io.h | 3 +++
lib/devres.c | 46
Add devm_arch_phys_wc_add() as managed wrapper around arch_phys_wc_add().
Useful for several grahpics drivers that set framebuffer memory to write
combining.
Signed-off-by: Thomas Zimmermann
---
include/linux/io.h | 2 ++
lib/devres.c | 36
2 files cha
Replace arch_phys_wc_add() and arch_io_reserve_memtype_wc() with
the rsp managed functions. Allows for removing the cleanup code
for memory management
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 2 --
drivers/gpu/drm/ast/ast_mm.c | 27 ++-
2 fil
Replace arch_phys_wc_add() with the rsp managed function. Allows for
removing the cleanup code for memory management
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/vboxvideo/vbox_drv.c | 5 +
drivers/gpu/drm/vboxvideo/vbox_drv.h | 1 -
drivers/gpu/drm/vboxvideo/vbox_ttm.c | 17 ++
Replace arch_phys_wc_add() and arch_io_reserve_memtype_wc() with
the rsp managed functions. Allows for removing the cleanup code
for memory management
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/mgag200/mgag200_drv.h | 2 --
drivers/gpu/drm/mgag200/mgag200_mm.c | 35 ++
The DMACTX field determines which context, as specified in the
TRANSCFG register, is used. While during boot it doesn't matter
which is used, later on it matters and this value is reused by
the firmware.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/falcon.c | 8
drivers/gpu/
Hi all,
***
New in v2:
Added support for Tegra194
Use standard iommu-map property instead of custom mechanism
***
this series adds support for Host1x 'context isolation'. Since
when programming engines through Host1x, userspace can program in
any addresses it wants, we need some way to isolate t
Set itself as the IOMMU for the host1x context device bus, containing
"dummy" devices used for Host1x context isolation.
Signed-off-by: Mikko Perttunen
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu
For engines that support context isolation, allocate a context when
opening a channel, and set up stream ID offset and context fields
when submitting a job.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.h| 2 ++
drivers/gpu/drm/tegra/submit.c | 13 +
drivers/gpu/d
Add code to do stream ID switching at the beginning of a job. The
stream ID is switched to the stream ID specified by the context
passed in the job structure.
Before switching the stream ID, an OP_DONE wait is done on the
channel's engine to ensure that there is no residual ongoing
work that might
Implement the get_streamid_offset required for supporting context
isolation. Since old firmware cannot support context isolation
without hacks that we don't want to implement, check the firmware
binary to see if context isolation should be enabled.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/
Add code to register context devices from device tree, allocate them
out and manage their refcounts.
Signed-off-by: Mikko Perttunen
---
v2:
* Directly set DMA mask instead of inheriting from Host1x.
* Use iommu-map instead of custom DT property.
---
drivers/gpu/host1x/Makefile | 1 +
drivers/
Add Host1x context stream IDs on systems that support Host1x context
isolation. Host1x and attached engines can use these stream IDs to
allow isolation between memory used by different processes.
The specified stream IDs must match those configured by the hypervisor,
if one is present.
Signed-off
The context bus is a "dummy" bus that contains struct devices that
correspond to IOMMU contexts assigned through Host1x to processes.
Even when host1x itself is built as a module, the bus is registered
in built-in code so that the built-in ARM SMMU driver is able to
reference it.
Signed-off-by: M
On 9/16/21 8:02 AM, Borislav Petkov wrote:
On Wed, Sep 15, 2021 at 10:26:06AM -0700, Kuppuswamy, Sathyanarayanan wrote:
I have a Intel variant patch (please check following patch). But it includes
TDX changes as well. Shall I move TDX changes to different patch and just
create a separate patc
From: John Harrison
Implement support for fetching the hardware description table from the
GuC. The call is made twice - once without a destination buffer to
query the size and then a second time to fill in the buffer.
Note that the table is only available on ADL-P and later platforms.
Cc: Mich
From: John Harrison
Various UMDs require hardware configuration information about the
current platform. A bunch of static information is available in a
fixed table that can be retrieved from the GuC.
v2: Add a kerneldoc comment.
Test-with: 20210915215558.2473428-2-john.c.harri...@intel.com
UMD:
From: Rodrigo Vivi
GuC contains a consolidated table with a bunch of information about the
current device.
Previously, this information was spread and hardcoded to all the components
including GuC, i915 and various UMDs. The goal here is to consolidate
the data into GuC in a way that all interes
On Thu, Sep 16, 2021 at 10:08:05AM -0700, Doug Anderson wrote:
> Hi,
>
> On Tue, Sep 14, 2021 at 4:14 AM Heiko Stübner wrote:
> >
> > Hi,
> >
> > Am Mittwoch, 8. September 2021, 15:53:56 CEST schrieb Chris Morgan:
> > > From: Chris Morgan
> > >
> > > After commit 928f9e268611 ("clk: fractional-d
Here's the v6 of the NVDEC support series, containing the
following changes:
* Minor changes to device tree bindings. See patch for details.
NVDEC hardware documentation can be found at
https://github.com/NVIDIA/open-gpu-doc/tree/master/classes/video
and example userspace can be found at
https:/
Add support for booting and using NVDEC on Tegra210, Tegra186
and Tegra194 to the Host1x and TegraDRM drivers. Booting in
secure mode is not currently supported.
Signed-off-by: Mikko Perttunen
---
v5:
* Remove num_instances
* Change from nvidia,instance to nvidia,host1x-class
v3:
* Change num_ins
Add YAML device tree bindings for NVDEC, now in a more appropriate
place compared to the old textual Host1x bindings.
Signed-off-by: Mikko Perttunen
---
v6:
* Elaborated description for nvidia,host1x-class.
* Added default value for nvidia,host1x-class.
v5:
* Changed from nvidia,instance to nvidi
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