Am 03.09.21 um 08:49 schrieb Pan, Xinhui:
Like vce/vcn does, visible VRAM is ok for ib test.
And in ib test stage, VRAM is sufficient.
NAK, that won't work for older hw generations (e.g. SI, maybe CIK as
well) where the IBs must be in a specific GTT hardware window.
Christian.
Signed-off-
Am 03.09.21 um 08:49 schrieb Pan, Xinhui:
The ret value might be -EBUSY, caller will think lru lock is still
locked but actually NOT. So return -ENOSPC instead. Otherwise we hit
list corruption.
ttm_bo_cleanup_refs might fail too if BO is not idle. If we return 0,
caller(ttm_tt_populate -> ttm_g
在 2021/9/3 15:04,“Koenig, Christian” 写入:
Am 03.09.21 um 08:49 schrieb Pan, Xinhui:
> Like vce/vcn does, visible VRAM is ok for ib test.
> And in ib test stage, VRAM is sufficient.
NAK, that won't work for older hw generations (e.g. SI, maybe CIK as
well) where the IBs
On 02.09.2021 01:10, Doug Anderson wrote:
> Hi,
>
> On Wed, Sep 1, 2021 at 2:12 PM Olof Johansson wrote:
>>
>> On Wed, Sep 1, 2021 at 1:20 PM Douglas Anderson
>> wrote:
>>>
>>> In the patch ("drm/panel-simple-edp: Split eDP panels out of
>>> panel-simple") we split the PANEL_SIMPLE driver in 2.
Am 03.09.21 um 09:15 schrieb Pan, Xinhui:
在 2021/9/3 15:04,“Koenig, Christian” 写入:
Am 03.09.21 um 08:49 schrieb Pan, Xinhui:
> Like vce/vcn does, visible VRAM is ok for ib test.
> And in ib test stage, VRAM is sufficient.
NAK, that won't work for older hw generations
On 02/09/2021 15:20, Daniel Vetter wrote:
The important part isn't so much that this does an rcu lookup - that's
more an implementation detail, which will also be removed.
The thing that makes this different from other functions is that it's
gettting you the vm that batchbuffers will run in fo
Am 02.09.21 um 16:42 schrieb Daniel Vetter:
On Wed, Sep 01, 2021 at 02:02:40PM +0200, Christian König wrote:
That the caller doesn't need to keep a reference is rather
risky and not defensive at all.
Especially dma_buf_poll got that horrible wrong, so better
remove that sentence and also clarif
Pan, you're sending patches to amd-gfx-boun...@lists.freedesktop.org, which
doesn't work. You need to send them to amd-...@lists.freedesktop.org instead.
--
Earthling Michel Dänzer | https://redhat.com
Libre software enthusiast | Mesa and X
On Thu, 2 Sep 2021 15:00:38 +0100
Steven Price wrote:
> It turns out that when locking a region, the region must be a naturally
> aligned power of 2. The upshot of this is that if the desired region
> crosses a 'large boundary' the region size must be increased
> significantly to ensure that the
Android Hardware Composer supports alpha values applied to layers.
Enabling non-opaque layers for the STM CRTC could help offload GPU
resources for screen composition.
Signed-off-by: Raphael Gallais-Pou
---
drivers/gpu/drm/stm/ltdc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
On 03/09/2021 09:51, Boris Brezillon wrote:
> On Thu, 2 Sep 2021 15:00:38 +0100
> Steven Price wrote:
>
>> It turns out that when locking a region, the region must be a naturally
>> aligned power of 2. The upshot of this is that if the desired region
>> crosses a 'large boundary' the region size
On Fri, Sep 03, 2021 at 11:24:02AM +0800, ZhiJie.Zhang wrote:
> From: zhangzhijie
>
> this callback was used by drm_kms_helper_hotplug_event()
>
> V2: (Thanks for Daniel's suggestions)
> - remove the FIXME below.since with the drm_client
> - infrastructure and the generic fbdev emulation we've
>
drm-misc-next-fixes-2021-09-03:
drm-misc-next-fixes for v5.15:
- Fix ttm_bo_move_memcpy() when ttm_resource is subclassed.
- Small fixes to panfrost, mgag200, vc4.
- Small ttm compilation fixes.
The following changes since commit 2819cf0e7dbe45a2bccf2f6c60fe6a27b299cc3e:
Merge tag 'drm-misc-next
It turns out that when locking a region, the region must be a naturally
aligned power of 2. The upshot of this is that if the desired region
crosses a 'large boundary' the region size must be increased
significantly to ensure that the locked region completely covers the
desired region. Previous cal
On 02/09/2021 21:02, Daniel Vetter wrote:
On Thu, Sep 2, 2021 at 6:20 PM Tvrtko Ursulin
wrote:
On 02/09/2021 16:05, Daniel Vetter wrote:
On Thu, Sep 2, 2021 at 2:42 PM Tvrtko Ursulin
wrote:
On 13/08/2021 21:30, Daniel Vetter wrote:
The only reason for this really is the i915_gem_engines
On 31/08/2021 21:21, Jim Cromie wrote:
The gvt component of this driver has ~120 pr_debugs, in 9 categories
quite similar to those in DRM. Following the interface model of
drm.debug, add a parameter to map bits to these categorizations.
DEFINE_DYNAMIC_DEBUG_CATEGORIES(debug_gvt, __gvt_debug,
On 31/08/2021 21:21, Jim Cromie wrote:
drm's debug system writes 10 distinct categories of messages to syslog
using a small API[1]: drm_dbg*(10 names), DRM_DEV_DEBUG*(3 names),
DRM_DEBUG*(8 names). There are thousands of these callsites, each
categorized in this systematized way.
These callsi
Currently we blow up in trace_dma_fence_init, when calling into
get_driver_name or get_timeline_name, since both the engine and context
might be NULL(or contain some garbage address) in the case of newly
allocated slab objects via the request ctor. Note that we also use
SLAB_TYPESAFE_BY_RCU here, w
https://bugzilla.kernel.org/show_bug.cgi?id=211277
--- Comment #47 from James Zhu (jam...@amd.com) ---
Hi Jerome,
Thanks! I knew this issue is not easy to judge if it is fixed. Since it
occurred quite randomly. On my setup, this WA passed 5 times up to 300
suspend/resume cycles, 1 time up to 3800
drm_sched_job_cleanup() will pass an uninitialized fence to
drm_sched_fence_free(), which will cause to_drm_sched_fence() to return
a NULL fence object, causing a NULL pointer deref when this NULL object
is passed to kmem_cache_free().
Let's create a new drm_sched_fence_free() function that takes
https://bugzilla.kernel.org/show_bug.cgi?id=211277
Anthony Rabbito (ted...@gmail.com) changed:
What|Removed |Added
CC||ted...@gmail.com
---
https://bugzilla.kernel.org/show_bug.cgi?id=211277
--- Comment #49 from Anthony Rabbito (ted...@gmail.com) ---
Created attachment 298661
--> https://bugzilla.kernel.org/attachment.cgi?id=298661&action=edit
journalctl of amdgpu trace
(In reply to Anthony Rabbito from comment #48)
--
You may re
https://bugzilla.kernel.org/show_bug.cgi?id=211277
--- Comment #50 from James Zhu (jam...@amd.com) ---
Hi Anthony,
Can you try if Comment #37? see if it helps. But from the log that you
attached, it is a different issue that GFX hw has lots of ECC error, which
cause gfx ring time out. after that
Clean up to start over with new and more accurate documentation.
Signed-off-by: Christian König
---
Documentation/gpu/drm-mm.rst | 49
1 file changed, 49 deletions(-)
diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst
index 0198fa43d254
Fix the remaining warnings, switch to inline structure documentation
and finally enable this.
Signed-off-by: Christian König
---
Documentation/gpu/drm-mm.rst | 9 +
include/drm/ttm/ttm_device.h | 73 +---
2 files changed, 51 insertions(+), 31 deletions(-)
di
Fix the last two remaining warnings and finally enable this.
Signed-off-by: Christian König
---
Documentation/gpu/drm-mm.rst | 9 +
include/drm/ttm/ttm_resource.h | 6 ++
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gp
Fix the last remaining warning and finally enable this.
Signed-off-by: Christian König
---
Documentation/gpu/drm-mm.rst| 6 ++
include/drm/ttm/ttm_placement.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst
index 094e36713
Fix the remaining warnings and finally enable this.
Signed-off-by: Christian König
---
Documentation/gpu/drm-mm.rst | 9 +
include/drm/ttm/ttm_tt.h | 9 +++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.r
Add support for booting and using NVDEC on Tegra210, Tegra186
and Tegra194 to the Host1x and TegraDRM drivers. Booting in
secure mode is not currently supported.
Signed-off-by: Mikko Perttunen
---
v3:
* Change num_instances to unsigned int
* Remove unnecessary '= 0' initializer
* Populate num_ins
Add a device tree node for NVDEC on Tegra186, and
device tree nodes for NVDEC and NVDEC1 on Tegra194.
Signed-off-by: Mikko Perttunen
---
v4:
* Add dma-coherent markers
v3:
* Change read2 to read-1
v2:
* Add NVDECSRD1 memory client
* Add also to T194 (both NVDEC0/1)
---
arch/arm64/boot/dts/nvidia
Here's the v4 of the NVDEC support series, containing two fixes
compared to v3:
* Fixed incorrect compatibility string in bindings YAML
* Added dma-coherent markers to Tegra194 device trees.
NVDEC hardware documentation can be found at
https://github.com/NVIDIA/open-gpu-doc/tree/master/classes/vi
Add YAML device tree bindings for NVDEC, now in a more appropriate
place compared to the old textual Host1x bindings.
Signed-off-by: Mikko Perttunen
---
v4:
* Fix incorrect compatibility string in 'if' condition
v3:
* Drop host1x bindings
* Change read2 to read-1 in interconnect names
v2:
* Fix i
On 02.09.21 08:05, yunfei.d...@mediatek.com wrote:
On Wed, 2021-09-01 at 14:17 +0200, Dafna Hirschfeld wrote:
Hi Dafna,
Thanks for your suggestion.
Hi
On 01.09.21 10:32, Yunfei Dong wrote:
There are just one core thread, in order to separeate different
hardware, using codec type to separea
On 29/07/2021 15:06, Daniel Vetter wrote:
On Thu, Jul 29, 2021 at 3:34 PM Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
Usage of Transparent Hugepages was disabled in 9987da4b5dcf
("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
appears majority of performance regressio
validate_lease expects one CRTC, one connector and one plane.
Signed-off-by: Simon Ser
Cc: Daniel Vetter
Cc: Pekka Paalanen
Cc: Keith Packard
---
include/uapi/drm/drm_mode.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index
This can be used to create a separate DRM file description, thus
creating a new GEM handle namespace.
My use-case is wlroots. The library splits responsibilities between
separate components: the GBM allocator creates buffers, the GLES2
renderer uses EGL to import them and render to them, the DRM
b
On Fri, 3 Sept 2021 at 13:31, Christian König
wrote:
>
> Fix the remaining warnings, switch to inline structure documentation
> and finally enable this.
>
> Signed-off-by: Christian König
> ---
> Documentation/gpu/drm-mm.rst | 9 +
> include/drm/ttm/ttm_device.h | 73 +--
On Wed, Sep 1, 2021 at 9:13 AM Thierry Reding wrote:
>
> On Fri, Jul 02, 2021 at 05:16:25PM +0300, Dmitry Osipenko wrote:
> > 01.07.2021 21:14, Thierry Reding пишет:
> > > On Tue, Jun 08, 2021 at 06:51:40PM +0200, Thierry Reding wrote:
> > >> On Fri, May 28, 2021 at 06:54:55PM +0200, Thierry Redin
On Fri, 3 Sept 2021 at 13:31, Christian König
wrote:
>
> Fix the last two remaining warnings and finally enable this.
>
> Signed-off-by: Christian König
> ---
> Documentation/gpu/drm-mm.rst | 9 +
> include/drm/ttm/ttm_resource.h | 6 ++
> 2 files changed, 11 insertions(+), 4 delet
On Fri, Sep 03, 2021 at 08:20:55AM -0500, Rob Herring wrote:
> On Wed, Sep 1, 2021 at 9:13 AM Thierry Reding
> wrote:
> >
> > On Fri, Jul 02, 2021 at 05:16:25PM +0300, Dmitry Osipenko wrote:
> > > 01.07.2021 21:14, Thierry Reding пишет:
> > > > On Tue, Jun 08, 2021 at 06:51:40PM +0200, Thierry Re
On Thu, Sep 02, 2021 at 02:10:48PM +0800, Dongliang Mu wrote:
> [ Upstream commit a49145acfb975d921464b84fe00279f99827d816 ]
>
> A fb_ioctl() FBIOPUT_VSCREENINFO call with invalid xres setting
> or yres setting in struct fb_var_screeninfo will result in a
> KASAN: vmalloc-out-of-bounds failure in
On Fri, 3 Sept 2021 at 13:31, Christian König
wrote:
>
> Clean up to start over with new and more accurate documentation.
>
> Signed-off-by: Christian König
For the series,
Reviewed-by: Matthew Auld
We could maybe also bring in ttm_pool.[ch]? It looks like it already
has near complete kernel-d
In preparation for clean driver release, attempts to drain work queues
and release freed objects are taken at driver remove time. However, GT
buffer pools are now not flushed before the driver release phase.
Since unused objects may stay there for up to one second, some may
survive until driver re
GPU wedged flag now set on driver unregister to prevent from further
using the GPU can be then cleared unintentionally when calling
__intel_gt_unset_wedged() still before the flag is finally marked
unrecoverable. We need to have it marked unrecoverable earlier.
Implement that by replacing a call t
On Fri, Sep 3, 2021 at 8:52 AM Thierry Reding wrote:
>
> On Fri, Sep 03, 2021 at 08:20:55AM -0500, Rob Herring wrote:
> > On Wed, Sep 1, 2021 at 9:13 AM Thierry Reding
> > wrote:
> > >
> > > On Fri, Jul 02, 2021 at 05:16:25PM +0300, Dmitry Osipenko wrote:
> > > > 01.07.2021 21:14, Thierry Reding
On Fri, Sep 03, 2021 at 09:36:33AM -0500, Rob Herring wrote:
> On Fri, Sep 3, 2021 at 8:52 AM Thierry Reding
> wrote:
> >
> > On Fri, Sep 03, 2021 at 08:20:55AM -0500, Rob Herring wrote:
> > > On Wed, Sep 1, 2021 at 9:13 AM Thierry Reding
> > > wrote:
> > > >
> > > > On Fri, Jul 02, 2021 at 05:
If we need to mark the PDE as operating in 64K GTT mode, we should be
paranoid and flush the extra writes, like we already do for the PTEs. On
some platforms the clflush can apparently add the just the right amount
of magical delay to force the GPU to see the updated entry.
Signed-off-by: Matthew
On Fri, 03 Sep 2021 11:31:53 +0300, Mikko Perttunen wrote:
> Add YAML device tree bindings for NVDEC, now in a more appropriate
> place compared to the old textual Host1x bindings.
>
> Signed-off-by: Mikko Perttunen
> ---
> v4:
> * Fix incorrect compatibility string in 'if' condition
> v3:
> * Dr
Hi Sudip,
On Thu, Sep 02, 2021 at 10:08:19AM +0100, Sudip Mukherjee wrote:
> Hi All,
>
> Our last night's test on rpi4 had a nasty trace. The test was with
> 7c636d4d20f8 ("Merge tag 'dt-5.15' of
> git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc"). Previous test
> was on 9e9fb7655ed5 ("Merg
Matthew Auld writes:
> If we need to mark the PDE as operating in 64K GTT mode, we should be
> paranoid and flush the extra writes, like we already do for the PTEs. On
> some platforms the clflush can apparently add the just the right amount
> of magical delay to force the GPU to see the updated
On Fri, Sep 03, 2021 at 11:31:53AM +0300, Mikko Perttunen wrote:
> Add YAML device tree bindings for NVDEC, now in a more appropriate
> place compared to the old textual Host1x bindings.
>
> Signed-off-by: Mikko Perttunen
> ---
> v4:
> * Fix incorrect compatibility string in 'if' condition
> v3:
Hello Geert,
On Thu, 2 Sept 2021 at 18:19, Geert Uytterhoeven wrote:
>
> Hi Sumit, Christian,
>
> This patch series adds missing dependencies on DMA_SHARED_BUFFER to
> various options of DMA-BUF, and drops a bogus select.
>
> As drivers/dma-buf/Kconfig contains interleaved options that se
This patch series adds support for the MDP and DSI PHY as found on the
MSM8953 platform (APQ8053, SDM450, SDA450, SDM625, SDM626). All the SoCs
on this platform use the adreno 506 GPU.
Changes since v1:
- Split the dsi phy doc changes into a separate commit
- Add Reviewed-by tag to patch 2
Sirees
SoCs based on the MSM8953 platform use the 14nm DSI PHY driver
Signed-off-by: Sireesh Kodali
---
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
b/Documentation/
From: Vladimir Lypak
Add phy configuration for 14nm dsi phy found on MSM8953 SoC. Only
difference from existing configurations are io_start addresses.
Signed-off-by: Vladimir Lypak
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Sireesh Kodali
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2
On 9/3/21 7:34 PM, Rob Herring wrote:
On Fri, Sep 03, 2021 at 11:31:53AM +0300, Mikko Perttunen wrote:
Add YAML device tree bindings for NVDEC, now in a more appropriate
place compared to the old textual Host1x bindings.
Signed-off-by: Mikko Perttunen
---
v4:
* Fix incorrect compatibility stri
On 01/09/2021 21:11, AngeloGioacchino Del Regno wrote:
Bringup functionality for MSM8998 in the DPU, driver which is mostly
the same as SDM845 (just a few variations).
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Dmitry Baryshkov
Few comments below
---
.../gpu/drm/msm/disp/d
On 01/09/2021 21:11, AngeloGioacchino Del Regno wrote:
The enum dpu_clk_ctrl_type misses DPU_CLK_CTRL_DMA{2,3} even though
this driver does actually handle both, if present: add the two in
preparation for adding support for SoCs having them.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed
On Wed, Sep 01, 2021 at 11:18:10AM +0200, Maxime Ripard wrote:
> The Advantech IDK-2121WR Device Tree binding doesn't really add any
> useful content that is not already present in the panel-lvds binding
> aside from a requirement on the data-mapping.
>
> Let's move it to the generic panel-lvds bi
On Wed, 01 Sep 2021 11:18:13 +0200, Maxime Ripard wrote:
> The Mitsubishi AA140XD12 Device Tree Binding was requiring a vcc-supply
> property. However, neither the existing device trees using that binding,
> nor the driver were actually using that property which is also redundant
> with power-suppl
On Wed, 01 Sep 2021 11:18:14 +0200, Maxime Ripard wrote:
> The Mitsubishi AA140XD12 Device Tree Binding was requiring a
> data-mapping property value which was set to another value in the
> existing Device Trees. Fix this.
>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Laurent Pinchart
> Cc: Sam R
On 02/09/2021 21:40, Lyude Paul wrote:
Reviewed-by: Lyude Paul
Do you need me to push this?
We'd pick this up through the msm tree.
On Tue, 2021-08-31 at 04:51 -0700, cgel@gmail.com wrote:
From: Chi Minghao
Fix the following coccicheck REVIEW:
./drivers/gpu/drm/msm/edp/edp_ctrl.c:12
On Wed, 01 Sep 2021 11:18:16 +0200, Maxime Ripard wrote:
> The Mitsubishi AA121TD01 Device Tree Binding was requiring a vcc-supply
> property. However, neither the existing device trees using that binding,
> nor the driver were actually using that property which is also redundant
> with power-suppl
On Wed, 01 Sep 2021 11:18:17 +0200, Maxime Ripard wrote:
> The Mitsubishi AA121TD01 Device Tree Binding was requiring a
> data-mapping property value which was set to another value in the
> existing Device Trees. Fix this.
>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Laurent Pinchart
> Cc: Sam R
On Fri, 2021-09-03 at 21:31 +0300, Dmitry Baryshkov wrote:
> On 02/09/2021 21:40, Lyude Paul wrote:
> > Reviewed-by: Lyude Paul
> >
> > Do you need me to push this?
>
> We'd pick this up through the msm tree.
ah-totally forgot msm had their own tree and didn't go through drm-misc-next.
Thanks!
From: Rob Clark
This series adds deadline awareness to fences, so realtime deadlines
such as vblank can be communicated to the fence signaller for power/
frequency management decisions.
This is partially inspired by a trick i915 does, but implemented
via dma-fence for a couple of reasons:
1) To
From: Rob Clark
Add a way to hint to the fence signaler of an upcoming deadline, such as
vblank, which the fence waiter would prefer not to miss. This is to aid
the fence signaler in making power management decisions, like boosting
frequency as the deadline approaches and awareness of missing de
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_vblank.c | 32
include/drm/drm_vblank.h | 1 +
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index b701cda86d0c..ec2732664b95 1006
From: Rob Clark
For an atomic commit updating a single CRTC (ie. a pageflip) calculate
the next vblank time, and inform the fence(s) of that deadline.
v2: Comment typo fix (danvet)
Signed-off-by: Rob Clark
Reviewed-by: Daniel Vetter
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_atomic_he
From: Rob Clark
As the finished fence is the one that is exposed to userspace, and
therefore the one that other operations, like atomic update, would
block on, we need to propagate the deadline from from the finished
fence to the actual hw fence.
v2: Split into drm_sched_fence_set_parent() (ckoe
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fence.c | 76 +++
drivers/gpu/drm/msm/msm_fence.h | 20 +++
drivers/gpu/drm/msm/msm_gpu.h | 1 +
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 20 +++
4 files changed, 117 inserti
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/dma-buf/dma-fence-array.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/dma-buf/dma-fence-array.c
b/drivers/dma-buf/dma-fence-array.c
index d3fbd950be94..8d194b09ee3d 100644
--- a/drivers/dma-buf/dma-fence-array.c
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/dma-buf/dma-fence-chain.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/dma-buf/dma-fence-chain.c
b/drivers/dma-buf/dma-fence-chain.c
index 1b4cb3e5cec9..736a9ad3ea6d 100644
--- a/drivers/dma-buf/dma-fence-chain.
From: Rob Clark
The initial purpose is for igt tests, but this would also be useful for
compositors that wait until close to vblank deadline to make decisions
about which frame to show.
Signed-off-by: Rob Clark
---
drivers/dma-buf/sync_file.c| 19 +++
include/uapi/linux/syn
From: Rob Clark
This consists of simply storing the most recent deadline, and adding an
ioctl to retrieve the deadline. This can be used in conjunction with
the SET_DEADLINE ioctl on a fence fd for testing. Ie. create various
sw_sync fences, merge them into a fence-array, set deadline on the
fe
On 31/08/2021 14:51, cgel@gmail.com wrote:
From: Chi Minghao
Fix the following coccicheck REVIEW:
./drivers/gpu/drm/msm/edp/edp_ctrl.c:1245:5-8 Unneeded variable
Reported-by: Zeal Robot
Signed-off-by: Chi Minghao
Reviewed-by: Dmitry Baryshkov
Glancing on msm/edp, as it was never supp
Hans de Goede asked me to take a topic from a private discussion here.
I must also preface that I'm not a graphics person and my knowledge of
DRI/DRM is cursory at best.
I initiated the conversation with de Goede after learning that the X
server now supports being started with an open DRM file des
On Fri, Sep 3, 2021 at 5:07 AM Tvrtko Ursulin
wrote:
>
>
> On 31/08/2021 21:21, Jim Cromie wrote:
> > The gvt component of this driver has ~120 pr_debugs, in 9 categories
> > quite similar to those in DRM. Following the interface model of
> > drm.debug, add a parameter to map bits to these catego
On Thu, Jul 29, 2021 at 1:49 PM Rob Clark wrote:
> On Thu, Jul 29, 2021 at 1:28 PM Caleb Connolly
> wrote:
> > On 29/07/2021 21:24, Rob Clark wrote:
> > > On Thu, Jul 29, 2021 at 1:06 PM Caleb Connolly
> > > wrote:
> > >>
> > >> Hi Rob,
> > >>
> > >> I've done some more testing! It looks like be
From: Matthew Brost
Add GuC kernel doc for all structures added thus far for GuC submission
and update the main GuC submission section with the new interface
details.
v2:
- Drop guc_active.lock DOC
v3:
- Fixup a few kernel doc comments (Daniele)
v4 (Daniele):
- Implement doc suggestions from
Hi Maxime,
On Fri, Sep 3, 2021 at 5:03 PM Maxime Ripard wrote:
>
> Hi Sudip,
>
> On Thu, Sep 02, 2021 at 10:08:19AM +0100, Sudip Mukherjee wrote:
> > Hi All,
> >
>
>
> >
> > You can see the complete dmesg at
> > https://openqa.qa.codethink.co.uk/tests/76#step/dmesg/8
>
> What test were you run
On Fri, Sep 3, 2021 at 12:39 PM John Stultz wrote:
>
> On Thu, Jul 29, 2021 at 1:49 PM Rob Clark wrote:
> > On Thu, Jul 29, 2021 at 1:28 PM Caleb Connolly
> > wrote:
> > > On 29/07/2021 21:24, Rob Clark wrote:
> > > > On Thu, Jul 29, 2021 at 1:06 PM Caleb Connolly
> > > > wrote:
> > > >>
> > >
Quoting Doug Anderson (2021-09-01 16:10:15)
> Hi,
>
> On Wed, Sep 1, 2021 at 2:12 PM Olof Johansson wrote:
> >
> > On Wed, Sep 1, 2021 at 1:20 PM Douglas Anderson
> > wrote:
> > >
> > > In the patch ("drm/panel-simple-edp: Split eDP panels out of
> > > panel-simple") we split the PANEL_SIMPLE d
On Fri, Sep 3, 2021 at 5:15 AM Tvrtko Ursulin
wrote:
>
>
> On 31/08/2021 21:21, Jim Cromie wrote:
> > drm's debug system writes 10 distinct categories of messages to syslog
> > using a small API[1]: drm_dbg*(10 names), DRM_DEV_DEBUG*(3 names),
> > DRM_DEBUG*(8 names). There are thousands of these
Hi, Jason:
jason-jh.lin 於 2021年8月25日 週三 下午10:48寫道:
>
> 1. Remove mediatek,dislpay.txt
> 2. Split each display function block to individual yaml file.
>
> Signed-off-by: jason-jh.lin
> ---
> .../display/mediatek/mediatek,aal.yaml| 75 ++
> .../display/mediatek/mediatek,ccorr.yaml
From: Matthew Brost
Propagating errors to dependent fences is broken and can lead to errors
from one client ending up in another. In commit 3761baae908a ("Revert
"drm/i915: Propagate errors on awaiting already signaled fences""), we
attempted to get rid of fence error propagation but missed the c
Now that Ayaz's MOCS initialization series has landed on
drm-intel-gt-next, we can add the new MOCS tables for XeHP SDV and DG2.
[1] https://patchwork.freedesktop.org/series/94315/
Lucas De Marchi (1):
drm/i915/xehpsdv: Define MOCS table for XeHP SDV
Matt Roper (1):
drm/i915/dg2: Define MOCS
From: Lucas De Marchi
Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
memory for L3 destined transaction" and L3_LKP to "enable Lookup for
uncacheable accesses".
Bspec: 45101
Cc: Daniele Ceraolo Spuri
Bspec: 45101, 45427
Cc: Ramalingam C
Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 37 +++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel
From: Vladimir Lypak
MDP version v1.16 is almost identical to v1.15 with most significant
difference being presence of second DSI interface. MDP v1.16 is found on
SoCs such as MSM8x53, SDM450, SDM632 (All with Adreno 506).
Signed-off-by: Vladimir Lypak
Signed-off-by: Sireesh Kodali
---
driver
On Fri, Sep 3, 2021 at 9:55 PM Greg KH wrote:
>
> On Thu, Sep 02, 2021 at 02:10:48PM +0800, Dongliang Mu wrote:
> > [ Upstream commit a49145acfb975d921464b84fe00279f99827d816 ]
> >
> > A fb_ioctl() FBIOPUT_VSCREENINFO call with invalid xres setting
> > or yres setting in struct fb_var_screeninfo w
Hi Danfa,
Thanks for your suggestion.
On Fri, 2021-09-03 at 14:42 +0200, Dafna Hirschfeld wrote:
>
> On 02.09.21 08:05, yunfei.d...@mediatek.com wrote:
> > On Wed, 2021-09-01 at 14:17 +0200, Dafna Hirschfeld wrote:
> > Hi Dafna,
> >
> > Thanks for your suggestion.
> > > Hi
> > >
> > > On 01.09.
On Thu, Sep 2, 2021 at 10:46 PM Daniel Vetter wrote:
>
> On Thu, Sep 02, 2021 at 07:19:01AM +0100, Anton Ivanov wrote:
> > On 02/09/2021 06:52, Randy Dunlap wrote:
> > > On 9/1/21 10:48 PM, Anton Ivanov wrote:
> > > > On 02/09/2021 03:01, Randy Dunlap wrote:
> > > > > boot_cpu_data [struct cpuinfo
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