Introduce a feature flag in gpulist to easily identify the capabilities
of each gpu revision. This will help to avoid a lot of adreno_is_axxx()
check when we add new features. In the current patch, HW APRIV feature
is converted to a feature flag.
Signed-off-by: Akhil P Oommen
---
This patch is re
On Thu, Jul 29, 2021 at 8:21 AM Akhil P Oommen wrote:
>
> This patch adds support for the gpu found in the Snapdragon 7c Gen 3
> compute platform. This gpu is similar to the exisiting a660 gpu with
> minor delta in the programing sequence. As the Adreno GPUs are moving
> away from a numeric chipid
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Add constants and params that are needed to configure SLPC.
>
> v2: Add a new abi header for SLPC. Replace bitfields with
> genmasks. Address other comments from Michal W.
>
> v3: Add slpc H2G format in abi, other review commments (Michal W)
>
>
On 7/29/2021 8:57 PM, Rob Clark wrote:
On Thu, Jul 29, 2021 at 7:33 AM Akhil P Oommen wrote:
Use rev instead of revn to identify the SKU. This is in
preparation to the introduction of 7c3 gpu which won't have a
revn.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm
On 7/29/2021 9:08 PM, Rob Clark wrote:
On Thu, Jul 29, 2021 at 8:21 AM Akhil P Oommen wrote:
This patch adds support for the gpu found in the Snapdragon 7c Gen 3
compute platform. This gpu is similar to the exisiting a660 gpu with
minor delta in the programing sequence. As the Adreno GPUs are
On Thu, Jul 29, 2021 at 8:36 AM Akhil P Oommen wrote:
>
> On 7/29/2021 8:57 PM, Rob Clark wrote:
> > On Thu, Jul 29, 2021 at 7:33 AM Akhil P Oommen
> > wrote:
> >>
> >> Use rev instead of revn to identify the SKU. This is in
> >> preparation to the introduction of 7c3 gpu which won't have a
> >>
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Add methods for interacting with GuC for enabling SLPC. Enable
> SLPC after GuC submission has been established. GuC load will
> fail if SLPC cannot be successfully initialized. Add various
> helper methods to set/unset the parameters for SLPC. They
Change in v2:
- add power-domain property into mediatek,mmsys.yaml
and modify commit message.
jason-jh.lin (5):
dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
dt-bindings: mediatek: display: Change format to yaml
dt-bindings: mediatek: display: add MERGE additional description
Add mt8195 SoC display binding.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,disp.yaml | 24 +--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
b/Documentation/devicetre
Change mediatek,dislpay.txt to mediatek,display.yaml
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,disp.txt| 219 -
.../display/mediatek/mediatek,disp.yaml | 432 ++
2 files changed, 432 insertions(+), 219 deletions(-)
delete mode 100644
Do
1. Add mediatek,dsc.yaml to decribe DSC module in details.
2. Add mt8195 SoC binding to mediatek,dsc.yaml.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,dsc.yaml| 73 +++
1 file changed, 73 insertions(+)
create mode 100644
Documentation/devicetree/bindin
1. clock drivers of MERGE
The MERGE controller may have 2 clock inputs.
The second clock of MERGE is async clock which is controlling
the async buffer between MERGE and other display function blocks.
2. MERGE fifo settings enable
The setting of merge fifo is mainly provided for the dis
1. There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
Each of them is bound to a display pipeline, so add their
definition in mtk-mmsys documentation with 2 compatibles.
2. Add description for power-domain property.
Signed-off-by: jason-jh.lin
---
this patch is base on [1][2]
[1] dt
On Thu, Jul 29, 2021 at 8:31 AM Akhil P Oommen wrote:
>
> Introduce a feature flag in gpulist to easily identify the capabilities
> of each gpu revision. This will help to avoid a lot of adreno_is_axxx()
> check when we add new features. In the current patch, HW APRIV feature
> is converted to a f
On 2021-07-22 12:23, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2021-07-13 08:54:05)
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c
b/drivers/gpu/drm/msm/dp/dp_panel.c
index 88196f7..0fdb551 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -303,7 +303,12
On Thu, Jul 29, 2021 at 5:19 PM Rob Clark wrote:
>
> On Thu, Jul 29, 2021 at 12:03 AM Daniel Vetter wrote:
> >
> > On Wed, Jul 28, 2021 at 10:58:51AM -0700, Rob Clark wrote:
> > > On Wed, Jul 28, 2021 at 10:23 AM Christian König
> > > wrote:
> > > >
> > > >
> > > >
> > > > Am 28.07.21 um 17:15 s
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Cache rp0, rp1 and rpn platform limits into SLPC structure
> for range checking while setting min/max frequencies.
>
> Also add "soft" limits which keep track of frequency changes
> made from userland. These are initially set to platform min
> and
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Add param set h2g helpers to set the min and max frequencies
> for use by SLPC.
>
> v2: Address review comments (Michal W)
> v3: Check for positive error code (Michal W)
> v4: Print generic error in set_param (Michal W)
>
> Signed-off-by: Sundares
On Thu, Jul 29, 2021 at 03:20:17PM +0200, Robert Foss wrote:
> Hey Jagan,
>
> On Sun, 4 Jul 2021 at 11:04, Jagan Teki wrote:
> >
> > Now the exynos dsi driver is fully aware of bridge
> > handling, so get the display mode from bridge, mode_set
> > API instead of legacy encoder crtc.
> >
> > This
Hi Laurent,
On Wed, Jul 28, 2021 at 06:37:29PM +0300, Laurent Pinchart wrote:
> Hello,
>
> This patch series stems from subsystem-wide changes I wanted to
> compile-test with an ARM64 cross-compiler. My laziness to fire a 32-bit
> ARM build probably resulted in more time being spent writing these
The hardware path of vdosys0 with eDP panel output need to go through
by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
DITHER, DSC and MERGE.
Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mm
Add display node for vdosys0.
Signed-off-by: jason-jh.lin
---
This patch is based on [1][2][3][4]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.w...@mediatek.com/
[2]arm64: dt
Add DSC into mtk_drm_ddp_comp to support for mt8195.
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specific
Add MERGE module file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/gpu/drm/med
Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/soc/mediatek/mt8195-mmsys.h|
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++
drive
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/soc/mediatek/mtk-mutex.c | 93 ++--
1 file changed,
Quoting Akhil P Oommen (2021-07-28 00:17:45)
> On 7/27/2021 5:46 AM, Stephen Boyd wrote:
> > Quoting Akhil P Oommen (2021-07-24 10:29:00)
> >> Add the necessary dt nodes for gpu support in sc7280.
> >>
> >> Signed-off-by: Akhil P Oommen
> >> ---
> >> This patch has dependency on the GPUCC bindings
Quoting Akhil P Oommen (2021-07-28 04:54:01)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 029723a..c88f366 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -592,6 +593,85 @@
>
On 7/29/2021 9:21 AM, Michal Wajdeczko wrote:
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. These
On Thu, Jul 29, 2021 at 9:18 AM Daniel Vetter wrote:
>
> On Thu, Jul 29, 2021 at 5:19 PM Rob Clark wrote:
> >
> > On Thu, Jul 29, 2021 at 12:03 AM Daniel Vetter wrote:
> > >
> > > On Wed, Jul 28, 2021 at 10:58:51AM -0700, Rob Clark wrote:
> > > > On Wed, Jul 28, 2021 at 10:23 AM Christian König
Quoting Akhil P Oommen (2021-07-28 04:54:02)
> From: Manaf Meethalavalappu Pallikunhi
>
> Add cooling-cells property and the cooling maps for the gpu thermal
> zones to support GPU thermal cooling.
>
> Signed-off-by: Manaf Meethalavalappu Pallikunhi
> Signed-off-by: Akhil P Oommen
> ---
Reviewe
On Thu, Jul 29, 2021 at 10:19 AM Stephen Boyd wrote:
>
> Quoting Akhil P Oommen (2021-07-28 04:54:01)
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 029723a..c88f366 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/ar
Quoting Rob Clark (2021-07-29 10:35:32)
> On Thu, Jul 29, 2021 at 10:19 AM Stephen Boyd wrote:
> >
> >
> > Why is 45000 after 55000? Is it on purpose? If not intended
> > please sort by frequency.
>
> We've used descending order, at least for gpu opp table, on other
> gens, fwiw.. not sure
From: Rob Clark
The more frequent frequency transitions resulting from clamping freq to
minimum when the GPU is idle seems to be causing some issue with the bus
getting voted off when it should be on. (An enable racing with an async
disable?) This might be a problem outside of the GPU, as I can
On 7/29/2021 9:26 PM, Rob Clark wrote:
On Thu, Jul 29, 2021 at 8:31 AM Akhil P Oommen wrote:
Introduce a feature flag in gpulist to easily identify the capabilities
of each gpu revision. This will help to avoid a lot of adreno_is_axxx()
check when we add new features. In the current patch, HW
Hi Sam,
Please help! I tried to push the first two patches to drm-misc-fixes using dim
push, but it pushed other things too besides these patches. I am sorry, don't
know what went wrong.
Anitha
> -Original Message-
> From: Sam Ravnborg
> Sent: Wednesday, July 28, 2021 12:05 AM
> To: Ch
Hi Gerd,
>
> On Thu, Jul 29, 2021 at 01:16:57AM -0700, Vivek Kasireddy wrote:
> > This feature enables the Guest to wait to know when a resource
> > is completely consumed by the Host.
>
> virtio spec update?
>
> What are the exact semantics?
[Kasireddy, Vivek] As of now, this is still a RFC ve
Hi Gerd,
>
> Hi,
>
> > + bool has_out_fence;
>
> > + if (virtio_has_feature(vgdev->vdev, VIRTIO_GPU_F_OUT_FENCE)) {
> > + vgdev->has_out_fence = true;
> > + vgdev->ddev->mode_config.deferred_out_fence = true;
>
> Looks like you don't need has_out_fence, you can just u
On 7/29/2021 10:46 PM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2021-07-28 00:17:45)
On 7/27/2021 5:46 AM, Stephen Boyd wrote:
Quoting Akhil P Oommen (2021-07-24 10:29:00)
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen
---
This patch has dependency on
On Tue, 27 Jul 2021 13:58:45 -0700 Kees Cook wrote:
> In preparation for FORTIFY_SOURCE performing compile-time and run-time
> field bounds checking for memset(), avoid intentionally writing across
> neighboring fields.
>
> Add struct_group() to mark region of struct rt6_info that should be
> init
Hi Anitha,
On Thu, Jul 29, 2021 at 06:48:45PM +, Chrisanthus, Anitha wrote:
> Hi Sam,
> Please help! I tried to push the first two patches to drm-misc-fixes using
> dim push, but it pushed other things too besides these patches. I am sorry,
> don't know what went wrong.
>
I see only these i
Remember before enjoying your holiday that the deadline for XDC 2022
proposals is *September 1st, 2021* :-)
Feel free to submit your proposal before, so we can give you early
feedback on it!
Sam
On Thu, 2021-07-01 at 18:14 +0200, Samuel Iglesias Gonsálvez wrote:
> This is a reminder that the cal
Quoting Akhil P Oommen (2021-07-29 11:57:23)
> On 7/29/2021 10:46 PM, Stephen Boyd wrote:
> > Quoting Akhil P Oommen (2021-07-28 00:17:45)
> >> On 7/27/2021 5:46 AM, Stephen Boyd wrote:
> >>> Quoting Akhil P Oommen (2021-07-24 10:29:00)
> Add the necessary dt nodes for gpu support in sc7280.
>
On Mon, Jul 19, 2021 at 06:10:09PM +0800, Xin Ji wrote:
> Add 'bus-type' and 'data-lanes' define for port0. Define DP tx lane0,
> lane1 swing register array define, and audio enable flag.
>
> The device which cannot pass DP tx PHY CTS caused by long PCB trace or
> embedded MUX, adjusting ANX7625 P
Hi
Am 28.07.21 um 22:11 schrieb Sam Ravnborg:
Hi Dan,
I think I got it - we need to set irq_enabled to true.
The documentation says so:
"
* @irq_enabled:
*
* Indicates that interrupt handling is enabled, specifically vblank
* handling. Drivers which
Hi
Am 29.07.21 um 21:18 schrieb Thomas Zimmermann:
Hi
Am 28.07.21 um 22:11 schrieb Sam Ravnborg:
Hi Dan,
I think I got it - we need to set irq_enabled to true.
The documentation says so:
"
* @irq_enabled:
*
* Indicates that interrupt handling is enabled,
sp
Hi
Am 29.07.21 um 21:24 schrieb dan.sned...@microchip.com:
Hi Thomas,
On 7/29/21 12:18 PM, Thomas Zimmermann wrote:
Hi
Am 28.07.21 um 22:11 schrieb Sam Ravnborg:
Hi Dan,
I think I got it - we need to set irq_enabled to true.
The documentation says so:
"
* @irq_enabled:
On Wed, Jul 28, 2021 at 09:45:51AM -0700, Douglas Anderson wrote:
>
> The overall goal of this series is to make the Samsung ATNA33XC20
> panel work more properly. As part of this, we have:
> * A bugfix for the recently abstracted DP AUX backlight code.
> * A bugfix for the sequencing of the ti-sn
Hi Thomas,
>
> Are you sure, you're testing with the latest drm-misc-next or drm-tip?
> Because using irq_enabled is deprecated and the flag was recently replaced
> by commit 1e4cd78ed493 ("drm: Don't test for IRQ support in VBLANK ioctls").
I was looking at drm-misc-fixes which did not have thi
This series adds support for the gpu found in the Snapdragon 7c Gen 3
compute platform. This gpu is similar to the exisiting a660 gpu with
minor delta in the programing sequence. As the Adreno GPUs are moving
away from a numeric chipid based naming scheme to a string, it was
decided to use 0x060305
Add the missing scache_cntl0 register programing which is required for
a660 gpu.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ---
1 file changed, 27 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/d
Use rev instead of revn to identify the SKU. This is in
preparation to the introduction of 7c3 gpu which won't have a
revn.
Signed-off-by: Akhil P Oommen
---
Changes in v4:
- Move adreno_cmp_rev() here to fix compilation
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +--
drivers/gpu/
This patch adds support for the gpu found in the Snapdragon 7c Gen 3
compute platform. This gpu is similar to the exisiting a660 gpu with
minor delta in the programing sequence. As the Adreno GPUs are moving
away from a numeric chipid based naming scheme to a string, it was
decided to use 0x0603050
On Wed, 21 Jul 2021 19:42:23 -0700, Bjorn Andersson wrote:
> reg was defined as one region covering the entire DP block, but the
> memory map is actually split in 4 regions and obviously the size of
> these regions differs between platforms.
>
> Switch the reg to require that all four regions are
Hi Rob,
I've done some more testing! It looks like before that patch ("drm/msm: Devfreq tuning") the GPU would never get above
the second frequency in the OPP table (342MHz) (at least, not in glxgears). With the patch applied it would more
aggressively jump up to the max frequency which seems t
On Thu, Jul 29, 2021 at 1:06 PM Caleb Connolly
wrote:
>
> Hi Rob,
>
> I've done some more testing! It looks like before that patch ("drm/msm:
> Devfreq tuning") the GPU would never get above
> the second frequency in the OPP table (342MHz) (at least, not in glxgears).
> With the patch applied it
On 15/07/2021 09:51, Vinod Koul wrote:
This add the bits in RM to enable the DSC blocks
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 32 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
3 fi
On Wed, Jul 21, 2021 at 11:56 AM Sean Paul wrote:
>
> From: Sean Paul
>
> This patch adds a new module parameter called drm.trace which accepts
> the same mask as drm.debug. When a debug category is enabled, log
> messages will be put in a new tracefs instance called drm for
> consumption.
>
> Us
On 15/07/2021 09:51, Vinod Koul wrote:
This add SDM845 DSC blocks into hw_catalog
Signed-off-by: Vinod Koul
---
Changes since RFC:
- use BIT values from MASK
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 22 +++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/
On Thu, Jul 22, 2021 at 05:21:39PM -0700, Douglas Anderson wrote:
> eDP panels generally contain almost everything needed to control them
> in their EDID. This comes from their DP heritage were a computer needs
> to be able to properly control pretty much any DP display that's
> plugged into it.
>
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Update the get/set min/max freq hooks to work for
> SLPC case as well. Consolidate helpers for requested/min/max
> frequency get/set to intel_rps where the proper action can
> be taken depending on whether SLPC is enabled.
>
> v2: Add wrappers for
On 29/07/2021 21:24, Rob Clark wrote:
On Thu, Jul 29, 2021 at 1:06 PM Caleb Connolly
wrote:
Hi Rob,
I've done some more testing! It looks like before that patch ("drm/msm: Devfreq
tuning") the GPU would never get above
the second frequency in the OPP table (342MHz) (at least, not in glxge
On Thu, Jul 29, 2021 at 2:24 PM wrote:
>
> On Wed, Jul 21, 2021 at 11:56 AM Sean Paul wrote:
> >
> > From: Sean Paul
> >
> > This patch adds a new module parameter called drm.trace which accepts
> > the same mask as drm.debug. When a debug category is enabled, log
> > messages will be put in a n
On Thu, Jul 29, 2021 at 08:17:44AM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/29/2021 4:10 AM, Rodrigo Vivi wrote:
> > On Wed, Jul 28, 2021 at 07:01:01PM -0700, Daniele Ceraolo Spurio wrote:
> > > This api allow user mode to create protected buffers and to mark
> > > contexts as making use o
On Wed, Jul 28, 2021 at 07:00:53PM -0700, Daniele Ceraolo Spurio wrote:
> From: Vitaly Lubart
>
> Export PAVP client to work with i915 driver,
> for binding it uses kernel component framework.
>
> v2:drop debug prints, refactor match code to match mei_hdcp (Tomas)
>
> Signed-off-by: Vitaly Luba
On Thu, Jul 29, 2021 at 1:28 PM Caleb Connolly
wrote:
>
>
>
> On 29/07/2021 21:24, Rob Clark wrote:
> > On Thu, Jul 29, 2021 at 1:06 PM Caleb Connolly
> > wrote:
> >>
> >> Hi Rob,
> >>
> >> I've done some more testing! It looks like before that patch ("drm/msm:
> >> Devfreq tuning") the GPU woul
On 15/07/2021 09:52, Vinod Koul wrote:
When DSC is enabled in DT, we need to configure the encoder for DSC
configuration, calculate DSC parameters for the given timing.
This patch adds that support by adding dpu_encoder_prep_dsc() which is
invoked when DSC is enabled in DT
Signed-off-by: Vinod
drm-misc-next-2021-07-29:
drm-misc-next for v5.15:
UAPI Changes:
- Add modifiers for arm fixed rate compression.
Cross-subsystem Changes:
- Assorted dt binding fixes.
- Convert ssd1307fb to json-schema.
- Update a lot of irc channels to point to OFTC, as everyone moved there.
- Fix the same divid
Hi,
On Thu, Jul 29, 2021 at 1:27 PM Rob Herring wrote:
>
> IMO, you should move any applicable compatibles to the edp-panel schema.
> Also, I don't think you should add 'edp-panel' to them. If they can work
> better with the generic eDP driver, then that should be an internal
> kernel change with
On 15/07/2021 09:52, Vinod Koul wrote:
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signed-of
On 15/07/2021 09:51, Vinod Koul wrote:
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff
On Mon, Jul 26, 2021 at 09:51:40AM +0200, Linus Walleij wrote:
> On Sun, Jul 25, 2021 at 4:04 PM Alexey Minnekhanov
> wrote:
>
> > The Samsung S6E3FA2 AMOLED cmd LCD panel is used on Samsung Galaxy
> > S5 (klte) phone.
> >
> > Signed-off-by: Alexey Minnekhanov
>
> Grr gmail put this in my spam
On Sun, 25 Jul 2021 17:03:37 +0300, Alexey Minnekhanov wrote:
> The Samsung S6E3FA2 AMOLED cmd LCD panel is used on Samsung Galaxy
> S5 (klte) phone.
>
> Signed-off-by: Alexey Minnekhanov
> ---
> .../display/panel/samsung,s6e3fa2.yaml| 63 +++
> 1 file changed, 63 inserti
Hi Thomas,
On 7/29/21 12:18 PM, Thomas Zimmermann wrote:
> Hi
>
> Am 28.07.21 um 22:11 schrieb Sam Ravnborg:
>> Hi Dan,
>>
I think I got it - we need to set irq_enabled to true.
The documentation says so:
"
* @irq_enabled:
*
* In
On Mon, 26 Jul 2021 10:32:59 -0700, Bjorn Andersson wrote:
> Add bindings for the two AUO panels B133HAN05 and B140HAN06, both
> 1920x1080 panels with 16.7M colors, first being 13.3" and the latter
> 14.0".
>
> Signed-off-by: Bjorn Andersson
> ---
> .../devicetree/bindings/display/panel/panel-si
On Wed, Jul 28, 2021 at 02:11:43PM -0700, Vinay Belgaumkar wrote:
> Tests that exercise the SLPC get/set frequency interfaces.
>
> Clamp_max will set max frequency to multiple levels and check
> that SLPC requests frequency lower than or equal to it.
>
> Clamp_min will set min frequency to differ
Hi Thomas and Sam,
On 7/29/21 12:48 PM, Sam Ravnborg wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Thomas,
>
>>
>> Are you sure, you're testing with the latest drm-misc-next or drm-tip?
>> Because using irq_enabled is deprecated and
On Sat, Jul 24, 2021 at 8:21 PM Bjorn Andersson
wrote:
>
> This patch adds a Adreno 680 entry to the gpulist.
Looks reasonable, but I wonder if we should just go ahead and add
adreno_is_a640_family() in a similar vein to
adreno_is_a650_familiy()/adreno_is_a660_family().. I think most of the
'if (
On 7/28/2021 17:34, Matthew Brost wrote:
If an engine associated with a context does not have a heartbeat, ban it
immediately. This is needed for GuC submission as a idle pulse doesn't
kick the context off the hardware where it then can check for a
heartbeat and ban the context.
It's worse than t
https://bugzilla.kernel.org/show_bug.cgi?id=213917
Bug ID: 213917
Summary: Screen starts flickering when laptop(amdgpu) wakes up
after suspend.
Product: Drivers
Version: 2.5
Kernel Version: 5.13.6
Hardware: x86-64
Hi Linus,
Regular drm fixes pull, seems about the right size, lots of small
fixes across the board, mostly amdgpu, but msm and i915 are in there
along with panel and ttm. There is an rc3 backmerge due to some
patches ending up in the gap between last and this week.
Dave.
drm-fixes-2021-07-30:
dr
On 7/29/2021 4:40 PM, Matthew Brost wrote:
On Wed, Jul 28, 2021 at 02:11:43PM -0700, Vinay Belgaumkar wrote:
Tests that exercise the SLPC get/set frequency interfaces.
Clamp_max will set max frequency to multiple levels and check
that SLPC requests frequency lower than or equal to it.
Clamp
On Wed, Jul 28, 2021 at 01:24:01PM +0200, Rasmus Villemoes wrote:
> On 28/07/2021 07.49, Greg Kroah-Hartman wrote:
> > On Tue, Jul 27, 2021 at 01:58:53PM -0700, Kees Cook wrote:
> >> In preparation for FORTIFY_SOURCE performing compile-time and run-time
> >> field bounds checking for memcpy(), memm
On Wed, Jul 28, 2021 at 07:49:46AM +0200, Greg Kroah-Hartman wrote:
> On Tue, Jul 27, 2021 at 01:58:53PM -0700, Kees Cook wrote:
> > In preparation for FORTIFY_SOURCE performing compile-time and run-time
> > field bounds checking for memcpy(), memmove(), and memset(), avoid
> > intentionally writin
Hi Vinay,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.14-rc3 next-20210729]
[If your patch is applied to the wrong git tree, kindly
This series enables Single Loop Power Control (SLPC) feature in GuC.
GuC implements various power management algorithms as part of it's
operation. These need to be specifically enabled by KMD. They replace
the legacy host based management of these features.
With this series, we will enable two PM
Add macros to check for SLPC support. This feature is currently supported
for Gen12+ and enabled whenever GuC submission is enabled/selected.
Include templates for SLPC init/fini and enable.
v2: Move SLPC helper functions to intel_guc_slpc.c/.h. Define
basic template for SLPC structure in intel_g
Also ensure uc_init is called before we initialize RPS so that we
can check for SLPC support. We do not need to enable up/down
interrupts when SLPC is enabled. However, we still need the ARAT
interrupt, which will be enabled separately later.
v2: Explicitly return from intel_rps_enable with slpc c
Add methods for interacting with GuC for enabling SLPC. Enable
SLPC after GuC submission has been established. GuC load will
fail if SLPC cannot be successfully initialized. Add various
helper methods to set/unset the parameters for SLPC. They can
be set using H2G calls or directly setting bits in
Add constants and params that are needed to configure SLPC.
v2: Add a new abi header for SLPC. Replace bitfields with
genmasks. Address other comments from Michal W.
v3: Add slpc H2G format in abi, other review commments (Michal W)
v4: Update status bits according to latest spec
v5: checkpatch(
Allocate data structures for SLPC and functions for
initializing on host side.
v2: Address review comments (Michal W)
v3: Remove unnecessary header includes (Michal W)
v4: Rebase
v5: Move allocation of shared data into slpc_init() (Michal W)
Reviewed-by: Michal Wajdeczko
Signed-off-by: Vinay Bel
The assumption when it was added was that GT would not be
holding any gt_pm references. However, uc_init is called
from gt_init_hw, which holds a forcewake ref. If SLPC
enable fails, we will still be holding this ref, which will
result in the BUG_ON.
Reviewed-by: Matthew Brost
Signed-off-by: Vina
Add param set h2g helpers to set the min and max frequencies
for use by SLPC.
v2: Address review comments (Michal W)
v3: Check for positive error code (Michal W)
v4: Print generic error in set_param (Michal W)
Reviewed-by: Michal Wajdeczko
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Vina
Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.
v2: Address review comments (Michal W)
v3: Formatting
This prints out relevant SLPC info from the SLPC shared structure.
We will send a H2G message which forces SLPC to update the
shared data structure with latest information before reading it.
v2: Address review comments (Michal W)
v3: Remove unnecessary tasks from slpc_info (Michal W)
v4: Rename f
Add helpers to read the min/max frequency being used
by SLPC. This is done by send a H2G command which forces
SLPC to update the shared data struct which can then be
read. These helpers will be used in a sysfs patch later
on.
v2: Address review comments (Michal W)
v3: Return err in case of query f
Update the get/set min/max freq hooks to work for
SLPC case as well. Consolidate helpers for requested/min/max
frequency get/set to intel_rps where the proper action can
be taken depending on whether SLPC is enabled.
v2: Add wrappers for getting rp0/1/n frequencies, update
softlimits in set min/ma
This feature hands over the control of HW RC6 to the GuC.
GuC decides when to put HW into RC6 based on it's internal
busyness algorithms.
GuCRC needs GuC submission to be enabled, and only
supported on Gen12+ for now.
When GuCRC is enabled, do not set HW RC6. Use a H2G message
to tell GuC to enab
This interrupt is enabled during RPS initialization, and
now needs to be done by SLPC code. It allows ARAT timer
expiry interrupts to get forwarded to GuC.
v2: Fix comment (Matthew Brost)
v3: checkpatch()
Reviewed-by: Matthew Brost
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc
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