On Mon, Jul 05, 2021 at 06:05:03PM +0800, Huacai Chen wrote:
> Currently, vga_arb_device_init() selects the first probed VGA device
> with VGA legacy resources enabled as the default device. However, some
> BMC-based VGA cards (e.g., AST2500 and HiSilicon D05) don't enable VGA
> legacy resources be
Remove old GuC stage descriptor, add LRC descriptor which will be used
by the new GuC interface implemented in this patch series.
v2:
(John Harrison)
- s/lrc/LRC/g
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h|
The first 18 patches [1] are basically ready to merge - only 3 are
missing RBs but all issues are mostly nits and have been address.
Hopefully by the time CI returns we can merge these.
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesktop.org/series/91840/
Matthew Brost (18):
drm/i
Add LRC descriptor context lookup array which can resolve the
intel_context from the LRC descriptor index. In addition to lookup, it
can determine if the LRC descriptor context is currently registered with
the GuC by checking if an entry for a descriptor index is present.
Future patches in the seri
Add new GuC interface defines and structures while maintaining old ones
in parallel.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 14 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 41 +++
Implement GuC submission tasklet for new interface. The new GuC
interface uses H2G to submit contexts to the GuC. Since H2G use a single
channel, a single tasklet is used for the submission path.
Also the per engine interrupt handler has been updated to disable the
rescheduling of the physical eng
Extend the deregistration context fence to fence whne a GuC context has
scheduling disable pending.
v2:
(John H)
- Update comment why we check the pin count within spin lock
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submi
Disable engine barriers for unpinning with GuC. This feature isn't
needed with the GuC as it disables context scheduling before unpinning
which guarantees the HW will not reference the context. Hence it is
not necessary to defer unpinning until a kernel context request
completes on each engine in t
Add bypass tasklet submission path to GuC. The tasklet is only used if H2G
channel has backpresure.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++
1 file changed, 29 insertions(+), 8 deletions(-)
diff --git a/
If two requests are on the same ring, they are explicitly ordered by the
HW. So, a submission fence is sufficient to ensure ordering when using
the new GuC submission interface. Conversely, if two requests share a
timeline and are on the same physical engine but different context this
doesn't ensur
Update GuC debugfs to support the new GuC structures.
v2:
(John Harrison)
- Remove intel_lrc_reg.h include from i915_debugfs.c
(Michal)
- Rename GuC debugfs functions
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/inte
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
- Remove C++ style comment
v3:
(Matthew Brost)
- Drop GUC_ID_START
(John Harrison)
- Fix
When running the GuC the GPU can't be considered idle if the GuC still
has contexts pinned. As such, a call has been added in
intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for
the number of unpinned contexts to go to zero.
v2: rtimeout -> remaining_timeout
v3: Drop unnecessa
Sometimes during context pinning a context with the same guc_id is
registered with the GuC. In this a case deregister must be done before
the context can be registered. A fence is inserted on all requests while
the deregister is in flight. Once the G2H is received indicating the
deregistration is c
Semaphores are an optimization and not required for basic GuC submission
to work properly. Disable until we have time to do the implementation to
enable semaphores and tune them for performance. Also long direction is
just to delete semaphores from the i915 so another reason to not enable
these for
With GuC scheduling, it isn't safe to unpin a context while scheduling
is enabled for that context as the GuC may touch some of the pinned
state (e.g. LRC). To ensure scheduling isn't enabled when an unpin is
done, a call back is added to intel_context_unpin when pin count == 1
to disable schedulin
Ensure G2H response has space in the buffer before sending H2G CTB as
the GuC can't handle any backpressure on the G2H interface.
v2:
(Matthew)
- s/INTEL_GUC_SEND/INTEL_GUC_CT_SEND
v3:
(Matthew)
- Add G2H credit accounting to blocking path, add g2h_release_space
helper
(John H)
- CTB_
Add trace point for GuC submit. Extended existing request trace points
to include submit fence value,, guc_id, and ring tail value.
v2: Fix white space alignment in i915_request_add trace point
v3: Delete dep_from , dep_to (Tvrtko)
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Joh
Disable preempt busywait when using GuC scheduling. This isn't needed as
the GuC controls preemption when scheduling.
v2:
(John H):
- Fix commit message
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 --
1 file
Add intel_context tracing. These trace points are particular helpful
when debugging the GuC firmware and can be enabled via
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS kernel config option.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_co
On Tue, Jul 20, 2021 at 1:55 PM Daniel Vetter wrote:
>
> On Tue, Jul 20, 2021 at 8:26 PM Rob Clark wrote:
> >
> > On Tue, Jul 20, 2021 at 11:03 AM Christian König
> > wrote:
> > >
> > > Hi Rob,
> > >
> > > Am 20.07.21 um 17:07 schrieb Rob Clark:
> > > > From: Rob Clark
> > > >
> > > > Somehow w
On Tue, Jul 20, 2021 at 04:01:27PM -0600, Alex Williamson wrote:
> On Tue, 20 Jul 2021 14:42:48 -0300
> Jason Gunthorpe wrote:
>
> > Compared to mbochs_remove() two cases are missing from the
> > vfio_register_group_dev() unwind. Add them in.
> >
> > Fixes: 681c1615f891 ("vfio/mbochs: Convert to
On Tue, 20 Jul 2021 19:49:55 -0300
Jason Gunthorpe wrote:
> On Tue, Jul 20, 2021 at 04:01:27PM -0600, Alex Williamson wrote:
> > On Tue, 20 Jul 2021 14:42:48 -0300
> > Jason Gunthorpe wrote:
> >
> > > Compared to mbochs_remove() two cases are missing from the
> > > vfio_register_group_dev() u
From: Maitreyee Rao
Add trace points across the MSM DP driver to help debug
interop issues.
Changes in v3:
- Got rid of redundant log messages.
- Unstuck colon from printf specifier in various places.
Signed-off-by: Maitreyee Rao
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 8 ++--
driver
On 7/10/2021 11:08 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
This prints out relevant SLPC info from the SLPC shared structure.
We will send a h2g message which forces SLPC to update the
shared data structure with latest information before reading it.
Signed
On 7/10/2021 11:15 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
Cache rp0, rp1 and rpn platform limits into slpc structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. Thes
gen8_clear_engine_error_register() is actually not used by
GRAPHICS_VER >= 8, since for those we are using another register that is
not engine-dependent. Fix the platform prefix, to make clear we are not
using any GEN6_RING_FAULT_REG_* one GRAPHICS_VER >= 8.
Signed-off-by: Lucas De Marchi
---
dr
The engine hw_id is only used by RING_FAULT_REG(), which is not used
since GRAPHICS_VER == 8. We tend to keep adding new defines just to be
consistent, but let's try to remove them and let them defined to 0 when
not used.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_engine_cs
We kept adding new engines and for that increasing hw_id unnecessarily:
it's not used since GRAPHICS_VER == 8. Prepend "gen6" to the field and
try to pack it in the structs to give a hint this field is actually not
used in recent platforms.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915
On 7/10/2021 11:20 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
Update the get/set min/max freq hooks to work for
slpc case as well. Consolidate helpers for requested/min/max
frequency get/set to intel_rps where the proper action can
be taken depending on whether
Motivated by my review in
https://patchwork.freedesktop.org/patch/443857/?series=92135&rev=5 I
went to look why we needed the additional hw_id fields. It turns out we
don't, but we kept adding new IDs to keep it consistent. Now that with
the extra media engines we would just leave than zero'ed, let
This is only used by GRAPHICS_VER == 6 and GRAPHICS_VER == 7. All other
recent platforms do not depend on this field, so it doesn't make much
sense to keep it generic like that. Instead, just do a mapping from
engine class to HW ID in the single place that is needed.
Signed-off-by: Lucas De Marchi
On 7/20/2021 15:39, Matthew Brost wrote:
Implement GuC submission tasklet for new interface. The new GuC
interface uses H2G to submit contexts to the GuC. Since H2G use a single
channel, a single tasklet is used for the submission path.
Also the per engine interrupt handler has been updated to d
On 7/10/2021 11:29 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
Tests that exercise the slpc get/set frequency interfaces.
Clamp_max will set max frequency to multiple levels and check
that slpc requests frequency lower than or equal to it.
Clamp_min will set m
On 7/10/2021 11:41 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
This feature hands over the control of HW RC6 to the GUC.
GUC decides when to put HW into RC6 based on it's internal
busyness algorithms.
GUCRC needs GUC submission to be enabled, and only
supported
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/nouveau/dispnv50/headc57d.c:173:1: warning: no previous
prototype for ‘headc57d_olut’ [-Wmissing-prototypes]
headc57d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
And no header file define a prototype for thi
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/nouveau/nouveau_bo.c: In function ‘nouveau_ttm_tt_populate’:
drivers/gpu/drm/nouveau/nouveau_bo.c:1245:17: warning: variable ‘dev’ set but
not used [-Wunused-but-set-variable]
struct device *dev;
^~~
drivers/gpu/d
On 7/20/2021 15:39, Matthew Brost wrote:
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
- Remove C++ style comment
v3:
(Matthew Brost
On 2021.07.16 18:41:38 +0800, Xiyu Yang wrote:
> refcount_t type and corresponding API can protect refcounters from
> accidental underflow and overflow and further use-after-free situations
>
Thanks for the patch. Is there any specific problem you run with current code?
Any shadow ppgtt error?
>
On Fri, 16 Jul 2021 at 21:07, Maarten Lankhorst
wrote:
>
> Hi Dave & Daniel,
>
> Lots of stuff this time around.
>
> Enjoy!
I've pulled this but there is an outstanding warning
/home/airlied/devel/kernel/dim/src/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c:
In function ‘hibmc_unload’:
/home/a
On 21/7/21 2:24 am, Daniel Vetter wrote:
On Mon, Jul 12, 2021 at 12:35:03PM +0800, Desmond Cheong Zhi Xi wrote:
Hi,
In the previous thread on this series we decided to remove a patch that was
violating a lockdep requirement in drm_lease. In addition to this change, I
took a closer look at the
Hello Thomas,
On 7/20/21 8:38 PM, Thomas Zimmermann wrote:
> Am 20.07.21 um 15:59 schrieb Daniel Vetter:
>> On Tue, Jul 20, 2021 at 03:42:45PM +0200, Javier Martinez Canillas wrote:
>>> On 7/20/21 3:01 PM, Daniel Vetter wrote:
On Mon, Jul 19, 2021 at 09:10:52AM +0200, Ard Biesheuvel wrote:
>>
Quoting maitreye (2021-07-20 15:39:30)
> diff --git a/drivers/gpu/drm/msm/dp/dp_link.c
> b/drivers/gpu/drm/msm/dp/dp_link.c
> index be986da..316e8e6 100644
> --- a/drivers/gpu/drm/msm/dp/dp_link.c
> +++ b/drivers/gpu/drm/msm/dp/dp_link.c
> @@ -1036,43 +1036,46 @@ int dp_link_process_request(struct
Am 20.07.21 um 20:13 schrieb Jason Ekstrand:
If we have a failure, decrement the reference count so that the next
call to ttm_global_init() will actually do something instead of assume
everything is all set up.
Signed-off-by: Jason Ekstrand
Fixes: 62b53b37e4b1 ("drm/ttm: use a static ttm_bo_glo
It's not obvious what the fields mean and how they should be used.
The most important detail is the link to drm_property.flags, which
describes how property types work.
Signed-off-by: Simon Ser
Cc: Pekka Paalanen
Cc: Daniel Vetter
Cc: Leandro Ribeiro
---
include/uapi/drm/drm_mode.h | 52 +
When a property has the type DRM_MODE_PROP_BITMASK, the value field
stores a bitshift, not a bitmask, which can be surprising.
Signed-off-by: Simon Ser
Cc: Pekka Paalanen
Cc: Daniel Vetter
Cc: Leandro Ribeiro
---
include/drm/drm_property.h | 5 +
1 file changed, 5 insertions(+)
diff --gi
201 - 246 of 246 matches
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