On 03/07/2021 14:32, Kalyan Thota wrote:
This change adds support for inline rotation in the dpu driver.
When inline rotation is enabled the VIG pipes will directly fetch the image
from memory in a rotated fashion
Inline rotation has following restrictions
1) Supported only with compressed forma
This series supports common bridge support for Samsung MIPI DSIM
which is used in Exynos and i.MX8MM SoC's.
The final bridge supports both the Exynos and i.MX8MM DSI devices.
Right now bridge offers two sets of implementations.
A. With component_ops and exynos specific code exclusively for
ex
DRM bridge drivers have built-in handling of treating
all display pipeline components as bridges.
Convert exynos_drm_dsi to a bridge driver with built-in
encoder support for compatibility with existing component
drivers.
This keeps switching the driver into the bridge in a more
feasible manner.
Now the exynos dsi driver supports bridge and legacy
encoder.
In order to support drm_device in both the implementations
it is required to preserve the drm_device in a private
structure and use it accordingly.
1. encoder case, the bind will assign the drm_device into
encoder->dev, so preserve
Use drm_panel_bridge to replace manual panel and
bridge_chain handling code.
This makes the driver simpler to allow all components
in the display pipeline to be treated as bridges by
cleaning the way to generic connector handling.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/exynos/exynos_drm_
Use drm_bridge_connector_init to create a connector
for display pipelines that use drm_bridge for encoder
implementation.
This allows splitting connector operations across
multiple bridges when necessary, instead of having
the last bridge in the chain creating the connector
and handling all connec
Now the exynos dsi driver is fully aware of bridge
handling, so get the display mode from bridge, mode_set
API instead of legacy encoder crtc.
This makes bridge usage more efficient instead of relying
on encoder stack.
Add mode_set in drm_bridge_funcs.
Signed-off-by: Jagan Teki
---
drivers/gpu
Exynos DSI driver is actually a Samsung MIPI DSIM bridge
IP which is also used in i.MX8MM platforms.
Right now the existing driver has some exynos drm specific
code bases like te_irq, crtc and component_ops.
In order to switch this driver into a common bridge driver
We can see 2 options to handle
The MIPI DSI IP used in Exynos and i.MX8MM are based
Samsung MIPI DSIM bridge.
In order to access the common bridge between platforms
the ideal way to push the driver into the bridge area.
So, this patch will move the exynos_drm_dsi.c driver
into samsung-dsim.c and do the necessary function
Samsing MIPI DSIM bridge can be found on Exynos and NXP's
i.MX8M Mini and Nano SoC's.
This dt-bindings replaces legacy exynos_dsim.txt.
Used the example node from latest Exynos SoC instead of
the one used in legacy exynos_dsim.txt.
Add dt-bingings for it.
Cc: Rob Herring
Signed-off-by: Jagan T
Add module init and exit functions for the bridge to
register and unregister dsi_driver.
Exynos drm driver stack will register the platform_driver
separately in the common of it's exynos_drm_drv.c including
dsi_driver. Register again would return -EBUSY, so return 0
for such cases as dsi_driver is
Existing bridge driver is able to find the panel or bridge
if of_node isn't a port(s). This is how the exynos dsi
node handling has been done so far.
However in order to make use of this bridge in other or
new supported platforms like i.MX8MM it is required to
have a port based of_node.
So, this
Finding panel_or_bridge might vary based on associated
DSI device drivers like DSI panel, bridge, and I2C based
DSI bridge.
All of these DSI drivers will invoke the DSI host in order
to find the panel_or_bridge from probe to host attach and
bridge_attach to host bridge attach.
So, in order to han
Samsung MIPI DSIM bridge can also be found in i.MX8MM SoC.
Add dt-bingings for it.
Cc: Rob Herring
Signed-off-by: Jagan Teki
---
.../display/bridge/samsung,mipi-dsim.yaml | 84 ++-
1 file changed, 83 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindi
Samsung MIPI DSIM bridge can also be found in i.MX8MM SoC.
Add compatible and associated driver_data it.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/bridge/samsung-dsim.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c
b/
eLCDIF is expecting to have input_bus_flags as DE_LOW
in order to set active low during valid data transfer
on each horizontal line.
Add DE_LOW flag via drm bridge timings.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/bridge/samsung-dsim.c | 5 +
1 file changed, 5 insertions(+)
diff --git
Host transfer in DSI master will invoke only when the DSI
commands sent from DSI devices like DSI Panel or DSI bridges
and this host transfer wouldn't invoke I2C based DSI
bridge drivers.
Handling DSI host initialization in transfer calls might miss
the controller setup for I2C based DSI bridges.
PMS_P offset value in existing driver is not compatible
with i.MX8MM.
However the i.MX8M Mini Application Reference manual shows
the PMS_P offset is the same in the driver, but the i.MX8MM
downstream driver uses a different one.
So, handle the PMS_P offset via driver_data and use the
offset value
Fixing up the mode flags are required in order to correlate
the correct sync flags in i.MX8MM eLCDIF.
So, handle the mode flags via bridge, mode_fixup.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/bridge/samsung-dsim.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gp
nwl_dsi_plat_clk_config structure added in below commit but not
used anywhere in the driver.
commit <44cfc6233447c> ("drm/bridge: Add NWL MIPI DSI host controller
support")
Drop it.
Cc: Guido Günther
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/bridge/nwl-dsi.c | 6 --
1 file changed, 6
24-bit SPWG, JEIDA bus formats are considered as 24-bit
bus widths for LCDC_CTRL register in mxsfb.
Add support for it.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/mxsfb/mxsfb_kms.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c
b/drivers/gpu/drm/mxsf
On 7/4/21 11:38 AM, Jagan Teki wrote:
24-bit SPWG, JEIDA bus formats are considered as 24-bit
bus widths for LCDC_CTRL register in mxsfb.
Add support for it.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/mxsfb/mxsfb_kms.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm
Hi Marek,
On Sun, Jul 4, 2021 at 3:23 PM Marek Vasut wrote:
>
> On 7/4/21 11:38 AM, Jagan Teki wrote:
> > 24-bit SPWG, JEIDA bus formats are considered as 24-bit
> > bus widths for LCDC_CTRL register in mxsfb.
> >
> > Add support for it.
> >
> > Signed-off-by: Jagan Teki
> > ---
> > drivers/gp
Hi,
On Sun, Jul 04, 2021 at 03:04:33PM +0530, Jagan Teki wrote:
> nwl_dsi_plat_clk_config structure added in below commit but not
> used anywhere in the driver.
>
> commit <44cfc6233447c> ("drm/bridge: Add NWL MIPI DSI host controller
> support")
>
> Drop it.
Reviewed-by: Guido Günther
Cheers,
Hi,
Something is wrong with the threading, since this patch does not contain
In-Reply-To header pointing to the cover letter? Could you please
correct that? Using git-send-email --compose would allow you to write
properly threaded cover letter.
On 03/07/2021 14:32, Kalyan Thota wrote:
Add i
On 7/4/21 11:57 AM, Jagan Teki wrote:
Hi Marek,
On Sun, Jul 4, 2021 at 3:23 PM Marek Vasut wrote:
On 7/4/21 11:38 AM, Jagan Teki wrote:
24-bit SPWG, JEIDA bus formats are considered as 24-bit
bus widths for LCDC_CTRL register in mxsfb.
Add support for it.
Signed-off-by: Jagan Teki
---
On 03/07/2021 14:32, Kalyan Thota wrote:
Add inline rotation support in dpu driver. This change adds
rotation config for SC7280 target.
Change-Id: I15861dc03422274ffd823fc0fc2c1e47909bb22c
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 47 +
driv
Hi,
I've had splash screen disabled on my RB3. However once I've enabled it,
I've got the attached crash during the boot on the msm/msm-next. It
looks like it is related to this particular set of changes.
On 11/06/2021 00:44, Rob Clark wrote:
From: Rob Clark
This picks up an earlier series
As dw-mipi-dsi supported all possible ways to find the DSI
devices. It can take multiple iterations for ltdc to find
all components attached to the DSI bridge.
The current ltdc driver failed to find the endpoint as
it returned -EINVAL for the first iteration itself. This leads
to following error:
Finding panel_or_bridge might vary based on associated
DSI devices like DSI panel, bridge, and I2C based DSI
bridge.
1. DSI panels and bridges will invoke the host attach
from probe in order to find the panel_or_bridge.
chipone_probe()
dw_mipi_dsi_host_attach().start
dw_mi
Series is,
Reviewed-by: Luben Tuikov
Regards,
Luben
On 2021-07-03 5:44 a.m., Dan Carpenter wrote:
> If amdgpu_eeprom_read() returns a negative error code then the error
> handling checks:
>
> if (res < buf_size) {
>
> The problem is that "buf_size" is a u32 so negative values are type
> pr
On Sun, Jul 4, 2021 at 1:25 AM Dmitry Baryshkov
wrote:
>
> On 03/07/2021 14:32, Kalyan Thota wrote:
> > This change adds support for inline rotation in the dpu driver.
> > When inline rotation is enabled the VIG pipes will directly fetch the image
> > from memory in a rotated fashion
> >
> > Inlin
I suspect you are getting a dpu fault, and need:
https://lore.kernel.org/linux-arm-msm/CAF6AEGvTjTUQXqom-xhdh456tdLscbVFPQ+iud1H1gHc8A2=h...@mail.gmail.com/
I suppose Bjorn was expecting me to send that patch
BR,
-R
On Sun, Jul 4, 2021 at 5:53 AM Dmitry Baryshkov
wrote:
>
> Hi,
>
> I've had sp
dpu_hw_ctl_clear_all_blendstages() clears settings for the few first LMs
instead of mixers actually used for the CTL. Change it to clear
necessary data, using provided mixer ids.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/
As discussed on IRC, change dpu_plane implementation to be virtual:
register unified planes and select backing SSPP block at runtime.
Use msm.dpu_use_virtual_planes=1 to enable usage of virtual planes
rather than statically allocated SSPPs at the plane registration.
Patches 1-9 move state variabl
LUT levels are setup outside of setup_qos_ctrl, so remove them from the
struct dpu_hw_pipe_qos_cfg.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 15 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 ++--
drivers/gpu/drm/msm/disp/dp
The pipe_qos_cfg is used only in _dpu_plane_set_qos_ctrl(), so remove it
from the dpu_plane struct and allocate it on stack when necessary.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 30 ---
1 file changed, 16 insertions(+), 14 deletions(-
Use plane->name instead of artificial pipe_name.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index
Master/virtual planes were used for multirect support. In preparation to
reworking DPU planes, drop support for master planes (which was not used
anyway).
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 11 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 3 +
struct dpu_hw_pipe_cfg represents an interim state during atomic
update/color fill, so move it out of struct dpu_plane.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 97 ---
1 file changed, 52 insertions(+), 45 deletions(-)
diff --git a/driv
The stage_cfg is not used outside of _dpu_crtc_blend_setup(), so remove
the temporary config from global struct.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 --
2 files changed, 6 insertions(+), 7 de
Scaler and pixel_ext configuration does not contain a long living state,
it is used only during plane update, so remove these two fiels from
dpu_plane_state and allocate them on stack.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 59 ++-
dri
Remove struct dpu_hw_pipe_cdp_cfg instance from dpu_plane, it is an
interim configuration structure. Allocate it on stack instead.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 14 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 --
2 files changed
Do not cache hw_pipe's sblk in dpu_plane. Use
pdpu->pipe_hw->cap->sblk directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 21 ++---
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/d
Simplify code surrounding CSC table setup by removing struct dpu_csc_cfg
pointer from dpu_plane and getting it directly at the CSC setup time.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 +-
drivers/gpu
In preparations of virtualizing the dpu_plane rip out debugfs support
from dpu_plane (as it is mostly used to expose plane's pipe registers).
Also move disable_danger file to danger/ debugfs subdir where it belongs.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |
As we are going to add virtual planes, add the list of supported formats
to the hw catalog entry. It will be used to setup universal planes, with
later selecting a pipe depending on whether the YUV format is used for
the framebuffer.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/d
Neither source split nor multirect are properly supported at this
moment. Both of these checks depend on zpos being equal for several
planes (which is a clear userspace bug). Drop these checks to simplify
dpu_crtc_atomic_check(). The actual support for either of these features
is not removed from t
Add support for handling and allocting SSPP blocks through the resource
manager. Handling code is not converted to use it though.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 10 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp
In preparation to adding fully virtualized planes, move struct
dpu_hw_pipe instance from struct dpu_plane to struct dpu_plane_state, as
it will become a part of state (allocated during atomic check) rather
than part of a plane (allocated during boot).
Signed-off-by: Dmitry Baryshkov
---
drivers/
Downstream driver uses dpu->caps->smart_dma_rev to update
sspp->cap->features with the bit corresponding to the supported SmartDMA
version. Upstream driver does not do this, resulting in SSPP subdriver
not enbaling setup_multirect callback. Make SSPP subdriver check global
smart_dma_rev to decide i
Stop limiting zpos property values, we use normalized_zpos anyway. And
nothing stops userspace from assigning several planes to a single zpos
(it is a userspace bug, but the kernel is forgiving about it).
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 11 +---
Client driven prefetch (CDP) is properly setup only for SSPP REC0
currently. Enable client driven prefetch also for SSPP REC1.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 12 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +++-
drivers/gpu/drm
If SmartDMA is supported by the hardware, SSPPs allow using two RGB
layers per the hardware pipe (with some additional restrictions, like no
support for scaling, etc). Register additional planes (two per the SSPP)
and check if we can use multirect during atomic_check.
Signed-off-by: Dmitry Baryshk
Do not cache hw_pipe's features in dpu_plane. Use
pdpu->pipe_hw->cap->features directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/dri
Add support for registering unified (virtualized) planes, allowing SSPP
block to be allocated at runtime, during atomic_check. This allows
userspace app to use any plane without caring if it supports scaler or
YUV formats. All planes are marked as supporting all formats and scaler
options. The kern
Add DPU_SSPP_CSC_ANY denoting any CSC block. As we are at it, rewrite
DPU_SSPP_SCALER (any scaler) to use BIT(x) instead of hand-coded
bitshifts.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |
Add the missing unlock before return from function
amdgpu_ras_debugfs_table_read() in the error handling
case.
Fixes: 9b790694a031 ("drm/amdgpu: RAS EEPROM table is now in debugfs")
Reported-by: Hulk Robot
Signed-off-by: Yang Yingliang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 6
On 3/7/21 3:07 am, Daniel Vetter wrote:
On Fri, Jul 02, 2021 at 12:53:53AM +0800, Desmond Cheong Zhi Xi wrote:
This patch series addresses potential use-after-free errors when dereferencing
pointers to struct drm_master. These were identified after one such bug was
caught by Syzbot in drm_getu
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