On Fri, 11 Jun 2021 18:35:16 -0300
Leandro Ribeiro wrote:
> Add a small description and document struct fields of
> drm_mode_get_plane.
>
> Signed-off-by: Leandro Ribeiro
Hi,
my
Reviewed-by: Pekka Paalanen
still stands as mentioned earlier.
Thanks,
pq
> ---
> include/uapi/drm/drm_mode.
On Mon, Jun 14, 2021 at 01:30:34AM +0200, Alexander Sverdlin wrote:
> Nikita posted a patch converting EP93xx to use Common Clock Framework. It
> turns out some cleanup is necessary in the EP93xx drivers to avoid
> "Enabling unprepared" clock warnings.
>
> Patches with stack traces in the commit m
Hi
Am 14.06.21 um 08:46 schrieb Joonas Lahtinen:
Quoting Thomas Zimmermann (2021-06-13 21:54:03)
Hi Joonas
Am 11.06.21 um 13:13 schrieb Joonas Lahtinen:
Quoting Joonas Lahtinen (2021-06-11 13:40:56)
Quoting Maarten Lankhorst (2021-06-11 12:27:15)
Pull request for drm-misc-next and drm-intel
Pushed to drm-misc-next, thanks!
On Monday, June 14, 2021, Alexander Sverdlin
wrote:
> Nikita posted a patch converting EP93xx to use Common Clock Framework. It
> turns out some cleanup is necessary in the EP93xx drivers to avoid
> "Enabling unprepared" clock warnings.
>
> Patches with stack traces in the commit messages are tes
Am 11.06.21 um 17:18 schrieb Daniel Vetter:
On Fri, Jun 11, 2021 at 12:09:19PM +0200, Christian König wrote:
Am 11.06.21 um 11:07 schrieb Daniel Vetter:
On Thu, Jun 10, 2021 at 11:17:59AM +0200, Christian König wrote:
Unwrap a the explicit fence if it is a dma_fence_chain and
sync to the first
Nikita posted a patch converting EP93xx to use Common Clock Framework. It
turns out some cleanup is necessary in the EP93xx drivers to avoid
"Enabling unprepared" clock warnings.
Patches with stack traces in the commit messages are tested on EP9302.
Link: https://lore.kernel.org/patchwork/patch/1
Use clk_prepare_enable()/clk_disable_unprepare() in preparation for switch
to Common Clock Framework.
Signed-off-by: Alexander Sverdlin
---
drivers/video/fbdev/ep93xx-fb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fbdev/ep93xx-fb.c b/drivers/video/fbde
https://bugzilla.kernel.org/show_bug.cgi?id=213391
--- Comment #13 from Nirmoy (nirmoy.ai...@gmail.com) ---
Hi Dimitris and Lahfa, please try Michel's suggestion.
--
You may reply to this email to add a comment.
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On Fri, Jun 11, 2021 at 04:54:32AM -0400, Rodrigo Vivi wrote:
> On Fri, Jun 11, 2021 at 08:09:00AM +0200, Zbigniew Kempczyński wrote:
> > On Thu, Jun 10, 2021 at 10:36:12AM -0400, Rodrigo Vivi wrote:
> > > On Thu, Jun 10, 2021 at 12:39:55PM +0200, Zbigniew Kempczyński wrote:
> > > > We have establi
From: Tvrtko Ursulin
A little bit of documentation covering the topics of engine discovery,
context engine maps and virtual engines. It is not very detailed but
supposed to be a starting point of giving a brief high level overview of
general principles and intended use cases.
v2:
* Have the tex
Purely for CI so we can get some pre-merge results for DG1. This is
especially useful for cross driver TTM changes where CI can hopefully
catch regressions. This is similar to how we already handle the DG1
specific uAPI, which are also hidden behind CONFIG_BROKEN.
Signed-off-by: Matthew Auld
Cc:
On 6/14/21 11:22 AM, Matthew Auld wrote:
Purely for CI so we can get some pre-merge results for DG1. This is
especially useful for cross driver TTM changes where CI can hopefully
catch regressions. This is similar to how we already handle the DG1
specific uAPI, which are also hidden behind CONF
Quoting Joonas Lahtinen (2021-06-11 14:13:02)
> Quoting Joonas Lahtinen (2021-06-11 13:40:56)
> > Quoting Maarten Lankhorst (2021-06-11 12:27:15)
> > > Pull request for drm-misc-next and drm-intel-gt-next.
> > >
> > > topic/i915-ttm-2021-06-11:
> > > drm-misc and drm-intel pull request for topic/i
Op 14-06-2021 om 11:22 schreef Matthew Auld:
> Purely for CI so we can get some pre-merge results for DG1. This is
> especially useful for cross driver TTM changes where CI can hopefully
> catch regressions. This is similar to how we already handle the DG1
> specific uAPI, which are also hidden beh
Early implementation of moving system memory for discrete cards over to
TTM. We first add the notion of objects being migratable under the object
lock to i915 gem, and add some asserts to verify that objects are either
locked or pinned when the placement is checked by the gem code.
Patch 2 and 3 d
The object ops i915_GEM_OBJECT_HAS_IOMEM and the object
I915_BO_ALLOC_STRUCT_PAGE flags are considered immutable by
much of our code. Introduce a new mem_flags member to hold these
and make sure checks for these flags being set are either done
under the object lock or with pages properly pinned. Th
After a TTM move or object init we need to update the i915 gem flags and
caching settings to reflect the new placement. Currently caching settings
are not changed during the lifetime of an object, although that might
change moving forward if we run into performance issues or issues with
WC system p
Instead of relying on a static placement, calculate at get_pages() time.
This should work for LMEM regions and system for now. For stolen we need
to take preallocated range into account. That will if needed be added
later.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2:
- Fixed
For discrete, use TTM for both cached and WC system memory. That means
we currently rely on the TTM memory accounting / shrinker. For cached
system memory we should consider remaining shmem-backed, which can be
implemented from our ttm_tt_populate callback. We can then also reuse our
own very elabo
Hi Xin,
Thank you for the patch.
On Fri, Jun 11, 2021 at 05:13:33PM +0800, Xin Ji wrote:
> Add MIPI rx DPI input feature support.
Could you expand the commit message to explain what this feature is ?
> Reviewed-by: Robert Foss
> Signed-off-by: Xin Ji
> ---
> drivers/gpu/drm/bridge/analogix/a
On Mon, 14 Jun 2021 at 10:53, Thomas Hellström
wrote:
>
> After a TTM move or object init we need to update the i915 gem flags and
> caching settings to reflect the new placement. Currently caching settings
> are not changed during the lifetime of an object, although that might
> change moving for
On 6/14/21 12:20 PM, Matthew Auld wrote:
On Mon, 14 Jun 2021 at 10:53, Thomas Hellström
wrote:
After a TTM move or object init we need to update the i915 gem flags and
caching settings to reflect the new placement. Currently caching settings
are not changed during the lifetime of an object, a
If nvkm_object_init() fails then we should not call nvkm_object_fini()
because it results in calling object->func->fini(object, suspend) twice.
Once inside the nvkm_object_init() function and once inside the
nvkm_object_fini() function.
Fixes: fbd58ebda9c8 ("drm/nouveau/object: merge with handle")
On Mon, 14 Jun 2021 at 11:32, Thomas Hellström
wrote:
>
>
> On 6/14/21 12:20 PM, Matthew Auld wrote:
> > On Mon, 14 Jun 2021 at 10:53, Thomas Hellström
> > wrote:
> >> After a TTM move or object init we need to update the i915 gem flags and
> >> caching settings to reflect the new placement. Curr
Den 11.06.2021 23.27, skrev Linus Walleij:
> Implement SPI reads for typec1, for SPI controllers that
> can support 9bpw in addition to 8bpw (such as GPIO bit-banged
> SPI).
>
> 9bpw emulation is not supported but we have to start with
> something.
>
> This is used by s6e63m0 to read display M
AGP for example doesn't have a dma_address array.
Signed-off-by: Christian König
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 3e09df0472ce..170ab
On Mon, Jun 14, 2021 at 01:43:27PM +0300, Dan Carpenter wrote:
> If nvkm_object_init() fails then we should not call nvkm_object_fini()
> because it results in calling object->func->fini(object, suspend) twice.
> Once inside the nvkm_object_init() function and once inside the
> nvkm_object_fini() f
Am 11.06.21 um 20:23 schrieb Ondrej Zary:
On Friday 11 June 2021 14:38:18 Christian König wrote:
Am 10.06.21 um 19:59 schrieb Christian König:
Am 10.06.21 um 19:50 schrieb Ondrej Zary:
[SNIP]
I can't see how this is called from the nouveau code, only
possibility I
see is that it is maybe c
Den 11.06.2021 23.42, skrev Linus Walleij:
> The SPI access to s6e63m0 is using the DBI protocol, so switch
> to using the elaborate DBI protocol implementation in the DRM
> DBI helper library.
>
> Cc: Douglas Anderson
> Cc: Noralf Trønnes
> Signed-off-by: Linus Walleij
> ---
> diff --git a
On 6/14/21 12:49 PM, Matthew Auld wrote:
On Mon, 14 Jun 2021 at 11:32, Thomas Hellström
wrote:
On 6/14/21 12:20 PM, Matthew Auld wrote:
On Mon, 14 Jun 2021 at 10:53, Thomas Hellström
wrote:
After a TTM move or object init we need to update the i915 gem flags and
caching settings to reflec
On Tue, 2021-06-08 at 13:15 +0200, Juan A. Suarez Romero wrote:
> The V3D engine has several hardware performance counters that can of
> interest for userspace performance analysis tools.
>
> This exposes new ioctls to create and destroy performance monitor
> objects, as well as to query the count
Early implementation of moving system memory for discrete cards over to
TTM. We first add the notion of objects being migratable under the object
lock to i915 gem, and add some asserts to verify that objects are either
locked or pinned when the placement is checked by the gem code.
Patch 2 and 3 d
The object ops i915_GEM_OBJECT_HAS_IOMEM and the object
I915_BO_ALLOC_STRUCT_PAGE flags are considered immutable by
much of our code. Introduce a new mem_flags member to hold these
and make sure checks for these flags being set are either done
under the object lock or with pages properly pinned. Th
After a TTM move or object init we need to update the i915 gem flags and
caching settings to reflect the new placement. Currently caching settings
are not changed during the lifetime of an object, although that might
change moving forward if we run into performance issues or issues with
WC system p
Instead of relying on a static placement, calculate at get_pages() time.
This should work for LMEM regions and system for now. For stolen we need
to take preallocated range into account. That will if needed be added
later.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2:
- Fixed
For discrete, use TTM for both cached and WC system memory. That means
we currently rely on the TTM memory accounting / shrinker. For cached
system memory we should consider remaining shmem-backed, which can be
implemented from our ttm_tt_populate callback. We can then also reuse our
own very elabo
From: Tvrtko Ursulin
When a non-persistent context exits we currently mark it as banned in
order to trigger fast termination of any outstanding GPU jobs it may have
left running.
In doing so we apply a very strict 1ms limit in which the left over job
has to preempt before we issues an engine res
On Fri, Jun 11, 2021 at 02:40:41PM +0200, Cornelia Huck wrote:
> On Mon, Jun 07 2021, Jason Gunthorpe wrote:
>
> > For some reason the vfio_mdev shim mdev_driver has its own module and
> > kconfig. As the next patch requires access to it from mdev.ko merge the
> > two modules together and remove
On Mon, 14 Jun 2021 at 12:54, Thomas Hellström
wrote:
>
> After a TTM move or object init we need to update the i915 gem flags and
> caching settings to reflect the new placement. Currently caching settings
> are not changed during the lifetime of an object, although that might
> change moving for
On Wed, 2021-06-09 at 09:46 +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 09.06.21 um 04:49 schrieb Pu Lehui:
> > Fixes gcc '-Wunused-const-variable' warning:
> > drivers/gpu/drm/hyperv/hyperv_drm_modeset.c:152:23: warning:
> > 'hyperv_modifiers' defined but not used [-Wunused-const-
> > var
On Fri, 11 Jun 2021 07:54:07 +0200
Maxime Ripard wrote:
> Hi,
>
> On Thu, Jun 10, 2021 at 11:00:05PM +0200, Daniel Vetter wrote:
> > On Thu, Jun 10, 2021 at 7:47 PM Maxime Ripard wrote:
> > >
> > > New KMS properties come with a bunch of requirements to avoid each
> > > driver from running th
On Mon, Jun 14, 2021 at 08:04:03PM +0530, Kirti Wankhede wrote:
> Jason,
>
> I couldn't find patch 1,2,4 and 5 of these series. Can you please keep
> k...@vger.kernel.org cc for all patches?
It is an error, sorry
> Also it will be helpful if you can add version prefix, eg. 'v3' for this
> series
hmm I see, thanks for the heads up, I'll double check why it uses
google email for sending.
wrt the assignment in the if clauses, are those typically frowned upon?
Thanks!
On Fri, Jun 11, 2021 at 4:17 PM Alex Deucher wrote:
>
> Just a heads up, your sender email and your signed-off-by don't match
On Fri, 11 Jun 2021 13:03:09 +0100
Liviu Dudau wrote:
> On Fri, Jun 11, 2021 at 08:14:59AM +, Simon Ser wrote:
> > On Thursday, June 10th, 2021 at 23:00, Daniel Vetter
> > wrote:
> >
> > > If there's a strong consensus that we really need this then I'm not
> > > going to nack this, but t
On Mon, Jun 14, 2021 at 10:49 AM Mark Yacoub wrote:
>
> hmm I see, thanks for the heads up, I'll double check why it uses
> google email for sending.
> wrt the assignment in the if clauses, are those typically frowned upon?
Yes, checkpatch complains about them.
Alex
> Thanks!
>
> On Fri, Jun 1
On 6/14/21 3:48 PM, Matthew Auld wrote:
On Mon, 14 Jun 2021 at 12:54, Thomas Hellström
wrote:
After a TTM move or object init we need to update the i915 gem flags and
caching settings to reflect the new placement. Currently caching settings
are not changed during the lifetime of an object, al
From: Rob Clark
Just for the purposes of testing. Write to it the # of objects to scan,
read back the # freed.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_debugfs.c | 28 ++
drivers/gpu/drm/msm/msm_drv.h | 4
drivers/gpu/drm/msm/msm_gem_shr
On Mon, Jun 14, 2021 at 05:49:12PM +0300, Pekka Paalanen wrote:
> On Fri, 11 Jun 2021 13:03:09 +0100
> Liviu Dudau wrote:
>
> > On Fri, Jun 11, 2021 at 08:14:59AM +, Simon Ser wrote:
> > > On Thursday, June 10th, 2021 at 23:00, Daniel Vetter
> > > wrote:
> > >
> > > > If there's a strong
Am 2021-06-09 um 3:23 p.m. schrieb Matthew Wilcox:
> On Mon, Jun 07, 2021 at 03:42:19PM -0500, Alex Sierra wrote:
>> +++ b/include/linux/dax.h
>> @@ -243,6 +243,16 @@ static inline bool dax_mapping(struct address_space
>> *mapping)
>> return mapping->host && IS_DAX(mapping->host);
>> }
>>
Hi,
On Fri, Jun 11, 2021 at 2:29 PM Linus Walleij wrote:
>
> +static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd,
> + u8 *data, size_t len)
> +{
> + struct spi_device *spi = dbi->spi;
> + u32 speed_hz = min_t(u32, MIPI_DBI_MAX_S
Hi,
On Fri, Jun 11, 2021 at 2:44 PM Linus Walleij wrote:
>
> static int s6e63m0_spi_probe(struct spi_device *spi)
> {
> struct device *dev = &spi->dev;
> + struct mipi_dbi *dbi;
> int ret;
>
> - spi->bits_per_word = 9;
> - /* Preserve e.g. SPI_3WIRE setting */
On Thu, Jun 10, 2021 at 9:55 AM Pekka Paalanen wrote:
>
> On Tue, 8 Jun 2021 19:43:15 +0200
> Werner Sembach wrote:
>
> > Add a new general drm property "active bpc" which can be used by graphic
> > drivers
> > to report the applied bit depth per pixel back to userspace.
> >
Maybe "bit depth p
On Fri, Jun 11, 2021 at 07:54:07AM +0200, Maxime Ripard wrote:
> On Thu, Jun 10, 2021 at 11:00:05PM +0200, Daniel Vetter wrote:
> > On Thu, Jun 10, 2021 at 7:47 PM Maxime Ripard wrote:
> > >
> > > New KMS properties come with a bunch of requirements to avoid each
> > > driver from running their ow
On 06/08, Juan A. Suarez Romero wrote:
> The V3D engine has several hardware performance counters that can of
> interest for userspace performance analysis tools.
>
> This exposes new ioctls to create and destroy performance monitor
> objects, as well as to query the counter values.
>
> Each crea
On Fri, Jun 11, 2021 at 02:34:18PM +0100, Liviu Dudau wrote:
> On Fri, Jun 11, 2021 at 08:56:04AM -0400, Alyssa Rosenzweig wrote:
> > > What I'm expected to see in the future is new functionality that gets
> > > implemented by
> > > one hardware vendor and the kernel developers trying to enable th
This patchset implements synchronous accelerated migration and clearing
for i915 on TTM. We plan to follow up with these operations made
asynchronous to the extent of TTM support for that:
A couple of patches from Chris which implement pipelined migration and
clears by atomically writing the PTEs
Introduce a for_i915_gem_ww(){} utility to help make the code
around a ww transaction more readable.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_ww.h | 31 +-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git
As we're about to add more ww-related functionality,
break out the dma_resv ww locking utilities to their own files
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2:
- Make sure filenames are sorted in include file lists and Makefile
(Reported by Matthew Auld)
---
drivers/gpu/
Since the ww transaction endpoint easily end up far out-of-scope of
the objects on the ww object list, particularly for contending lock
objects, make sure we reference objects on the list so they don't
disappear under us.
This comes with a performance penalty so it's been debated whether this
is r
From: Chris Wilson
In the next patch, we will want to look at the dma addresses of
individual page tables, so add a routine to iterate over them.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 49
drivers/gpu/drm/i
From: Chris Wilson
Allow internal clients to create and destroy a pinned context.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
v2:
- (Thomas) Export also the pinned context destructor
---
drivers/gpu/drm/i915/gt/intel_engine.h| 11 +
drivers/gpu/drm/i915/gt/intel_engi
From: Chris Wilson
In the next patch, we will want to write a PTE for an explicit
dma address, outside of the usual vma.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/driv
From: Chris Wilson
If we pipeline the PTE updates and then do the copy of those pages
within a single unpreemptible command packet, we can submit the copies
and leave them to be scheduled without having to synchronously wait
under a global lock. In order to manage migration, we need to
preallocat
From: Chris Wilson
Set up a default migration context on the GT and use it from the
selftests.
Add a perf selftest and make sure we exercise LMEM if available.
Signed-off-by: Chris Wilson
Co-developed-by: Thomas Hellström
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v3:
- Sk
It's unused with the exception of selftest. Replace a call in the
memory_region live selftest with a call into a corresponding
function in the new migrate code.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/Makefile | 1 -
.../gpu/drm/i915/gem/i915_gem_object_blt.c
It's not used anywhere.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/Makefile | 1 -
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 355 -
.../gpu/drm/i915/gem/i915_gem_client_blt.h| 21 -
.../i915/gem/selftests/i915_gem_client_blt.c | 704 ---
From: Ramalingam C
Invokes the pipelined page migration through blt, for
i915_ttm_move requests of eviction and also obj clear.
Signed-off-by: Ramalingam C
---
v2:
- subfunction for accel_move (Thomas)
- engine_pm_get/put around context_move/clear (Thomas)
- Invalidation at accel_clear (Thom
From: Chris Wilson
Update the PTE and emit a clear within a single unpreemptible packet
such that we can schedule and pipeline clears.
Signed-off-by: Chris Wilson
Co-developed-by: Thomas Hellström
Signed-off-by: Thomas Hellström
---
v3:
- Handle engine instances correctly (Reported by Matthew
On Mon, Jun 14, 2021 at 10:35:30AM +0200, Zbigniew Kempczyński wrote:
> On Fri, Jun 11, 2021 at 04:54:32AM -0400, Rodrigo Vivi wrote:
> > On Fri, Jun 11, 2021 at 08:09:00AM +0200, Zbigniew Kempczyński wrote:
> > > On Thu, Jun 10, 2021 at 10:36:12AM -0400, Rodrigo Vivi wrote:
> > > > On Thu, Jun 10,
On 14/06/2021 17:26, Thomas Hellström wrote:
It's not used anywhere.
Signed-off-by: Thomas Hellström
We do have to keep igt_client_tiled_blits subtest, it's not related to
the client blitting code and was added afterwards. Not completely sure
why it's in this file.
With that added back,
R
On Mon, Jun 14, 2021 at 04:24:13PM +0100, Liviu Dudau wrote:
> On Mon, Jun 14, 2021 at 05:49:12PM +0300, Pekka Paalanen wrote:
> > On Fri, 11 Jun 2021 13:03:09 +0100
> > Liviu Dudau wrote:
> >
> > > On Fri, Jun 11, 2021 at 08:14:59AM +, Simon Ser wrote:
> > > > On Thursday, June 10th, 2021 at
On Monday 14 June 2021 13:05:17 Christian König wrote:
> AGP for example doesn't have a dma_address array.
>
> Signed-off-by: Christian König
Fixes NULL pointer dereference in nouveau_bo_sync_for_device on AGP cards.
Tested-by: Ondrej Zary
> ---
> drivers/gpu/drm/nouveau/nouveau_bo.c | 4 ++-
On 6/14/21 6:33 PM, Matthew Auld wrote:
On 14/06/2021 17:26, Thomas Hellström wrote:
It's not used anywhere.
Signed-off-by: Thomas Hellström
We do have to keep igt_client_tiled_blits subtest, it's not related to
the client blitting code and was added afterwards. Not completely sure
why i
On 14/06/2021 17:26, Thomas Hellström wrote:
It's unused with the exception of selftest. Replace a call in the
memory_region live selftest with a call into a corresponding
function in the new migrate code.
I guess we do lose some coverage around blitting massively sized GEM
objects using the h
Den 14.06.2021 17.49, skrev Doug Anderson:
> Hi,
>
> On Fri, Jun 11, 2021 at 2:29 PM Linus Walleij
> wrote:
>>
>> +static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd,
>> + u8 *data, size_t len)
>> +{
>> + struct spi_device *spi =
On 6/9/2021 9:36 PM, Matthew Brost wrote:
From: Michal Wajdeczko
New GuC firmware will unify format of MMIO and CTB H2G messages.
Introduce their definitions now to allow gradual transition of
our code to match new changes.
Signed-off-by: Matthew Brost
Signed-off-by: Michal Wajdeczko
Cc:
The call to the hw scheduler has a limitation on the size of all parameters
combined. I think we can only pass a 32-bit sequence number and a ~16-bit
global (per-GPU) syncobj handle in one call and not much else.
The syncobj handle can be an element index in a global (per-GPU) syncobj
table and it
As long as we can figure out who touched to a certain sync object last
that would indeed work, yes.
Christian.
Am 14.06.21 um 19:10 schrieb Marek Olšák:
The call to the hw scheduler has a limitation on the size of all
parameters combined. I think we can only pass a 32-bit sequence number
and
Am 11.06.21 um 16:55 schrieb Daniel Vetter:
On Fri, Jun 11, 2021 at 04:53:11PM +0200, Christian König wrote:
Am 11.06.21 um 16:47 schrieb Daniel Vetter:
On Fri, Jun 11, 2021 at 02:02:57PM +0200, Christian König wrote:
As the name implies if testing all fences is requested we
should indeed tes
On Thu 10 Jun 16:44 CDT 2021, Rob Clark wrote:
> From: Jordan Crouse
>
> Call report_iommu_fault() to allow upper-level drivers to register their
> own fault handlers.
>
> Signed-off-by: Jordan Crouse
> Signed-off-by: Rob Clark
> Acked-by: Will Deacon
Reviewed-by: Bjorn Andersson
Regards,
On Thu 10 Jun 16:44 CDT 2021, Rob Clark wrote:
> From: Jordan Crouse
>
> Add a callback in adreno-smmu-priv to read interesting SMMU
> registers to provide an opportunity for a richer debug experience
> in the GPU driver.
>
> Signed-off-by: Jordan Crouse
> Signed-off-by: Rob Clark
I presume
Early implementation of moving system memory for discrete cards over to
TTM. We first add the notion of objects being migratable under the object
lock to i915 gem, and add some asserts to verify that objects are either
locked or pinned when the placement is checked by the gem code.
Patch 2 and 3 d
Instead of relying on a static placement, calculate at get_pages() time.
This should work for LMEM regions and system for now. For stolen we need
to take preallocated range into account. That will if needed be added
later.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2:
- Fixed
For discrete, use TTM for both cached and WC system memory. That means
we currently rely on the TTM memory accounting / shrinker. For cached
system memory we should consider remaining shmem-backed, which can be
implemented from our ttm_tt_populate callback. We can then also reuse our
own very elabo
The object ops i915_GEM_OBJECT_HAS_IOMEM and the object
I915_BO_ALLOC_STRUCT_PAGE flags are considered immutable by
much of our code. Introduce a new mem_flags member to hold these
and make sure checks for these flags being set are either done
under the object lock or with pages properly pinned. Th
After a TTM move or object init we need to update the i915 gem flags and
caching settings to reflect the new placement. Currently caching settings
are not changed during the lifetime of an object, although that might
change moving forward if we run into performance issues or issues with
WC system p
Unwrap the explicit fence if it is a dma_fence_chain and
sync to the first fence not matching the owner rules.
Signed-off-by: Christian König
Acked-by: Daniel Vetter
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 118 +--
1 file changed, 68 insertions(+), 50 deletions(-)
di
Drop the workaround and instead implement a better solution.
Basically we are now chaining all submissions using a dma_fence_chain
container and adding them as exclusive fence to the dma_resv object.
This way other drivers can still sync to the single exclusive fence
while amdgpu only sync to fen
On Thu 10 Jun 16:44 CDT 2021, Rob Clark wrote:
> From: Jordan Crouse
>
> Use the new adreno-smmu-priv fault info function to get more SMMU
> debug registers and print the current TTBR0 to debug per-instance
> pagetables and figure out which GPU block generated the request.
>
Acked-by: Bjorn An
On Thu 10 Jun 16:44 CDT 2021, Rob Clark wrote:
> From: Rob Clark
>
> Add, via the adreno-smmu-priv interface, a way for the GPU to request
> the SMMU to stall translation on faults, and then later resume the
> translation, either retrying or terminating the current translation.
>
> This will be
On 6/14/21 6:26 PM, Thomas Hellström wrote:
From: Ramalingam C
Invokes the pipelined page migration through blt, for
i915_ttm_move requests of eviction and also obj clear.
Signed-off-by: Ramalingam C
---
v2:
- subfunction for accel_move (Thomas)
- engine_pm_get/put around context_move/c
Hi Marek,
On Tue, May 25, 2021 at 12:38:47PM +0200, Marek Vasut wrote:
> On 5/18/21 1:03 AM, Laurent Pinchart wrote:
>
> Hi,
>
> [...]
>
> >> @@ -69,10 +70,33 @@ static void lvds_codec_disable(struct drm_bridge
> >> *bridge)
> >>"Failed to disable regulator \"vcc\": %d\n",
Hi Marek,
Thank you for the patch.
On Wed, Jun 02, 2021 at 10:37:30PM +0200, Marek Vasut wrote:
> Decoder input LVDS format is a property of the decoder chip or even
> its strapping. Add DT property data-mapping the same way lvds-panel
> does, to define the LVDS data mapping.
>
> Signed-off-by:
On 6/9/2021 9:36 PM, Matthew Brost wrote:
From: Michal Wajdeczko
The MMIO based Host-to-GuC communication protocol has been
updated to use unified HXG messages.
Update our intel_guc_send_mmio() function by correctly handle
BUSY, RETRY and FAILURE replies. Also update our documentation.
Sin
Implement SPI reads for typec1, for SPI controllers that
can support 9bpw in addition to 8bpw (such as GPIO bit-banged
SPI).
9bpw emulation is not supported but we have to start with
something.
This is used by s6e63m0 to read display MTP information
which is used by the driver for backlight contr
The SPI access to s6e63m0 is using the DBI protocol, so switch
to using the elaborate DBI protocol implementation in the DRM
DBI helper library.
Acked-by: Noralf Trønnes
Reviewed-by: Douglas Anderson
Signed-off-by: Linus Walleij
---
ChangeLog v1->v2:
- Drop two debug prints
- Drop development a
On 6/9/2021 9:36 PM, Matthew Brost wrote:
From: Michal Wajdeczko
Definition of the CTB descriptor has changed, leaving only
minimal shared fields like HEAD/TAIL/STATUS.
Both HEAD and TAIL are now in dwords.
Add some ABI documentation and implement required changes.
v2:
(Daniele)
- Dr
On 6/9/2021 9:36 PM, Matthew Brost wrote:
From: Michal Wajdeczko
Definition of the CTB registration action has changed.
Add some ABI documentation and implement required changes.
v2:
(Checkpoint)
- Fix warnings
(Daniele)
- Drop FIXME
(John H)
- Drop value in kernel doc, just
On 6/9/2021 9:36 PM, Matthew Brost wrote:
From: Michal Wajdeczko
Format of the CTB messages has changed:
- support for multiple formats
- message fence is now part of the header
- reuse of unified HXG message formats
v2:
(Daniele)
- Better comment in ct_write()
Signed-off-by: Mi
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