Am 02.06.21 um 21:19 schrieb Daniel Vetter:
On Wed, Jun 02, 2021 at 08:52:38PM +0200, Christian König wrote:
Am 02.06.21 um 20:48 schrieb Daniel Vetter:
On Wed, Jun 02, 2021 at 05:38:51AM -0400, Marek Olšák wrote:
On Wed, Jun 2, 2021 at 5:34 AM Marek Olšák wrote:
Yes, we can't break anythi
Am 03.06.21 um 05:28 schrieb Wan Jiabing:
Fix following coccicheck warning:
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1726:2-3: Unneeded semicolon
Signed-off-by: Wan Jiabing
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
1 file changed, 1 insertion(+), 1
Am 04.06.21 um 05:02 schrieb Chen Li:
Also fix some coding issue reported from sparse.
Signed-off-by: Chen Li
Acked-by: Christian König
---
drivers/gpu/drm/radeon/radeon_uvd.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/
Am 04.06.21 um 05:04 schrieb Chen Li:
I met a gpu addr bug recently and the kernel log
tells me the pc is memcpy/memset and link register is
radeon_uvd_resume.
As we know, in some architectures, optimized memcpy/memset
may not work well on device memory. Trival memcpy_toio/memset_io
can fix t
Also fix some coding issue reported from sparse.
Signed-off-by: Chen Li
---
drivers/gpu/drm/radeon/radeon_uvd.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c
b/drivers/gpu/drm/radeon/radeon_uvd.c
index dfa9fd
I met a gpu addr bug recently and the kernel log
tells me the pc is memcpy/memset and link register is
radeon_uvd_resume.
As we know, in some architectures, optimized memcpy/memset
may not work well on device memory. Trival memcpy_toio/memset_io
can fix this problem.
BTW, amdgpu has already don
changelog:
v1->v2: split sparse and memcp/memset fix
Chen Li (2):
radeon: fix coding issues reported from sparse
radeon: use memcpy_to/fromio for UVD fw upload
drivers/gpu/drm/radeon/radeon_uvd.c | 30 -
1 file changed, 17 insertions(+), 13 deletions(-)
--
On Fri, Jun 4, 2021 at 3:41 AM Kees Cook wrote:
> VEXPRESS_CONFIG needs to either be missing, built-in, or modular when
> pl111 is modular. Update the Kconfig to reflect the need.
>
> Fixes: 4dc7c97d04dc ("drm/pl111: depend on CONFIG_VEXPRESS_CONFIG")
Yeah that doesn't work, thanks for fixing th
On 03/06/2021 22:21, Alyssa Rosenzweig wrote:
> The value of the AFBC_FEATURES register is required by userspace to
> determine AFBC support on Bifrost. A user on our IRC channel (#panfrost)
> reported a workload that raised a fault on one system's Mali G31 but
> worked flawlessly with another syst
Am 03.06.21 um 09:36 schrieb Daniel Vetter:
On Thu, Jun 3, 2021 at 8:50 AM Thomas Hellström
wrote:
On 6/2/21 8:40 PM, Daniel Vetter wrote:
On Wed, Jun 02, 2021 at 11:48:41AM +0200, Christian König wrote:
Am 02.06.21 um 11:16 schrieb Thomas Hellström (Intel):
On 6/2/21 10:32 AM, Christian Kö
Am 03.06.21 um 14:34 schrieb Colin King:
From: Colin Ian King
The variable k is being assigned a value that is never read, the
assignment is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
Reviewed-by: Christian König
---
drivers/gpu/drm
Hi Linus
On Fri, May 28, 2021 at 01:57:56AM +0200, Linus Walleij wrote:
> On Mon, May 24, 2021 at 3:19 PM Maxime Ripard wrote:
>
> > The new gpiod interface takes care of parsing the GPIO flags and to
> > return the logical value when accessing an active-low GPIO, so switching
> > to it simplifi
Am 04.06.21 um 09:53 schrieb Chen Li:
I met a gpu addr bug recently and the kernel log
tells me the pc is memcpy/memset and link register is
radeon_uvd_resume.
As we know, in some architectures, optimized memcpy/memset
may not work well on device memory. Trival memcpy_toio/memset_io
can fix t
On Thu, Jun 03, 2021 at 07:02:57PM -0700, Matthew Brost wrote:
> On Thu, Jun 03, 2021 at 11:35:28PM +0200, Daniel Vetter wrote:
> > On Wed, Jun 02, 2021 at 10:16:18PM -0700, Matthew Brost wrote:
> > > From: Michal Wajdeczko
> > >
> > > Generic helpers should be placed in i915_utils.h.
> >
> > Ra
On Fri, Jun 4, 2021 at 5:25 AM Matthew Brost wrote:
>
> On Wed, Jun 02, 2021 at 03:33:43PM +0100, Tvrtko Ursulin wrote:
> >
> > On 06/05/2021 20:14, Matthew Brost wrote:
> > > Reset implementation for new GuC interface. This is the legacy reset
> > > implementation which is called when the i915 ow
On Thu, Jun 03, 2021 at 04:04:08PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> Future GuC will require CTB buffers sizes to be multiple of 4K.
> Make these changes now as this shouldn't impact us too much.
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
> Review
On 02/06/2021 17:32, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:17: warning: expecting
prototype for Register offsets in MDSS register file for the interrupt
registers(). Prototype was for MDP_SSPP_TOP0_OFF() instead
On Wed, Jun 02, 2021 at 10:16:23PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> In upcoming patch we will allow more CTB requests to be sent in
> parallel to the GuC for processing, so we shouldn't assume any more
> that GuC will always reply without 10ms.
>
> Use bigger value from C
On Wed, Jun 02, 2021 at 10:16:24PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> We want to stop using guc.send_mutex while sending CTB messages
> so we have to start protecting access to CTB send descriptor.
>
> For completeness protect also CTB receive descriptor.
>
> Add spinlock
Am 04.06.21 um 10:28 schrieb Chen Li:
On Fri, 04 Jun 2021 16:08:26 +0800,
Christian König wrote:
Am 04.06.21 um 09:53 schrieb Chen Li:
I met a gpu addr bug recently and the kernel log
tells me the pc is memcpy/memset and link register is
radeon_uvd_resume.
As we know, in some architecture
On Thu, Jun 03, 2021 at 09:10:14AM -0700, Matthew Brost wrote:
> On Thu, Jun 03, 2021 at 11:44:57AM +0200, Michal Wajdeczko wrote:
> >
> >
> > On 03.06.2021 07:16, Matthew Brost wrote:
> > > Ensure H2G buffer updates are visible before descriptor tail updates by
> > > inserting a barrier between
On Wed, Jun 02, 2021 at 10:16:30PM -0700, Matthew Brost wrote:
> From: Daniele Ceraolo Spurio
>
> GuC has its own defines for the engine classes. They're currently
> mapping 1:1 to the defines used by the driver, but there is no guarantee
> this will continue in the future. Given that we've been
On 04.06.2021 10:20, Daniel Vetter wrote:
> On Thu, Jun 03, 2021 at 04:04:08PM -0700, Matthew Brost wrote:
>> From: Michal Wajdeczko
>>
>> Future GuC will require CTB buffers sizes to be multiple of 4K.
>> Make these changes now as this shouldn't impact us too much.
>>
>> Signed-off-by: Michal
Am 04.06.21 um 10:43 schrieb Chen Li:
I met a gpu addr bug recently and the kernel log
tells me the pc is memcpy/memset and link register is
radeon_uvd_resume.
As we know, in some architectures, optimized memcpy/memset
may not work well on device memory. Trival memcpy_toio/memset_io
can fix this
On Fri, Jun 04, 2021 at 09:00:31AM +0200, Christian König wrote:
> Am 02.06.21 um 21:19 schrieb Daniel Vetter:
> > On Wed, Jun 02, 2021 at 08:52:38PM +0200, Christian König wrote:
> > >
> > > Am 02.06.21 um 20:48 schrieb Daniel Vetter:
> > > > On Wed, Jun 02, 2021 at 05:38:51AM -0400, Marek Olšák
On Fri, 04 Jun 2021, Dmitry Baryshkov wrote:
> On 02/06/2021 17:32, Lee Jones wrote:
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:17: warning: expecting
> > prototype for Register offsets in MDSS register file for the interrupt
On 6/4/21 9:51 AM, Christian König wrote:
Am 03.06.21 um 09:36 schrieb Daniel Vetter:
On Thu, Jun 3, 2021 at 8:50 AM Thomas Hellström
wrote:
On 6/2/21 8:40 PM, Daniel Vetter wrote:
On Wed, Jun 02, 2021 at 11:48:41AM +0200, Christian König wrote:
Am 02.06.21 um 11:16 schrieb Thomas Hellstr
Hi Stefan,
On Wed, May 26, 2021 at 12:47:29PM +0200, Stefan Wahren wrote:
> Hi,
>
> yesterday i was testing with Linux 5.13-rc3 on my Raspberry Pi 4 B
> (multi_v7_defconfig) and i'm getting the following errors during boot:
>
> [ 25.947494] vc4_hdmi fef00700.hdmi: ASoC: error at
> snd_soc_dai_
On Fri, Jun 04, 2021 at 11:01:40AM +0200, Thomas Hellström wrote:
>
> On 6/4/21 9:51 AM, Christian König wrote:
> > Am 03.06.21 um 09:36 schrieb Daniel Vetter:
> > > On Thu, Jun 3, 2021 at 8:50 AM Thomas Hellström
> > > wrote:
> > > >
> > > > On 6/2/21 8:40 PM, Daniel Vetter wrote:
> > > > > On
On Fri, Jun 04, 2021 at 09:44:59AM +0200, Linus Walleij wrote:
> On Fri, Jun 4, 2021 at 3:41 AM Kees Cook wrote:
>
> > VEXPRESS_CONFIG needs to either be missing, built-in, or modular when
> > pl111 is modular. Update the Kconfig to reflect the need.
> >
> > Fixes: 4dc7c97d04dc ("drm/pl111: depen
Hi, Christian,
It looks like all patches in the series have been reviewed or acked by
Matthew,
and while still a little worried about the final outcome of embedding a
struct ttm_mem_resource, FWIW,
Acked-by: Thomas Hellström
/Thomas
On 6/2/21 12:09 PM, Christian König wrote:
To improve the
Hello Borislav,
On 6/3/21 10:27 PM, Borislav Petkov wrote:
> On Tue, Jun 01, 2021 at 04:59:10PM +0200, Javier Martinez Canillas wrote:
>> The series touches different subystems and will need coordination between
>> maintainers. Ard Biesheuvel said that can be merged through the EFI tree.
>
> I'm
In order to ease debugging of DSI host registration issues, print return
code of dsi_mgr_setup_components().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
b/
Am 03.06.21 um 18:09 schrieb Liam Howlett:
Use vma_lookup() to find the VMA at a specific address. As vma_lookup()
will return NULL if the address is not within any VMA, the start address
no longer needs to be validated.
Signed-off-by: Liam R. Howlett
Reviewed-by: Christian König
---
dr
Am 04.06.21 um 10:57 schrieb Daniel Vetter:
On Fri, Jun 04, 2021 at 09:00:31AM +0200, Christian König wrote:
Am 02.06.21 um 21:19 schrieb Daniel Vetter:
On Wed, Jun 02, 2021 at 08:52:38PM +0200, Christian König wrote:
Am 02.06.21 um 20:48 schrieb Daniel Vetter:
On Wed, Jun 02, 2021 at 05:38:5
Am 03.06.21 um 10:45 schrieb Matthew Auld:
On 02/06/2021 11:09, Christian König wrote:
[SNIP]
-/**
- * ttm_bo_mem_placement - check if placement is compatible
- * @bo: BO to find memory for
- * @place: where to search
- * @mem: the memory object to fill in
- *
- * Check if placement is compat
On Fri, Jun 04, 2021 at 11:41:29AM +0200, Javier Martinez Canillas wrote:
> On 6/3/21 10:27 PM, Borislav Petkov wrote:
> > On Tue, Jun 01, 2021 at 04:59:10PM +0200, Javier Martinez Canillas wrote:
...
> > Btw, for the future, please CC everyone on the whole patchset - I had to
> > go look at your
Hi,
Commit ccf953d8f3d6 ("fb_defio: Remove custom address_space_operations")
seems to be breaking Hyper-V framebuffer
(drivers/video/fbdev/hyperv_fb.c) driver for me: Hyper-V guest boots
well and plymouth even works but when I try starting Gnome, virtual
screen just goes black. Reverting the above
On Thu, Jun 3, 2021 at 8:40 PM Kees Cook wrote:
>
> VEXPRESS_CONFIG needs to either be missing, built-in, or modular when
> pl111 is modular. Update the Kconfig to reflect the need.
>
> Fixes: 4dc7c97d04dc ("drm/pl111: depend on CONFIG_VEXPRESS_CONFIG")
> Signed-off-by: Kees Cook
> ---
> v2: use
On 27/05/2021 11:22, Tvrtko Ursulin wrote:
On 27/05/2021 11:13, Daniel Vetter wrote:
On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote:
On 25/05/2021 15:47, Daniel Vetter wrote:
On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote:
+ dri-devel as per process
On 25
The value of the AFBC_FEATURES register is required by userspace to
determine AFBC support on Bifrost. A user on our IRC channel (#panfrost)
reported a workload that raised a fault on one system's Mali G31 but
worked flawlessly with another system's Mali G31. We determined the
cause to be missing A
On Fri, Jun 04, 2021 at 02:25:01PM +0200, Vitaly Kuznetsov wrote:
> Hi,
>
> Commit ccf953d8f3d6 ("fb_defio: Remove custom address_space_operations")
> seems to be breaking Hyper-V framebuffer
> (drivers/video/fbdev/hyperv_fb.c) driver for me: Hyper-V guest boots
> well and plymouth even works but
The value of the AFBC_FEATURES register is required by userspace to
determine AFBC support on Bifrost. A user on our IRC channel (#panfrost)
reported a workload that raised a fault on one system's Mali G31 but
worked flawlessly with another system's Mali G31. We determined the
cause to be missing A
On Fri, Jun 4, 2021 at 11:15 AM Daniel Vetter wrote:
> On Fri, Jun 04, 2021 at 09:44:59AM +0200, Linus Walleij wrote:
> > On Fri, Jun 4, 2021 at 3:41 AM Kees Cook wrote:
> >
> > > VEXPRESS_CONFIG needs to either be missing, built-in, or modular when
> > > pl111 is modular. Update the Kconfig to r
convert_dc_color_depth_into_bpc() that converts the enum dc_color_depth to an
integer had the casses for COLOR_DEPTH_999 and COLOR_DEPTH_11 missing.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
1 file changed, 4 insertions(+)
diff --git a/dri
Rev 2: Fix small typo in commit message.
convert_dc_color_depth_into_bpc() that converts the enum dc_color_depth to an
integer had the cases for COLOR_DEPTH_999 and COLOR_DEPTH_11 missing.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
1 file changed, 4 insertions(+)
diff --git a/driv
On Tue, Jun 01, 2021 at 04:59:11PM +0200, Javier Martinez Canillas wrote:
> The x86 architecture has generic support to register a system framebuffer
> platform device. It either registers a "simple-framebuffer" if the config
> option CONFIG_X86_SYSFB is enabled, or a legacy VGA/VBE/EFI FB device.
On 6/4/21 2:20 PM, Andy Shevchenko wrote:
> On Fri, Jun 04, 2021 at 11:41:29AM +0200, Javier Martinez Canillas wrote:
>> On 6/3/21 10:27 PM, Borislav Petkov wrote:
>>> On Tue, Jun 01, 2021 at 04:59:10PM +0200, Javier Martinez Canillas wrote:
[snip]
>
> For myself I wrote a script to try being sm
On Fri, Jun 04, 2021 at 02:25:01PM +0200, Vitaly Kuznetsov wrote:
> Commit ccf953d8f3d6 ("fb_defio: Remove custom address_space_operations")
> seems to be breaking Hyper-V framebuffer
https://lore.kernel.org/linux-mm/YLZUrEjVJWBGGMxf@phenom.ffwll.local/
On 2021-06-04 9:16 a.m., Werner Sembach wrote:
> convert_dc_color_depth_into_bpc() that converts the enum dc_color_depth to an
> integer had the cases for COLOR_DEPTH_999 and COLOR_DEPTH_11 missing.
>
> Signed-off-by: Werner Sembach
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |
Am 04.06.21 um 11:12 schrieb Daniel Vetter:
On Fri, Jun 04, 2021 at 11:01:40AM +0200, Thomas Hellström wrote:
On 6/4/21 9:51 AM, Christian König wrote:
Am 03.06.21 um 09:36 schrieb Daniel Vetter:
On Thu, Jun 3, 2021 at 8:50 AM Thomas Hellström
wrote:
On 6/2/21 8:40 PM, Daniel Vetter wrote:
On Wed, 26 May 2021 at 17:21, Emil Velikov wrote:
>
> Hi Ville,
>
> On Tue, 18 May 2021 at 12:17, Ville Syrjälä
> wrote:
> >
> > On Tue, May 18, 2021 at 12:09:56PM +0100, Emil Velikov wrote:
> > > Hi Ville,
> > >
> > > On Mon, 17 May 2021 at 18:24, Ville Syrjälä
> > > wrote:
> > > >
> > > > On S
On Fri, 2021-06-04 at 15:38 +0200, Christian König wrote:
> Am 04.06.21 um 11:12 schrieb Daniel Vetter:
> > On Fri, Jun 04, 2021 at 11:01:40AM +0200, Thomas Hellström wrote:
> > > On 6/4/21 9:51 AM, Christian König wrote:
> > > > Am 03.06.21 um 09:36 schrieb Daniel Vetter:
> > > > > On Thu, Jun 3,
Am 04.06.21 um 16:03 schrieb Thomas Hellström:
On Fri, 2021-06-04 at 15:38 +0200, Christian König wrote:
Am 04.06.21 um 11:12 schrieb Daniel Vetter:
On Fri, Jun 04, 2021 at 11:01:40AM +0200, Thomas Hellström wrote:
On 6/4/21 9:51 AM, Christian König wrote:
Am 03.06.21 um 09:36 schrieb Daniel
On Fri, Jun 04, 2021 at 02:47:16PM +0100, Emil Velikov wrote:
> On Wed, 26 May 2021 at 17:21, Emil Velikov wrote:
> >
> > Hi Ville,
> >
> > On Tue, 18 May 2021 at 12:17, Ville Syrjälä
> > wrote:
> > >
> > > On Tue, May 18, 2021 at 12:09:56PM +0100, Emil Velikov wrote:
> > > > Hi Ville,
> > > >
>
On Fri, 2021-06-04 at 16:06 +0200, Christian König wrote:
> Am 04.06.21 um 16:03 schrieb Thomas Hellström:
> > On Fri, 2021-06-04 at 15:38 +0200, Christian König wrote:
> > > Am 04.06.21 um 11:12 schrieb Daniel Vetter:
> > > > On Fri, Jun 04, 2021 at 11:01:40AM +0200, Thomas Hellström
> > > > wrote
Am 04.06.21 um 16:11 schrieb Thomas Hellström:
On Fri, 2021-06-04 at 16:06 +0200, Christian König wrote:
Am 04.06.21 um 16:03 schrieb Thomas Hellström:
On Fri, 2021-06-04 at 15:38 +0200, Christian König wrote:
Am 04.06.21 um 11:12 schrieb Daniel Vetter:
On Fri, Jun 04, 2021 at 11:01:40AM +
On 04/06/2021 14:00, Alyssa Rosenzweig wrote:
> The value of the AFBC_FEATURES register is required by userspace to
> determine AFBC support on Bifrost. A user on our IRC channel (#panfrost)
> reported a workload that raised a fault on one system's Mali G31 but
> worked flawlessly with another syst
On Fri, Jun 04, 2021 at 11:07:42AM +1000, Alistair Popple wrote:
> On Friday, 4 June 2021 12:47:40 AM AEST Peter Xu wrote:
> > External email: Use caution opening links or attachments
> >
> > On Thu, Jun 03, 2021 at 09:39:32PM +1000, Alistair Popple wrote:
> > > Reclaim won't run on the page due t
On 2021-06-02 4:26 p.m., Shankar, Uma wrote:
>
>
>> -Original Message-
>> From: Pekka Paalanen
>> Sent: Wednesday, June 2, 2021 3:04 PM
>> To: Shankar, Uma
>> Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Modem,
>> Bhanuprakash
>> Subject: Re: [PATCH 01/21] drm:
From: Emil Velikov
Currently as the workaround is applied the screen flickers. As a result
we do not achieve seamless boot experience.
Avoiding the issue in the common use-case might be hard, although we can
resolve it for dual GPU setups - when the "other" GPU is primary and/or
outputs are conn
The newly added dma_resv_reset_shared_max() is used from an inline
function, so it can appear in drivers as well.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-resv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 3964df
On Fri, 4 Jun 2021 at 15:08, Ville Syrjälä
wrote:
>
> On Fri, Jun 04, 2021 at 02:47:16PM +0100, Emil Velikov wrote:
> > On Wed, 26 May 2021 at 17:21, Emil Velikov wrote:
> > >
> > > Hi Ville,
> > >
> > > On Tue, 18 May 2021 at 12:17, Ville Syrjälä
> > > wrote:
> > > >
> > > > On Tue, May 18, 202
On Thu, May 20, 2021 at 2:58 PM Kai-Heng Feng
wrote:
>
> On HP Fury G7 Workstations, graphics output is re-routed from Intel GFX
> to discrete GFX after S3. This is not desirable, because userspace will
> treat connected display as a new one, losing display settings.
>
> The expected behavior is t
On Fri, Jun 4, 2021 at 11:52 AM Christian König
wrote:
>
> The newly added dma_resv_reset_shared_max() is used from an inline
> function, so it can appear in drivers as well.
>
> Signed-off-by: Christian König
Acked-by: Alex Deucher
> ---
> drivers/dma-buf/dma-resv.c | 1 +
> 1 file changed,
Hi Doug,
panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
if (!panel->no_hpd) {
@@ -708,6 +712,8 @@ static int panel_simple_probe(struct device *dev,
const struct panel_desc *desc)
if (!panel->ddc)
return -EPROBE_DEFER;
+
Reviewed-by: Jason Ekstrand
On Fri, Jun 4, 2021 at 10:59 AM Alex Deucher wrote:
>
> On Fri, Jun 4, 2021 at 11:52 AM Christian König
> wrote:
> >
> > The newly added dma_resv_reset_shared_max() is used from an inline
> > function, so it can appear in drivers as well.
> >
> > Signed-off-by: Chris
On 2021-06-04 03:44, Dmitry Baryshkov wrote:
In order to ease debugging of DSI host registration issues, print
return
code of dsi_mgr_setup_components().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 4 ++--
1 file changed, 2 inserti
> Repeated word ;) But I've fixed that up and pushed it to drm-misc-next.
Whoops! Thanks. Next up would be v2 of the cycle counter series, which
means adding timestamp queries to the GL driver so I can test new UABI
for a TIMESTAMP parameter...
Applied. Thanks!
Alex
On Fri, Jun 4, 2021 at 1:05 AM Gustavo A. R. Silva
wrote:
>
> In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning
> by explicitly adding a break statement instead of letting the code fall
> through to the next case.
>
> Link: https://github.com/KSPP/li
Applied. Thanks!
Alex
On Fri, Jun 4, 2021 at 3:03 AM Christian König
wrote:
>
> Am 03.06.21 um 05:28 schrieb Wan Jiabing:
> > Fix following coccicheck warning:
> > ./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1726:2-3: Unneeded semicolon
> >
> > Signed-off-by: Wan Jiabing
>
> Reviewed-by: Christia
From: Mark Yacoub
For each CRTC state, check the size of Gamma and Degamma LUTs so
unexpected and larger sizes wouldn't slip through.
TEST: IGT:kms_color::pipe-invalid-gamma-lut-sizes
Signed-off-by: Mark Yacoub
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++
.../gpu/drm/amd/displa
From: Mark Yacoub
For each CRTC state, check the size of Gamma and Degamma LUTs so
unexpected and larger sizes wouldn't slip through.
TEST: IGT:kms_color::pipe-invalid-gamma-lut-sizes
Signed-off-by: Mark Yacoub
Change-Id: I9d513a38e8ac2af1b4bf802e1feb1a4d726fba4c
---
.../gpu/drm/amd/display/
Ignore this patch, in favor of (
https://patchwork.freedesktop.org/series/91023/), which appends the commit
title with drm/amd/display.
On Fri, Jun 4, 2021 at 12:59 PM Mark Yacoub wrote:
> From: Mark Yacoub
>
> For each CRTC state, check the size of Gamma and Degamma LUTs so
> unexpected and
On Thu, Jun 3, 2021 at 11:51 PM Linus Walleij wrote:
>
> Hi Qiang,
Hey Linus,
> I am using Lima on the ST-Ericsson U8500 SoC. It is one
> of the very earliest versions of MALI 400 MP. It mostly works
> on the mobile phones I have using PostmarkeOS and
> the Phosh UI (Wayland with MESA), but now
I started work on my proposal for better color handling in Linux display
drivers: https://lkml.org/lkml/2021/5/12/764
Since the first read-only property is now implemented for amdgpu and i915 I
wanted to collect some feedback, since the other two read-only properties will
be quite similar, I hope.
This commits implements the "active bpc" drm property for the Intel GPU driver.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++-
d
Add a new general drm property "active bpc" which can be used by graphic drivers
to report the applied bit depth per pixel back to userspace.
While "max bpc" can be used to change the color depth, there was no way to check
which one actually got used. While in theory the driver chooses the best/hi
This commits implements the "active bpc" drm property for the AMD GPU driver.
Signed-off-by: Werner Sembach
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c| 4 +++-
2 files changed, 20 insertions(+), 2 deletions(-)
dif
convert_dc_color_depth_into_bpc() that converts the enum dc_color_depth to an
integer had the casses for COLOR_DEPTH_999 and COLOR_DEPTH_11 missing.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
1 file changed, 4 insertions(+)
diff --git a/dri
Applied. Thanks!
Alex
On Fri, Jun 4, 2021 at 7:53 AM Chen Li wrote:
>
>
> Also fix some coding issues reported from sparse.
>
> Signed-off-by: Chen Li
> Acked-by: Christian König
> ---
> drivers/gpu/drm/radeon/radeon_uvd.c | 24 +---
> 1 file changed, 13 insertions(+), 11
On Thu, Jun 3, 2021 at 4:09 PM Matthew Brost wrote:
>
> Signed-off-by: Matthew Brost
> ---
> Documentation/gpu/i915.rst | 6
> drivers/gpu/drm/i915/i915_scheduler_types.h | 37 ++---
> 2 files changed, 38 insertions(+), 5 deletions(-)
>
> diff --git a/Docum
Applied with the RB fixed.
Thanks!
Alex
On Fri, Jun 4, 2021 at 7:53 AM Chen Li wrote:
>
>
> I met a gpu addr bug recently and the kernel log
> tells me the pc is memcpy/memset and link register is
> radeon_uvd_resume.
>
> As we know, in some architectures, optimized memcpy/memset
> may not work
The pull request you sent on Fri, 4 Jun 2021 11:54:28 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2021-06-04-1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/3a3c5ab3d6988afdcd63f3fc8e33d157ca1d9c67
Thank you!
--
Deet-doot-dot, I am a bot.
https://
On Fri, Jun 04, 2021 at 07:17:21PM +0200, Werner Sembach wrote:
> Add a new general drm property "active bpc" which can be used by graphic
> drivers
> to report the applied bit depth per pixel back to userspace.
>
> While "max bpc" can be used to change the color depth, there was no way to
> che
On Fri, Jun 04, 2021 at 07:17:23PM +0200, Werner Sembach wrote:
> This commits implements the "active bpc" drm property for the Intel GPU
> driver.
>
> Signed-off-by: Werner Sembach
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 13 +
> drivers/gpu/drm/i915/display/intel_dp.
On Fri, Jun 04, 2021 at 12:20:36PM -0500, Jason Ekstrand wrote:
> On Thu, Jun 3, 2021 at 4:09 PM Matthew Brost wrote:
> >
> > Signed-off-by: Matthew Brost
> > ---
> > Documentation/gpu/i915.rst | 6
> > drivers/gpu/drm/i915/i915_scheduler_types.h | 37 ++---
On Thu, Jun 3, 2021 at 4:09 PM Matthew Brost wrote:
>
> Introduce i915_sched_engine object which is lower level data structure
> that i915_scheduler / generic code can operate on without touching
> execlist specific structures. This allows additional submission backends
> to be added without break
On Wed, May 26, 2021 at 04:33:56PM -0700, Matthew Brost wrote:
> Add entry for i915 GuC submission / DRM scheduler integration plan.
> Follow up patch with details of new parallel submission uAPI to come.
>
> v2:
> (Daniel Vetter)
> - Expand explaination of why bonding isn't supported for GuC
>
On Fri, Jun 04, 2021 at 12:38:22PM -0500, Jason Ekstrand wrote:
> On Thu, Jun 3, 2021 at 4:09 PM Matthew Brost wrote:
> >
> > Introduce i915_sched_engine object which is lower level data structure
> > that i915_scheduler / generic code can operate on without touching
> > execlist specific structur
Hi Claire,
On Thu, May 27, 2021 at 08:58:30PM +0800, Claire Chang wrote:
> This series implements mitigations for lack of DMA access control on
> systems without an IOMMU, which could result in the DMA accessing the
> system memory at unexpected times and/or unexpected addresses, possibly
> leadin
Reviewed-by: Jason Ekstrand
On Thu, Jun 3, 2021 at 4:09 PM Matthew Brost wrote:
>
> Add wrapper function around RB tree to determine if i915_sched_engine is
> empty.
>
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +-
> drivers/gpu/drm/i915/gt/
On Fri, Jun 4, 2021 at 12:42 PM Matthew Brost wrote:
>
> On Fri, Jun 04, 2021 at 12:38:22PM -0500, Jason Ekstrand wrote:
> > On Thu, Jun 3, 2021 at 4:09 PM Matthew Brost
> > wrote:
> > >
> > > Introduce i915_sched_engine object which is lower level data structure
> > > that i915_scheduler / gene
On Fri, Jun 04, 2021 at 12:51:43PM -0500, Jason Ekstrand wrote:
> On Fri, Jun 4, 2021 at 12:42 PM Matthew Brost wrote:
> >
> > On Fri, Jun 04, 2021 at 12:38:22PM -0500, Jason Ekstrand wrote:
> > > On Thu, Jun 3, 2021 at 4:09 PM Matthew Brost
> > > wrote:
> > > >
> > > > Introduce i915_sched_engi
On Wed, May 26, 2021 at 04:33:57PM -0700, Matthew Brost wrote:
> Add entry for i915 new parallel submission uAPI plan.
>
> v2:
> (Daniel Vetter):
> - Expand logical order explaination
> - Add dummy header
> - Only allow N BBs in execbuf IOCTL
> - Configure parallel submission per slot not
On Fri, Jun 04, 2021 at 10:16:14AM +0200, Daniel Vetter wrote:
> On Fri, Jun 4, 2021 at 5:25 AM Matthew Brost wrote:
> >
> > On Wed, Jun 02, 2021 at 03:33:43PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 06/05/2021 20:14, Matthew Brost wrote:
> > > > Reset implementation for new GuC interface. Thi
On Fri, Jun 4, 2021 at 12:59 PM Matthew Brost wrote:
>
> On Fri, Jun 04, 2021 at 12:51:43PM -0500, Jason Ekstrand wrote:
> > On Fri, Jun 4, 2021 at 12:42 PM Matthew Brost
> > wrote:
> > >
> > > On Fri, Jun 04, 2021 at 12:38:22PM -0500, Jason Ekstrand wrote:
> > > > On Thu, Jun 3, 2021 at 4:09 PM
On Fri, Jun 04, 2021 at 10:44:31AM +0200, Daniel Vetter wrote:
> On Wed, Jun 02, 2021 at 10:16:30PM -0700, Matthew Brost wrote:
> > From: Daniele Ceraolo Spurio
> >
> > GuC has its own defines for the engine classes. They're currently
> > mapping 1:1 to the defines used by the driver, but there i
On 2021-06-01 6:51 a.m., Uma Shankar wrote:
> Add Plane Degamma Mode as an enum property. Create a helper
> function for all plane color management features.
>
> This is an enum property with values as blob_id's and exposes
> the various gamma modes supported and the lut ranges. Getting
> the blob
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