HEAD~2 punted on merging DRM_DEBUG_KMS_RATELIMITED; clean that up now,
removing the extra macro indirections which support !KMS cases, since
only _KMS_RATELIMITED is used. They can be re-added once needed.
conflict was here:
c5261e93758a drm/print: Fixup DRM_DEBUG_KMS_RATELIMITED()
Signed-off-by
hi everyone,
this patchset reworks the drm.debug controlled debug categories,
and remaps them to use dynamic_debug_exec_queries().
To do this "smoothly", DRM_UT_* is converted from an enum to a
class-prefix string, which is prepended## to the real format string.
This lets us use:
$> echo module
drm's debug system uses distinct categories of debug messages, mapped
to bits in drm.debug. Currently, code does a lot of unlikely bit-mask
checks on drm.debug (in drm_debug_enabled), we can use dynamic debug
instead, and get all that jump_label goodness.
RFC: dynamic debug has no concept of cate
s/prink/printk/ - no functional changes
Signed-off-by: Jim Cromie
---
include/drm/drm_print.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index a3c58c941bdc..9377a17d74f1 100644
--- a/include/drm/drm_print.h
+++ b/include/
The gvt component of this driver has ~120 pr_debugs, in 9 "classes".
Following model of drm.debug, add a parameter to map bits to these
classes.
In Makefile, add DYNAMIC_DEBUG_MODULE if CONFIG_DRM_USE_DYNAMIC_DEBUG.
In i915_params.c, add callback to map bits to queries.
TBD: consider moving the c
On 5/13/2021 10:43 PM, Jonathan Marek wrote:
SM8250 AOP firmware already sets up PDC registers for us, and it only needs
to be enabled. This path will be used for other newer GPUs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 -
1 file chan
On 5/13/2021 10:43 PM, Jonathan Marek wrote:
These aren't used by anything anymore.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/msm_gpu.h | 9 -
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/ad
On 5/13/2021 10:43 PM, Jonathan Marek wrote:
Value was shifted in the wrong direction, resulting in the field always
being zero, which is incorrect for A650.
Fixes: d0bac4e9cd66 ("drm/msm/a6xx: set ubwc config for A640 and A650")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6
On Thu, May 20, 2021 at 4:28 PM Daniel Vetter wrote:
>
> On Thu, May 20, 2021 at 08:35:14AM +0100, Matthew Auld wrote:
> > From: Chris Wilson
> >
> > The first tracepoint for a request is trace_dma_fence_init called before
> > we have associated the request with a device. The tracepoint uses
> >
On 5/13/2021 10:43 PM, Jonathan Marek wrote:
Update CP_PROTECT register programming based on downstream.
A6XX_PROTECT_RW is renamed to A6XX_PROTECT_NORDWR to make things aligned
and also be more clear about what it does.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
[Public]
>Hi,
>On 5/27/21 3:30 AM, Lang Yu wrote:
>> Make TTM_PL_FLAG_* start from zero and add
>> TTM_PL_FLAG_TEMPORARY flag for temporary
>> GTT allocation use.
>GTT is a driver private acronym, right? And it doesn't look like
>TTM_PL_FLAG_TEMPORARY will be used in core TTM, so should we inst
Cleanup and just make TTM_PL_FLAG_* start from zero.
Currently, we have a limitted GTT memory size and need a bounce buffer
when doing buffer migration between VRAM and SYSTEM domain.
The problem is under GTT memory pressure we can't do buffer migration
between VRAM and SYSTEM domain. But in some
If a BO's backing store is temporary GTT memory, we should
move it in BO validation.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/ttm/ttm_bo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index c32a37d0a460..80c8cb2c3f31 100644
-
Currently, we have a limitted GTT memory size and need a bounce buffer
when doing buffer migration between VRAM and SYSTEM domain.
The problem is under GTT memory pressure we can't do buffer migration
between VRAM and SYSTEM domain. But in some cases we really need that.
Eespecially when validatin
Yes, exactly that's my thinking and also the reason why I'm pondering so
hard on the requirement that the memory for shared user fences should
not be modifiable by userspace directly.
Christian.
Am 29.05.21 um 05:33 schrieb Marek Olšák:
My first email can be ignored except for the sync files.
On Thu, May 27, 2021 at 4:19 PM Matthew Brost wrote:
>
> On Thu, May 27, 2021 at 10:41:10AM +0100, Tvrtko Ursulin wrote:
> >
> > On 26/05/2021 21:03, Matthew Brost wrote:
> > > Introduce i915_sched_engine object which is lower level data structure
> > > that i915_scheduler / generic code can opera
On Thu, May 27, 2021 at 11:26:37AM -0500, Jason Ekstrand wrote:
> The current context uAPI allows for two methods of setting context
> parameters: SET_CONTEXT_PARAM and CONTEXT_CREATE_EXT_SETPARAM. The
> former is allowed to be called at any time while the later happens as
> part of GEM_CONTEXT_CR
On Thu, May 27, 2021 at 11:26:39AM -0500, Jason Ekstrand wrote:
> For now this is a no-op because everyone passes in a null SSEU but it
> lets us get some of the error handling and selftest refactoring plumbed
> through.
>
> Signed-off-by: Jason Ekstrand
I've reviewed this one already in the pre
On 5/30/21 6:51 PM, Christian König wrote:
Hi Thomas,
Am 29.05.21 um 17:48 schrieb Thomas Hellström (Intel):
Hi, Christian,
On 4/30/21 11:25 AM, Christian König wrote:
Start with the range manager to make the resource object the base
class for the allocated nodes.
While at it cleanup a lot
From: Thierry Reding
On Sun, 30 May 2021 22:55:06 +0300, Dmitry Osipenko wrote:
> The format modifier is 64bit, while DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT
> uses BIT() macro that is 32bit on ARM32.
>
> The (modifier &= ~DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT) doesn't work as
> expected on ARM32 and
Am 31.05.21 um 10:22 schrieb Lang Yu:
If a BO's backing store is temporary GTT memory, we should
move it in BO validation.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/ttm/ttm_bo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_b
On Thu, May 27, 2021 at 11:26:42AM -0500, Jason Ekstrand wrote:
> This means that the proto-context needs to grow support for engine
> configuration information as well as setparam logic. Fortunately, we'll
> be deleting a lot of setparam logic on the primary context shortly so it
> will hopefully
On 5/13/2021 10:44 PM, Jonathan Marek wrote:
If a6xx_hw_init() fails before creating the shadow_bo, the a6xx_pm_suspend
code referencing it will crash. Change the condition to one that avoids
this problem (note: creation of shadow_bo is behind this same condition)
Fixes: e8b0b994c3a5 ("drm/msm/a
Local variable 'i' and 'j' will be initialized in the for loop, so
remove the redundant initialization.
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Signed-off-by: Shaokun Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 17 -
1 file changed, 8 insertions(+), 9 deletions
Looks DRM to me. CCed...
On Mon, May 31, 2021 at 12:13:22AM -0700, syzbot wrote:
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:7ac3a1c1 Merge tag 'mtd/fixes-for-5.13-rc4' of git://git.k..
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt
Hi Mark, Takashi,
On Wed, May 26, 2021 at 11:39:21AM +0100, Mark Brown wrote:
> On Tue, May 25, 2021 at 03:23:47PM +0200, Maxime Ripard wrote:
> > The IEC958 status bit is usually set by the userspace after hw_params
> > has been called, so in order to use whatever is set by the userspace, we
> >
On Thu, May 27, 2021 at 11:26:45AM -0500, Jason Ekstrand wrote:
> The current context uAPI allows for two methods of setting context
> parameters: SET_CONTEXT_PARAM and CONTEXT_CREATE_EXT_SETPARAM. The
> former is allowed to be called at any time while the later happens as
> part of GEM_CONTEXT_CR
Hi, Lang,
On 5/31/21 10:19 AM, Yu, Lang wrote:
[Public]
Hi,
On 5/27/21 3:30 AM, Lang Yu wrote:
Make TTM_PL_FLAG_* start from zero and add
TTM_PL_FLAG_TEMPORARY flag for temporary
GTT allocation use.
GTT is a driver private acronym, right? And it doesn't look like
TTM_PL_FLAG_TEMPORARY will b
On Sun, 30 May 2021, Alyssa Rosenzweig wrote:
> Like many free software projects, freedesktop.org issued a non-binding
> recommendation for projects to migrate from Freenode to OFTC [1]. As
> such, freedesktop.org entries in the MAINTAINERS file are out-of-date as
> the respective channels have mo
This adds a new driver for the Samsung DB7430 DPI display
controller as controlled over SPI.
Right now the only panel product we know that is using this
display controller is the LMS397KF04 but there may be more.
Cc: Doug Anderson
Signed-off-by: Linus Walleij
---
ChangeLog v1->v2:
- Rename driv
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu, Lang wrote:
[Public]
Hi,
On 5/27/21 3:30 AM, Lang Yu wrote:
Make TTM_PL_FLAG_* start from zero and add
TTM_PL_FLAG_TEMPORARY flag for temporary
GTT allocation use.
GTT is a driver private acronym, righ
On Fri, 28 May 2021, "Leizhen (ThunderTown)" wrote:
> On 2021/5/27 18:04, Jani Nikula wrote:
>> On Thu, 27 May 2021, Zhen Lei wrote:
>>> If intel_hdcp_validate_v_prime() has been successful within the allowed
>>> number of tries, we can directly call drm_dbg_kms() and "goto out" without
>>> jumpi
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu, Lang wrote:
[Public]
Hi,
On 5/27/21 3:30 AM, Lang Yu wrote:
Make TTM_PL_FLAG_* start from zero and add
TTM_PL_FLAG_TEMPORARY flag for temporary
GTT allocat
Pushed to drm-misc-next.
On Sat, 29 May 2021 at 23:10, Adrien Grassein wrote:
>
> Reviewed-by: Adren Grassein
>
> Le sam. 29 mai 2021 à 02:30, Linus Walleij a écrit
> :
> >
> > The Lontium bridge is including legacy header files for GPIO
> > but not using them. Delete the includes.
> >
> > Cc:
Hi Doug,
just sent out a v2 of this! Hope you can look at it.
Some comment on comments:
On Thu, Apr 29, 2021 at 10:21 PM Doug Anderson wrote:
(...)
> > +#define LMS397_UNKNOWN_F8 0xf8
> > +#define LMS397_UNKNOWN_FC 0xfc
>
> I managed to dig up a copy of the DCS spec.
Hey Yu,
I'm not finding your this patch with the correct tags. I'd expect the subject:
[PATCH v2] drm: bridge: cdns-mhdp8546: Fix PM reference leak in
cdns_mhdp_probe()
Can you please resubmit using this title, just to be sure I merge the
right version of this code.
On Sat, 29 May 2021 at 11:46,
Am 31.05.21 um 12:46 schrieb Thomas Hellström (Intel):
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu, Lang wrote:
[Public]
Hi,
On 5/27/21 3:30 AM, Lang Yu wrote:
Make TTM_PL_FLAG_* start from zero and a
On Mon, 31 May 2021 11:42:13 +0200,
Maxime Ripard wrote:
>
> Hi Mark, Takashi,
>
> On Wed, May 26, 2021 at 11:39:21AM +0100, Mark Brown wrote:
> > On Tue, May 25, 2021 at 03:23:47PM +0200, Maxime Ripard wrote:
> > > The IEC958 status bit is usually set by the userspace after hw_params
> > > has b
On 5/31/21 12:56 PM, Christian König wrote:
Am 31.05.21 um 12:46 schrieb Thomas Hellström (Intel):
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu, Lang wrote:
[Public]
Hi,
On 5/27/21 3:30 AM, Lang Yu w
If a BO's backing store is temporary GTT memory, we should
move it in BO validation.
v2: move the check outside of for loop
Signed-off-by: Lang Yu
---
drivers/gpu/drm/ttm/ttm_bo.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
Am 31.05.21 um 13:30 schrieb Lang Yu:
If a BO's backing store is temporary GTT memory, we should
move it in BO validation.
v2: move the check outside of for loop
Signed-off-by: Lang Yu
In general those patches now have my rb, but let me add some more
documentation to them to better explain
Am 31.05.21 um 13:19 schrieb Thomas Hellström (Intel):
On 5/31/21 12:56 PM, Christian König wrote:
Am 31.05.21 um 12:46 schrieb Thomas Hellström (Intel):
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström (Intel):
Hi, Lang,
On 5/31/21 10:19 AM, Yu, La
On 5/31/21 2:02 PM, Christian König wrote:
Am 31.05.21 um 13:19 schrieb Thomas Hellström (Intel):
On 5/31/21 12:56 PM, Christian König wrote:
Am 31.05.21 um 12:46 schrieb Thomas Hellström (Intel):
On 5/31/21 12:32 PM, Christian König wrote:
Am 31.05.21 um 11:52 schrieb Thomas Hellström (I
This is an initial patch series to move discrete memory management over to
TTM. It will be followed up shortly with adding more functionality.
The buddy allocator is temporarily removed along with its selftests and
It is replaced with the TTM range manager and some selftests are adjusted
to accoun
Any sleeping dma_resv lock taken while the vma pages_mutex is held
will cause a lockdep splat.
Move the i915_gem_object_pin_pages() call out of the pages_mutex
critical section.
Signed-off-by: Thomas Hellström
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_vma.c | 29 +
All users of this function actually want the dma segment sizes, but that's
not what's calculated. Fix that and rename the function to
i915_sg_dma_sizes to reflect what's calculated.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2 +-
We are currently sharing the VM reservation locks across a number of
gem objects with page-table memory. Since TTM will individiualize the
reservation locks when freeing objects, including accessing the shared
locks, make sure that the shared locks are not freed until that is done.
For PPGTT we add
Temporarily remove the buddy allocator and related selftests
and hook up the TTM range manager for i915 regions.
Also modify the mock region selftests somewhat to account for a
fragmenting manager.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld #v2
---
v2:
- Fix an error unwind in lm
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free()
callbacks, that would cause problems with fault().
Instead, implement a method mapping page-b
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
So add a best-effort memcpy_from_wc taking dma-buf-map pointer
arguments that attempts to use a fast prefetching memcpy and
otherwise falls b
Use fast wc memcpy for reading out of wc memory for TTM bo moves.
Cc: Dave Airlie
Cc: Christian König
Cc: Daniel Vetter
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König #v4
--
v4:
- Clarify when we try drm_memcpy_from_wc_dbm (Reported by Matthew Auld)
- Be paranoid about when drm_
If the bo is idle when calling ttm_bo_pipeline_gutting(), we unnecessarily
create a ghost object and push it out to delayed destroy.
Fix this by adding a path for idle, and document the function.
Also avoid having the bo end up in a bad state vulnerable to user-space
triggered kernel BUGs if the c
Embed a struct ttm_buffer_object into the i915 gem object, making sure
we alias the gem object part. It's a bit unfortunate that the
struct ttm_buffer_ojbect embeds a gem object since we otherwise could
make the TTM part private to the TTM backend, and use the usual
i915 gem object for the other ba
Since objects can be migrated or evicted when not pinned or locked,
update the checks for lmem residency or future residency so that
the value returned is not immediately stale.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2: Simplify i915_gem_object_migratable() (Reported by M
We are calling the eviction_valuable driver callback at eviction time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM backend needs the same functionality for swapout,
and that might actually be beneficial to other drivers as well.
Add an eviction_valuable call al
From: Maarten Lankhorst
The platform should exclusively use mmap_offset, one less path to worry
about for discrete.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gp
Most logical place to introduce TTM buffer objects is as an i915
gem object backend. We need to add some ops to account for added
functionality like delayed delete and LRU list manipulation.
Initially we support only LMEM and SYSTEM memory, but SYSTEM
(which in this case means evicted LMEM objects
From: Maarten Lankhorst
This allows drivers to distinguish between different types of vma_node's.
The readonly flag was unused and is thus removed.
This is a temporary solution, until i915 is converted completely to
use ttm for bo's.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellstr
From: Maarten Lankhorst
Use the ttm handlers for servicing page faults, and vm_access.
We do our own validation of read-only access, otherwise use the
ttm handlers as much as possible.
Because the ttm handlers expect the vma_node at vma->base, we slightly
need to massage the mmap handlers to lo
Am 31.05.21 um 14:19 schrieb Thomas Hellström:
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free()
callbacks, that would cause problems with fa
Am 31.05.21 um 14:19 schrieb Thomas Hellström:
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
So add a best-effort memcpy_from_wc taking dma-buf-map pointer
arguments that attempts to
ping
在 2021/5/15 17:01, Baokun Li 写道:
From: "libaok...@huawei.com"
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/nouveau/dispnv50/disp.c: In function 'nv50_mstm_cleanup':
drivers/gpu/drm/nouveau/dispnv50/disp.c:1389:6: warning:
variable ‘ret’ set but not used [-Wunused-but-
On which branch are you working? I have problems applying that one to
amd-staging-drm-next.
Christian.
Am 31.05.21 um 10:22 schrieb Lang Yu:
Currently, we have a limitted GTT memory size and need a bounce buffer
when doing buffer migration between VRAM and SYSTEM domain.
The problem is under
On 2021-05-20 4:18 p.m., Daniel Vetter wrote:
> On Thu, May 20, 2021 at 10:13:38AM +0200, Michel Dänzer wrote:
>> On 2021-05-20 9:55 a.m., Daniel Vetter wrote:
>>> On Wed, May 19, 2021 at 5:48 PM Michel Dänzer wrote:
On 2021-05-19 5:21 p.m., Jason Ekstrand wrote:
> On Wed, May 19, 20
[AMD Official Use Only]
>-Original Message-
>From: Koenig, Christian
>Sent: Monday, May 31, 2021 8:49 PM
>To: Yu, Lang ; amd-...@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Thomas Hellströ ; Olsak, Marek
>; Huang, Ray ; Deucher,
>Alexander
>Subject: Re: [PATCH v2 3/3]
On 5/31/21 2:36 PM, Christian König wrote:
Am 31.05.21 um 14:19 schrieb Thomas Hellström:
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free(
[AMD Official Use Only]
>-Original Message-
>From: Koenig, Christian
>Sent: Monday, May 31, 2021 7:55 PM
>To: Yu, Lang ; amd-...@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Thomas Hellströ ; Olsak, Marek
>; Huang, Ray ; Deucher,
>Alexander
>Subject: Re: [PATCH v2 2/2]
The SC7280 SoC uses the 7nm (V4.1) DSI PHY driver with
different enable|disable regulator loads.
Signed-off-by: Rajeev Nandan
---
drivers/gpu/drm/msm/Kconfig | 6 +++---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gp
Add support for v2.5.0 DSI block in the SC7280 SoC.
Signed-off-by: Rajeev Nandan
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 20
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
b/drivers/gpu/drm/msm/dsi
Add YAML schema for the device tree bindings for MSM 7nm DSI PHY driver.
Cc: Jonathan Marek
Signed-off-by: Rajeev Nandan
---
.../bindings/display/msm/dsi-phy-7nm.yaml | 68 ++
1 file changed, 68 insertions(+)
create mode 100644
Documentation/devicetree/bindings/di
Changes in this series add support for MSM display DSI CTRL & PHY drivers
for the SC7280 SoC, which has DSI controller v2.5.0 and DSI PHY v4.1.
This series also updates the missing bindings (yaml) for the 7nm DSI PHY
driver on "msm-next" branch.
Rajeev Nandan (3):
dt-bindings: msm/dsi: Add yaml
Hi Patrice
Thanks for your time to test my patch.
On Mon, May 31, 2021 at 9:20 PM Patrice CHOTARD
wrote:
>
> Hi Dillon
>
>
>
> On 5/14/21 1:02 PM, dillon.min...@gmail.com wrote:
> > From: Dillon Min
> >
> > This seriese fix three i2c/clk bug for stm32 f4/f7
> > - kernel runing in sdram, i2c dri
On Mon, May 31, 2021 at 9:15 PM Patrice CHOTARD
wrote:
>
> Hi Dillon
>
> When trying to applying this patch using "git am --3 " i got this
> error :
>
> error: cannot convert from y to UTF-8
> fatal: could not parse patch
>
> Whereas i got no similar error with the other patch 2/3 and 4.
>
> I f
pm_runtime_get_sync will increment pm usage counter even it failed.
Forgetting to putting operation will result in reference leak here.
Fix it by replacing it with pm_runtime_resume_and_get to keep usage
counter balanced.
Reported-by: Hulk Robot
Signed-off-by: Yu Kuai
---
changes in V2:
- chang
On 2021/05/31 18:54, Robert Foss wrote:
Hey Yu,
I'm not finding your this patch with the correct tags. I'd expect the subject:
[PATCH v2] drm: bridge: cdns-mhdp8546: Fix PM reference leak in
cdns_mhdp_probe()
Can you please resubmit using this title, just to be sure I merge the
right version of
Added r-b tag and merged to drm-misc next.
https://cgit.freedesktop.org/drm/drm-misc/log/?h=drm-misc-next
Thanks for the submission, and sorry about making you jump through all
those hoops.
On Mon, 31 May 2021 at 15:47, Yu Kuai wrote:
>
> pm_runtime_get_sync will increment pm usage counter even
On Thu, May 27, 2021 at 11:26:47AM -0500, Jason Ekstrand wrote:
> When the APIs were added to manage the engine set on a GEM context
> directly from userspace, the questionable choice was made to allow
> changing the engine set on a context at any time. This is horribly racy
> and there's absolute
On Thu, May 27, 2021 at 11:26:46AM -0500, Jason Ekstrand wrote:
> When the APIs were added to manage VMs more directly from userspace, the
> questionable choice was made to allow changing out the VM on a context
> at any time. This is horribly racy and there's absolutely no reason why
> any usersp
On Tue, May 11, 2021 at 02:27:08AM +0300, Dmitry Osipenko wrote:
> Display controller (DC) performs isochronous memory transfers, and thus,
> has a requirement for a minimum memory bandwidth that shall be fulfilled,
> otherwise framebuffer data can't be fetched fast enough and this results
> in a D
On Thu, May 27, 2021 at 11:26:50AM -0500, Jason Ekstrand wrote:
> Now that we have the whole engine set and VM at context creation time,
> we can just assign those fields instead of creating first and handling
> the VM and engines later. This lets us avoid creating useless VMs and
> engine sets an
Hi Patrice
On Mon, May 31, 2021 at 9:51 PM Patrice CHOTARD
wrote:
>
>
>
> On 5/31/21 3:38 PM, Dillon Min wrote:
> > Hi Patrice
> >
> > Thanks for your time to test my patch.
> >
> > On Mon, May 31, 2021 at 9:20 PM Patrice CHOTARD
> > wrote:
> >>
> >> Hi Dillon
> >>
> >>
> >>
> >> On 5/14/21 1:02
On Fri 28 May 10:33 CDT 2021, Dmitry Baryshkov wrote:
> On 07/04/2021 18:01, Dmitry Baryshkov wrote:
> > Move the bus clock to mdp device node,in order to facilitate bus band
> > width scaling on sdm845 target.
> >
> > The parent device MDSS will not vote for bus bw, instead the vote will
> > be
On Wed 07 Apr 10:01 CDT 2021, Dmitry Baryshkov wrote:
> Move the bus clock to mdp device node,in order to facilitate bus band
> width scaling on sm8250 target.
>
> The parent device MDSS will not vote for bus bw, instead the vote will
> be triggered by mdp device node. Since a minimum vote is req
On Fri, May 28, 2021 at 12:32 AM Tom Lendacky wrote:
>
> On 5/27/21 9:41 AM, Tom Lendacky wrote:
> > On 5/27/21 8:02 AM, Christoph Hellwig wrote:
> >> On Wed, May 19, 2021 at 11:50:07AM -0700, Florian Fainelli wrote:
> >>> You convert this call site with swiotlb_init_io_tlb_mem() which did not
> >
On 5/13/2021 10:44 PM, Jonathan Marek wrote:
Add adreno_is_{a660,a650_family} helpers and convert update existing
adreno_is_a650 usage based on downstream driver's logic (changing into
adreno_is_a650_family or adding adreno_is_a660).
And add the remaining changes required for A660, again based o
On 5/13/2021 10:44 PM, Jonathan Marek wrote:
Accept all SQE firmware versions for A660.
Re-organize the function a bit and print an error message for unexpected
GPU IDs instead of failing silently.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 36 +
On 5/13/2021 10:44 PM, Jonathan Marek wrote:
Add a660 hwcg table, ported over from downstream.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 ++
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h
On Thursday, May 20th, 2021 at 10:17 AM, Pekka Paalanen
wrote:
> I think adding "for all drivers" would make things much more clear,
> like in the other cases you mention "atomic-capable drivers".
Good point, done.
> > @@ -797,6 +802,13 @@ struct drm_get_cap {
> > * If set to 1, the DRM core
On 5/31/21 2:19 PM, Thomas Hellström wrote:
From: Maarten Lankhorst
Use the ttm handlers for servicing page faults, and vm_access.
We do our own validation of read-only access, otherwise use the
ttm handlers as much as possible.
Because the ttm handlers expect the vma_node at vma->base, we
This is an initial patch series to move discrete memory management over to
TTM. It will be followed up shortly with adding more functionality.
The buddy allocator is temporarily removed along with its selftests and
It is replaced with the TTM range manager and some selftests are adjusted
to accoun
All users of this function actually want the dma segment sizes, but that's
not what's calculated. Fix that and rename the function to
i915_sg_dma_sizes to reflect what's calculated.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2 +-
We are currently sharing the VM reservation locks across a number of
gem objects with page-table memory. Since TTM will individiualize the
reservation locks when freeing objects, including accessing the shared
locks, make sure that the shared locks are not freed until that is done.
For PPGTT we add
Any sleeping dma_resv lock taken while the vma pages_mutex is held
will cause a lockdep splat.
Move the i915_gem_object_pin_pages() call out of the pages_mutex
critical section.
Signed-off-by: Thomas Hellström
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_vma.c | 29 +
Temporarily remove the buddy allocator and related selftests
and hook up the TTM range manager for i915 regions.
Also modify the mock region selftests somewhat to account for a
fragmenting manager.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld #v2
---
v2:
- Fix an error unwind in lm
Embed a struct ttm_buffer_object into the i915 gem object, making sure
we alias the gem object part. It's a bit unfortunate that the
struct ttm_buffer_ojbect embeds a gem object since we otherwise could
make the TTM part private to the TTM backend, and use the usual
i915 gem object for the other ba
Use fast wc memcpy for reading out of wc memory for TTM bo moves.
Cc: Dave Airlie
Cc: Christian König
Cc: Daniel Vetter
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König #v4
--
v4:
- Clarify when we try drm_memcpy_from_wc_dbm (Reported by Matthew Auld)
- Be paranoid about when drm_
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free()
callbacks, that would cause problems with fault().
Instead, implement a method mapping page-b
Reading out of write-combining mapped memory is typically very slow
since the CPU doesn't prefetch. However some archs have special
instructions to do this.
So add a best-effort memcpy_from_wc taking dma-buf-map pointer
arguments that attempts to use a fast prefetching memcpy and
otherwise falls b
If the bo is idle when calling ttm_bo_pipeline_gutting(), we unnecessarily
create a ghost object and push it out to delayed destroy.
Fix this by adding a path for idle, and document the function.
Also avoid having the bo end up in a bad state vulnerable to user-space
triggered kernel BUGs if the c
We are calling the eviction_valuable driver callback at eviction time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM backend needs the same functionality for swapout,
and that might actually be beneficial to other drivers as well.
Add an eviction_valuable call al
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