On Thu, 20 May 2021, Alex Deucher wrote:
> Applied. Thanks!
Thanks again Alex.
> On Thu, May 20, 2021 at 8:03 AM Lee Jones wrote:
> >
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c:99: warning: expecting prototype
> > for smuio_v13_0_sup
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of Chris
> Chiu
> Sent: perjantai 21. toukokuuta 2021 7.02
> To: Rafael J. Wysocki
> Cc: Brown, Len ; Karol Herbst ; Linux
> PM ; Linux PCI ;
> Westerberg, Mika ; Rafael J. Wysocki
> ; dri-devel ; Bjorn
> Helgaas
> ; intel-...@lists
Am 20.05.21 um 19:23 schrieb Jason Ekstrand:
[SNIP]
I'd argue then that making amdgpu poll semantics match those of other drivers
is a pre-requisite for the new ioctl, otherwise it seems unlikely that the
ioctl will be widely adopted.
This seems backwards, because that means useful improvem
Am 20.05.21 um 21:14 schrieb Daniel Vetter:
On Thu, May 20, 2021 at 9:04 PM Jason Ekstrand wrote:
On Thu, May 20, 2021 at 12:23 PM Jason Ekstrand wrote:
On Thu, May 20, 2021 at 5:50 AM Christian König
wrote:
Am 20.05.21 um 09:55 schrieb Daniel Vetter:
On Wed, May 19, 2021 at 5:48 PM Michel
Am 20.05.21 um 19:08 schrieb Daniel Vetter:
[SNIP]
AH! So we are basically telling the fence backend that we have just
missed an event we waited for.
So what we want to know is how long the frontend wanted to wait instead
of how long the backend took for rendering.
tbh I'm not sure the timesta
Am 20.05.21 um 21:00 schrieb Jason Ekstrand:
From: Christian König
Add a helper to iterate over all fences in a dma_fence_array object.
v2 (Jason Ekstrand)
- Return NULL from dma_fence_array_first if head == NULL. This matches
the iterator behavior of dma_fence_chain_for_each in that it
Am 20.05.21 um 17:09 schrieb Thomas Hellström:
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free()
callbacks, that would cause problems with fa
Am 20.05.21 um 17:09 schrieb Thomas Hellström:
Use fast wc memcpy for reading out of wc memory for TTM bo moves.
Cc: Dave Airlie
Cc: Christian König
Cc: Daniel Vetter
Signed-off-by: Thomas Hellström
Oh, yes I really wanted to have that in TTM for quite some time.
But I'm wondering if we s
Am 20.05.21 um 17:09 schrieb Thomas Hellström:
If the bo is idle when calling ttm_bo_pipeline_gutting(), we unnecessarily
create a ghost object and push it out to delayed destroy.
Fix this by adding a path for idle, and document the function.
Also avoid having the bo end up in a bad state vulner
We have this nice kerneldoc, but forgot to include it.
Signed-off-by: Daniel Vetter
Cc: Sumit Semwal
Cc: "Christian König"
Cc: linux-me...@vger.kernel.org
Cc: linaro-mm-...@lists.linaro.org
---
Documentation/driver-api/dma-buf.rst | 9 +
1 file changed, 9 insertions(+)
diff --git a/Do
Am 21.05.21 um 10:24 schrieb Daniel Vetter:
We have this nice kerneldoc, but forgot to include it.
Well I didn't forgot it, I just didn't had time to double check that it
is bug free :)
Signed-off-by: Daniel Vetter
Cc: Sumit Semwal
Cc: "Christian König"
Cc: linux-me...@vger.kernel.org
C
On 5/21/21 10:10 AM, Christian König wrote:
Am 20.05.21 um 17:09 schrieb Thomas Hellström:
Use fast wc memcpy for reading out of wc memory for TTM bo moves.
Cc: Dave Airlie
Cc: Christian König
Cc: Daniel Vetter
Signed-off-by: Thomas Hellström
Oh, yes I really wanted to have that in TTM
Swapping a ttm object which has no backend pages makes no sense.
Suggested-by: Christian König
Signed-off-by: xinhui pan
---
drivers/gpu/drm/ttm/ttm_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c
i
Am 20.05.21 um 23:38 schrieb Jason Ekstrand:
On Thu, May 20, 2021 at 10:46 AM Matthew Brost wrote:
On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote:
Am 19.05.21 um 18:51 schrieb Matthew Brost:
On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
Oh, yeah we call th
Am 21.05.21 um 10:31 schrieb xinhui pan:
Swapping a ttm object which has no backend pages makes no sense.
Suggested-by: Christian König
Signed-off-by: xinhui pan
Reviewed-by: Christian König
Going to add a CC: stable and pushing that to drm-misc-fixes in a minute.
---
drivers/gpu/drm/t
On 5/21/21 10:21 AM, Christian König wrote:
Am 20.05.21 um 17:09 schrieb Thomas Hellström:
If the bo is idle when calling ttm_bo_pipeline_gutting(), we
unnecessarily
create a ghost object and push it out to delayed destroy.
Fix this by adding a path for idle, and document the function.
Also
use pm_runtime_resume_and_get() to replace pm_runtime_get_sync and
pm_runtime_put_noidle.
Signed-off-by: Tian Tao
---
v2: drop unnecessary change about if condition.
---
drivers/gpu/drm/exynos/exynos_drm_mic.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu
Scheduler takes care of its own locking, dont worry. For everything else
there's reservation locking on each bo.
So seems to be entirely redundnant and just a bit in the way.
Signed-off-by: Daniel Vetter
Cc: Rob Herring
Cc: Tomeu Vizoso
Cc: Steven Price
Cc: Alyssa Rosenzweig
---
drivers/gpu
Docs for struct dma_resv are fairly clear:
"A reservation object can have attached one exclusive fence (normally
associated with write operations) or N shared fences (read
operations)."
https://dri.freedesktop.org/docs/drm/driver-api/dma-buf.html#reservation-objects
Furthermore a review across a
More consistency and prep work for the next patch.
Aside: I wonder whether we shouldn't just move this entire xarray
business into the scheduler so that not everyone has to reinvent the
same wheels. Cc'ing some scheduler people for this too.
Cc: "Christian König"
Cc: Luben Tuikov
Cc: Alex Deuch
No need to set it explicitly.
Signed-off-by: Daniel Vetter
Cc: Laurentiu Palcu
Cc: Lucas Stach
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: Philipp Zabel
Cc: Paul Cercueil
Cc: Chun-Kuang Hu
Cc: Matthias Brugger
Cc: Neil Armstrong
Currently this has no practial relevance I think because there's not
many who can pull off a setup with panfrost and another gpu in the
same system. But the rules are that if you're setting an exclusive
fence, indicating a gpu write access in the implicit fencing system,
then you need to wait for a
Like we have for the shadow helpers too, and roll it out to drivers.
Signed-off-by: Daniel Vetter
Cc: Dave Airlie
Cc: Thomas Zimmermann
Cc: Hans de Goede
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: David Airlie
Cc: Daniel Vetter
Cc: Tian Tao
Cc: Laurent Pinchart
---
drivers/gpu/drm/ast/
It's tedious to review this all the time, and my audit showed that
arcpgu actually forgot to set this.
Make this the default and stop worrying.
Again I sprinkled WARN_ON_ONCE on top to make sure we don't have
strange combinations of hooks: cleanup_fb without prepare_fb doesn't
make sense, and sin
There's a bunch of atomic drivers who don't do this quite correctly,
luckily most of them aren't in wide use or people would have noticed
the tearing.
By making this the default we avoid the constant audit pain and can
additionally remove a ton of lines from vfuncs for a bit more clarity
in smalle
I guess no one ever tried running omap together with lima or panfrost,
not even sure that's possible. Anyway for consistency, fix this.
Signed-off-by: Daniel Vetter
Cc: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm
Goes through all the drivers and deletes the default hook since it's
the default now.
Signed-off-by: Daniel Vetter
Cc: Joel Stanley
Cc: Andrew Jeffery
Cc: "Noralf Trønnes"
Cc: Linus Walleij
Cc: Emma Anholt
Cc: David Lechner
Cc: Kamlesh Gurudasani
Cc: Oleksandr Andrushchenko
Cc: Daniel Vet
All they do is refcount the fb, which the atomic helpers already do.
This is was necessary with the legacy helpers and I guess just carry
over in the conversion. drm_plane_state always has a full reference
for its ->fb pointer during its entire lifetime,
see __drm_atomic_helper_plane_destroy_state
Spotted while trying to convert panfrost to these.
Signed-off-by: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
---
drivers/gpu/drm/drm_gem.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/drm_gem.c b/d
Am Freitag, dem 21.05.2021 um 11:09 +0200 schrieb Daniel Vetter:
> Scheduler takes care of its own locking, dont worry. For everything else
> there's reservation locking on each bo.
>
> So seems to be entirely redundnant and just a bit in the way.
I haven't read all the surrounding code, but this
在 2021/5/21 17:09, Daniel Vetter 写道:
Like we have for the shadow helpers too, and roll it out to drivers.
Signed-off-by: Daniel Vetter
Cc: Dave Airlie
Cc: Thomas Zimmermann
Cc: Hans de Goede
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: David Airlie
Cc: Daniel Vetter
Cc: Tian Tao
Cc: La
On Thu, May 20, 2021 at 9:15 PM Daniel Vetter wrote:
>
> On Thu, May 20, 2021 at 9:04 PM Jason Ekstrand wrote:
> >
> > On Thu, May 20, 2021 at 12:23 PM Jason Ekstrand
> > wrote:
> > >
> > > On Thu, May 20, 2021 at 5:50 AM Christian König
> > > wrote:
> > > >
> > > > Am 20.05.21 um 09:55 schrie
Make sure all bo->base.pages entries are either NULL or pointing to a
valid page before calling drm_gem_shmem_put_pages().
Reported-by: Tomeu Vizoso
Cc:
Fixes: 187d2929206e ("drm/panfrost: Add support for GPU heap allocations")
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/panfrost/panfro
Am Freitag, dem 21.05.2021 um 11:09 +0200 schrieb Daniel Vetter:
> No need to set it explicitly.
>
> Signed-off-by: Daniel Vetter
> Cc: Laurentiu Palcu
> Cc: Lucas Stach
For dcss and imx-drm:
Acked-by: Lucas Stach
> Cc: Shawn Guo
> Cc: Sascha Hauer
> Cc: Pengutronix Kernel Team
> Cc: Fabi
On Tue, 10 Nov 2020 at 03:49, John Stultz wrote:
> Hey All,
> So just wanted to send my last revision of my patch series
> of performance optimizations to the dma-buf system heap.
>
> This series reworks the system heap to use sgtables, and then
> consolidates the pagelist method from the heap-
On Fri, May 21, 2021 at 11:10 AM Daniel Vetter wrote:
>
> Docs for struct dma_resv are fairly clear:
>
> "A reservation object can have attached one exclusive fence (normally
> associated with write operations) or N shared fences (read
> operations)."
>
> https://dri.freedesktop.org/docs/drm/drive
Eliminate the follow smatch warning:
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++---
1 file changed, 6 insertions(+), 7 d
Add bindings for Snapdragon DisplayPort controller driver.
Signed-off-by: Chandan Uddaraju
Signed-off-by: Vara Reddy
Signed-off-by: Tanmay Shah
Signed-off-by: Kuogee Hsieh
Signed-off-by: Krishna Manikandan
Changes in V2:
-Provide details about sel-gpio
Changes in V4:
-Provide details about
MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema
for DPU device tree bindings.
Signed-off-by: Krishna Manikandan
Changes in v2:
- Changed dpu to DPU (Sam Ravnborg)
- Fixed indentation issues (Sam Ravnborg)
- Added empty
Add YAML schema for the device tree bindings for DSI
Signed-off-by: Krishna Manikandan
Changes in v1:
- Separate dsi controller bindings to a separate patch (Stephen Boyd)
- Merge dsi-common-controller.yaml and dsi-controller-main.yaml to
a single file (Stephen Boyd)
- Drop sup
Add YAML schema for the device tree bindings for DSI PHY.
Signed-off-by: Krishna Manikandan
Changes in v1:
- Merge dsi-phy.yaml and dsi-phy-10nm.yaml (Stephen Boyd)
- Remove qcom,dsi-phy-regulator-ldo-mode (Stephen Boyd)
- Add clock cells properly (Stephen Boyd)
- Remove unnecessary
On 21/05/2021 10:38, Boris Brezillon wrote:
> Make sure all bo->base.pages entries are either NULL or pointing to a
> valid page before calling drm_gem_shmem_put_pages().
>
> Reported-by: Tomeu Vizoso
> Cc:
> Fixes: 187d2929206e ("drm/panfrost: Add support for GPU heap allocations")
> Signed-off
Am 21.05.21 um 11:09 schrieb Daniel Vetter:
Docs for struct dma_resv are fairly clear:
"A reservation object can have attached one exclusive fence (normally
associated with write operations) or N shared fences (read
operations)."
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2
Hi Vidya,
on which machines this would help? I see there's many vblanks already
being waited. There's igt_display_commit2 which probably will block and
even if it didn't there's igt_pipe_crc_collect_crc(..) where crc
calculation is started after flip and then get one crc before disabling
crc
On Tue, May 11, 2021 at 10:05:26AM +0300, Heikki Krogerus wrote:
> On Wed, May 05, 2021 at 06:24:07PM +0200, Hans de Goede wrote:
> > Hi All,
> >
> > Here is v3 of my patchset making DP over Type-C work on devices where the
> > Type-C controller does not drive the HPD pin on the GPU, but instead
>
On 19/05/2021 00:58, Matthew Brost wrote:
Add entry fpr i915 new parallel submission uAPI plan.
v2:
(Daniel Vetter):
- Expand logical order explaination
- Add dummy header
- Only allow N BBs in execbuf IOCTL
- Configure parallel submission per slot not per gem context
Cc: Tvrtko
On 20/05/2021 20:41, Daniel Vetter wrote:
On Thu, May 20, 2021 at 11:57:44AM +0100, Tvrtko Ursulin wrote:
On 20/05/2021 10:54, Daniel Vetter wrote:
On Wed, May 19, 2021 at 7:19 PM Matthew Brost wrote:
On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
On Tue, May 18, 2021 at
Hi Daniel,
Le ven., mai 21 2021 at 11:09:54 +0200, Daniel Vetter
a écrit :
No need to set it explicitly.
Signed-off-by: Daniel Vetter
Cc: Laurentiu Palcu
Cc: Lucas Stach
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: Philipp Zabel
Hi,
On Fri, 21 May 2021 at 10:10, Daniel Vetter wrote:
> Currently this has no practial relevance I think because there's not
> many who can pull off a setup with panfrost and another gpu in the
> same system. But the rules are that if you're setting an exclusive
> fence, indicating a gpu write a
On 20/05/2021 18:47, Daniel Vetter wrote:
On Thu, May 20, 2021 at 6:31 PM Christian König
wrote:
Yeah, having the timestamp is a good idea as well.
drm-driver: i915
I think we should rather add something like printing
file_operations->owner->name to the common fdinfo code.
This way we
Am 21.05.21 um 14:22 schrieb Daniel Stone:
Hi,
On Fri, 21 May 2021 at 10:10, Daniel Vetter wrote:
Currently this has no practial relevance I think because there's not
many who can pull off a setup with panfrost and another gpu in the
same system. But the rules are that if you're setting an exc
Am 21.05.21 um 14:26 schrieb Tvrtko Ursulin:
On 20/05/2021 18:47, Daniel Vetter wrote:
On Thu, May 20, 2021 at 6:31 PM Christian König
wrote:
Yeah, having the timestamp is a good idea as well.
drm-driver: i915
I think we should rather add something like printing
file_operations->owner-
pm_runtime_get_sync will increment pm usage counter even it failed.
Forgetting to putting operation will result in reference leak here.
Fix it by replacing it with pm_runtime_resume_and_get to keep usage
counter balanced.
Reported-by: Hulk Robot
Signed-off-by: Zou Wei
---
drivers/gpu/drm/bridge
Am Freitag, 21. Mai 2021, 11:09:54 CEST schrieb Daniel Vetter:
> No need to set it explicitly.
>
> Signed-off-by: Daniel Vetter
> Cc: Laurentiu Palcu
> Cc: Lucas Stach
> Cc: Shawn Guo
> Cc: Sascha Hauer
> Cc: Pengutronix Kernel Team
> Cc: Fabio Estevam
> Cc: NXP Linux Team
> Cc: Philipp Za
Display Stream Compression (DSC) compresses the display stream in host which
is later decoded by panel. This series enables this for Qualcomm msm driver.
This was tested on Google Pixel3 phone which use LGE SW43408 panel.
The changes include adding DT properties for DSC then hardware blocks suppor
We required a helper to create and set the dsc_dce_header, so add the
dsc_dce_header and API drm_dsc_dsi_pps_header_init
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/drm_dsc.c | 11 +++
include/drm/drm_dsc.h | 16
2 files changed, 27 insertions(+)
diff --git a/driv
DSC enables streams to be compressed before we send to panel. This
requires DSC enabled encoder and a panel to be present. So we add this
information in board DTS and find if DSC can be enabled and the
parameters required to configure DSC are added to binding document along
with example
Signed-off
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 26 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
DSC needs some configuration from device tree, add support to read and
store these params and add DSC structures in msm_drv
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 170 +
drivers/gpu/drm/msm/msm_drv.h | 32 ++
2 files changed, 202
In SDM845, DSC can be enabled by writing to pingpong block registers, so
add support for DSC in hw_pp
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14
2 files changed, 46 insertions(
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 26 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
In SDM845, DSC can be enabled by writing to pingpong block registers, so
add support for DSC in hw_pp
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14
2 files changed, 46 insertions(
DSC needs some configuration from device tree, add support to read and
store these params and add DSC structures in msm_drv
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 171 +
drivers/gpu/drm/msm/msm_drv.h | 32 ++
2 files changed, 203
This add the bits in RM to enable the DSC blocks
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 32 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
3 files changed, 34 insertions(+)
diff --git a/d
This add SDM845 DSC blocks into hw_catalog
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 22 +++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc_mode() to detect dsc
enabled and pass this to .setup_intf_cfg()
Signed-off-by: Vinod Koul
---
drivers/gpu/dr
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc_mode() to detect dsc
enabled and pass this to .setup_intf_cfg()
Signed-off-by: Vinod Koul
---
drivers/gpu/dr
When DSC is enabled in DT, we need to configure the encoder for DSC
configuration, calculate DSC parameters for the given timing.
This patch adds that support by adding dpu_encoder_prep_dsc() which is
invoked when DSC is enabled in DT
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions upto 4k. For more resolutions like 8k this won't
work.
Furthermore, we can use 1 DSC encoder in lesser resulutions, but that is
not power efficient according to Abhinav, so it is recommended to always
use
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/ms
When DSC is enabled, we need to pass the DSC parameters to panel driver
as well, so add a dsc parameter in panel and set it when DSC is enabled
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 5 +
include/drm/drm_panel.h| 7 +++
2 files changed, 12 insertio
On Mon, May 17, 2021 at 11:50:32AM +0300, Dan Carpenter wrote:
> There is a reversed if statement in this probe function so the driver is
> completely broken.
>
> Fixes: dc13cac4862c ("video: hgafb: fix potential NULL pointer dereference")
> Signed-off-by: Dan Carpenter
> ---
> drivers/video/fbd
On Fri, 21 May 2021 at 13:28, Christian König wrote:
> Am 21.05.21 um 14:22 schrieb Daniel Stone:
> > Yeah, the 'second-generation Valhall' GPUs coming later this year /
> > early next year are starting to get pretty weird. Firmware-mediated
> > job scheduling out of multiple queues, userspace hav
Am 21.05.21 um 14:54 schrieb Daniel Stone:
On Fri, 21 May 2021 at 13:28, Christian König wrote:
Am 21.05.21 um 14:22 schrieb Daniel Stone:
Yeah, the 'second-generation Valhall' GPUs coming later this year /
early next year are starting to get pretty weird. Firmware-mediated
job scheduling out
On Fri, May 21, 2021 at 7:50 AM Vinod Koul wrote:
>
> DSC enables streams to be compressed before we send to panel. This
> requires DSC enabled encoder and a panel to be present. So we add this
> information in board DTS and find if DSC can be enabled and the
> parameters required to configure DSC
Framebuffer devices that are registered by DRM drivers for fbdev emulation
have a "drmfb" suffix in their name. But makes them to be quite confusing
if a driver already has "drm" in its name:
$ cat /proc/fb
0 rockchipdrmdrmfb
$ cat /proc/fb
0 simpledrmdrmfb
Instead, let's just add a "-fb" suffix
On Fri, 21 May 2021 at 14:09, Christian König wrote:
> Am 21.05.21 um 14:54 schrieb Daniel Stone:
> > If you're curious, the interface definitions are in the csf/ directory
> > in the 'Bifrost kernel driver' r30p0 download you can get from the Arm
> > developer site. Unfortunately the exact semant
On 21-05-21, 08:18, Rob Herring wrote:
> On Fri, May 21, 2021 at 7:50 AM Vinod Koul wrote:
> >
> > DSC enables streams to be compressed before we send to panel. This
> > requires DSC enabled encoder and a panel to be present. So we add this
> > information in board DTS and find if DSC can be enabl
On Friday, May 21st, 2021 at 1:49 AM, Lyude Paul wrote:
> After considering Libera and OFTC as options, the board settled on
> recommending OFTC. The primary reason for this is because OFTC is
> associated with our parent foundation SPI, and has a long and well known
> history of involvement with
Am 21.05.21 um 11:50 schrieb Jiapeng Chong:
Eliminate the follow smatch warning:
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
Reviewed-by: Christian König
---
drivers/gpu/dr
On 5/21/21 4:09 AM, Daniel Vetter wrote:
Goes through all the drivers and deletes the default hook since it's
the default now.
Acked-by: David Lechner
On Fri, May 21, 2021 at 6:50 AM Vinod Koul wrote:
>
> Display Stream Compression (DSC) compresses the display stream in host which
> is later decoded by panel. This series enables this for Qualcomm msm driver.
> This was tested on Google Pixel3 phone which use LGE SW43408 panel.
>
> The changes in
Den 21.05.2021 11.09, skrev Daniel Vetter:
> Goes through all the drivers and deletes the default hook since it's
> the default now.
>
> Signed-off-by: Daniel Vetter
Acked-by: Noralf Trønnes
Indeed, a lot of communities are moving to Libera. However,
centralization is what caused the mess with freenode in the first place,
thus communities spreading to different services may not be such a bad
idea. As long as the channels themselves are not split, that is.
On 21/05/2021 15:33, Simo
On Fri, May 21, 2021 at 09:43:59AM +0200, Christian König wrote:
> Am 20.05.21 um 19:08 schrieb Daniel Vetter:
> > [SNIP]
> > > AH! So we are basically telling the fence backend that we have just
> > > missed an event we waited for.
> > >
> > > So what we want to know is how long the frontend want
Hello Juha-Pekka
We are seeing the CRC failures on Jasperlake systems. Sometimes the test passes
and sometimes it fails throwing CRC error.
Regards
Vidya
-Original Message-
From: Juha-Pekka Heikkila
Sent: Friday, May 21, 2021 5:00 PM
To: Srinivas, Vidya ;
intel-...@lists.freedesktop.
On Fri, May 21, 2021 at 11:46:23AM +0200, Bas Nieuwenhuizen wrote:
> On Fri, May 21, 2021 at 11:10 AM Daniel Vetter wrote:
> >
> > Docs for struct dma_resv are fairly clear:
> >
> > "A reservation object can have attached one exclusive fence (normally
> > associated with write operations) or N sha
On Fri 21 May 07:49 CDT 2021, Vinod Koul wrote:
> DSC enables streams to be compressed before we send to panel. This
> requires DSC enabled encoder and a panel to be present. So we add this
> information in board DTS and find if DSC can be enabled and the
> parameters required to configure DSC are
On Fri, May 21, 2021 at 11:32:48AM +0200, Lucas Stach wrote:
> Am Freitag, dem 21.05.2021 um 11:09 +0200 schrieb Daniel Vetter:
> > Scheduler takes care of its own locking, dont worry. For everything else
> > there's reservation locking on each bo.
> >
> > So seems to be entirely redundnant and ju
On Fri, May 21, 2021 at 2:10 AM Daniel Vetter wrote:
>
> - msm is mildly entertaining. It also supports MSM_SUBMIT_NO_IMPLICIT,
> but because it doesn't use the drm/scheduler it handles fences from
> the wrong context with a synchronous dma_fence_wait. See
> submit_fence_sync() leading to ms
On Fri, May 21, 2021 at 07:58:57AM -0700, Rob Clark wrote:
> On Fri, May 21, 2021 at 2:10 AM Daniel Vetter wrote:
> >
> > - msm is mildly entertaining. It also supports MSM_SUBMIT_NO_IMPLICIT,
> > but because it doesn't use the drm/scheduler it handles fences from
> > the wrong context with a
On Fri, May 21, 2021 at 4:37 PM Daniel Vetter wrote:
>
> On Fri, May 21, 2021 at 11:46:23AM +0200, Bas Nieuwenhuizen wrote:
> > On Fri, May 21, 2021 at 11:10 AM Daniel Vetter
> > wrote:
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 del
The first parameter passed to container_of() is the pointer to the work
structure passed to the worker and never NULL. The NULL check on the
result of container_of() is therefore unnecessary and misleading.
Remove it.
This change was made automatically with the following Coccinelle script.
@@
typ
On Fri, May 21, 2021 at 11:10:57AM +0200, Daniel Vetter wrote:
> Spotted while trying to convert panfrost to these.
>
> Signed-off-by: Daniel Vetter
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Thomas Zimmermann
> Cc: David Airlie
> Cc: Daniel Vetter
Cc: Emma Anholt
As original autho
On 5/21/21 12:09 PM, Daniel Vetter wrote:
> Goes through all the drivers and deletes the default hook since it's
> the default now.
>
> Signed-off-by: Daniel Vetter
Acked-by: Oleksandr Andrushchenko
On Fri, May 21, 2021 at 05:00:46PM +0200, Bas Nieuwenhuizen wrote:
> On Fri, May 21, 2021 at 4:37 PM Daniel Vetter wrote:
> >
> > On Fri, May 21, 2021 at 11:46:23AM +0200, Bas Nieuwenhuizen wrote:
> > > On Fri, May 21, 2021 at 11:10 AM Daniel Vetter
> > > wrote:
> > > > ---
> > > > drivers/gpu/
On Fri, May 21, 2021 at 10:26:28AM +0200, Christian König wrote:
> Am 21.05.21 um 10:24 schrieb Daniel Vetter:
> > We have this nice kerneldoc, but forgot to include it.
>
> Well I didn't forgot it, I just didn't had time to double check that it is
> bug free :)
It does seem to generate decent lo
On Fri, May 21, 2021 at 06:19:30PM +0530, Vinod Koul wrote:
> We required a helper to create and set the dsc_dce_header, so add the
> dsc_dce_header and API drm_dsc_dsi_pps_header_init
>
> Signed-off-by: Vinod Koul
> ---
> drivers/gpu/drm/drm_dsc.c | 11 +++
> include/drm/drm_dsc.h |
On Fri, May 21, 2021 at 05:06:06PM +0800, Tian Tao wrote:
> use pm_runtime_resume_and_get() to replace pm_runtime_get_sync and
> pm_runtime_put_noidle.
It would be good to explain why: Apparently get_sync increments the
refcount even if it fails, which ususally leads to leaks.
With that or simila
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