Lee,
> This set is part of a larger effort attempting to clean-up W=1 kernel
> builds, which are currently overwhelmingly riddled with niggly little
> warnings.
Applied everything but patch 29 to 5.13/scsi-staging, thanks!
--
Martin K. Petersen Oracle Linux Engineering
__
[AMD Public Use]
Ping
-Original Message-
From: Zhang, Jack (Jian)
Sent: Monday, March 15, 2021 1:24 PM
To: Jack Zhang ; dri-devel@lists.freedesktop.org;
amd-...@lists.freedesktop.org; Koenig, Christian ;
Grodzovsky, Andrey ; Liu, Monk ;
Deng, Emily ; Rob Herring ; Tomeu Vizoso
; Stev
Hi,
It's been a fairly quiet week, but here are the changes for drm-misc-next
Thanks!
Maxime
drm-misc-next-2021-03-16:
drm-misc-next for 5.13:
UAPI Changes:
- Documentation for the DRM_CAP_* defines
Cross-subsystem Changes:
Core Changes:
- dma-fence: More documentation for the recoverable
Hi Jason,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tegra-drm/drm/tegra/for-next]
[also build test ERROR on linus/master v5.12-rc3 next-20210316]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to
Fix the following coccicheck warnings:
./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c:721:65-70: WARNING:
conversion to bool not needed here.
./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c:1139:67-72: WARNING:
conversion to bool not needed here.
Reported-by: Abaci Robot
Signed-off-by: J
On 2021-03-16 12:10 a.m., Jason Ekstrand wrote:
> On Mon, Mar 15, 2021 at 4:05 PM Jason Ekstrand wrote:
>>
>> Modern userspace APIs like Vulkan are built on an explicit
>> synchronization model. This doesn't always play nicely with the
>> implicit synchronization used in the kernel and assumed by
Hi!
On Tue, Mar 09, 2021 at 06:08:49PM +0100, Noralf Trønnes wrote:
> Hi drm-misc maintainers,
>
> I have this series:
>
> GUD USB Display driver
> https://patchwork.freedesktop.org/series/87044/#rev3
>
> That depends on this drm-misc-fixes commit:
>
> 3a3fe21242a3 ("drm: Use USB controller's
On Mon, Mar 15, 2021 at 08:00:30PM +0100, Thomas Hellström (Intel) wrote:
>
> On 3/15/21 7:47 PM, Christian König wrote:
> >
> >
> > Am 15.03.21 um 18:08 schrieb Thomas Hellström (Intel):
> > >
> > > On 3/15/21 11:26 AM, Christian König wrote:
> > > >
> > > >
> > > > Am 13.03.21 um 19:29 schr
On Fri, Mar 12, 2021 at 05:10:43PM +0100, Dmitry Vyukov wrote:
> On Fri, Mar 12, 2021 at 3:22 PM Daniel Vetter wrote:
> >
> > On Fri, Mar 12, 2021 at 11:46:27AM +0100, Dmitry Vyukov wrote:
> > > On Fri, Mar 12, 2021 at 11:26 AM syzbot
> > > wrote:
> > > >
> > > > Hello,
> > > >
> > > > syzbot fou
On Fri, Mar 12, 2021 at 03:50:35PM +0100, Christian König wrote:
> Am 12.03.21 um 15:36 schrieb Daniel Vetter:
> > On Fri, Mar 12, 2021 at 03:35:50PM +0100, Daniel Vetter wrote:
> > > On Fri, Mar 12, 2021 at 03:27:58PM +0100, Christian König wrote:
> > > >
> > > > Am 12.03.21 um 15:04 schrieb Dani
On Mon, Mar 15, 2021 at 05:04:22PM +0100, Christian König wrote:
> Instead of having a global lock.
>
> Signed-off-by: Christian König
I guess per zone lru lock is a lot more work since then we need to handle
ordering and ABBA deadlocks? s/zone/mem region/ I think is the proper ttm
lingo.
-Danie
On Mon, 15 Mar 2021 at 19:14, Christian König
wrote:
>
> Remove the unused evict parameter and drop swapping bo->mem.
>
> Signed-off-by: Christian König
For the series,
Reviewed-by: Matthew Auld
___
dri-devel mailing list
dri-devel@lists.freedesktop.o
On Mon, Mar 15, 2021 at 05:37:27PM +, Tvrtko Ursulin wrote:
>
> On 12/03/2021 15:46, Tvrtko Ursulin wrote:
> > From: Chris Wilson
> >
> > Currently, we cancel outstanding requests within a context when the
> > context is closed. We may also want to cancel individual requests using
> > the sa
On Fri, Mar 12, 2021 at 03:46:22PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Module parameter is added (request_timeout_ms) to allow configuring the
> default request/fence expiry.
>
> Default value is inherited from CONFIG_DRM_I915_REQUEST_TIMEOUT.
>
> Signed-off-by: Tvrtko Ursul
On Fri, Mar 12, 2021 at 03:46:20PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Idea here is to make the watchdog mechanism more useful than for just
> default request/fence expiry.
>
> To this effect a new context param I915_CONTEXT_PARAM_WATCHDOG is added
> where the value fields al
On Fri, Mar 12, 2021 at 03:46:21PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> A new Kconfig option CONFIG_DRM_I915_REQUEST_TIMEOUT is added, defaulting
> to 10s, and this timeout is applied to _all_ contexts using the previously
> added watchdog facility.
>
> Result of this is that
Den 16.03.2021 10.08, skrev Maxime Ripard:
> Hi!
>
> On Tue, Mar 09, 2021 at 06:08:49PM +0100, Noralf Trønnes wrote:
>> Hi drm-misc maintainers,
>>
>> I have this series:
>>
>> GUD USB Display driver
>> https://patchwork.freedesktop.org/series/87044/#rev3
>>
>> That depends on this drm-misc-fix
Hi,
On 3/16/21 10:27 AM, Daniel Vetter wrote:
On Mon, Mar 15, 2021 at 08:00:30PM +0100, Thomas Hellström (Intel) wrote:
On 3/15/21 7:47 PM, Christian König wrote:
Am 15.03.21 um 18:08 schrieb Thomas Hellström (Intel):
On 3/15/21 11:26 AM, Christian König wrote:
Am 13.03.21 um 19:29 schrieb
On Tue, Mar 16, 2021 at 11:38:53AM +0100, Thomas Hellström (Intel) wrote:
> Hi,
>
> On 3/16/21 10:27 AM, Daniel Vetter wrote:
> > On Mon, Mar 15, 2021 at 08:00:30PM +0100, Thomas Hellström (Intel) wrote:
> > > On 3/15/21 7:47 PM, Christian König wrote:
> > > >
> > > > Am 15.03.21 um 18:08 schrieb
On 3/16/21 12:06 PM, Daniel Vetter wrote:
On Tue, Mar 16, 2021 at 11:38:53AM +0100, Thomas Hellström (Intel) wrote:
Hi,
On 3/16/21 10:27 AM, Daniel Vetter wrote:
On Mon, Mar 15, 2021 at 08:00:30PM +0100, Thomas Hellström (Intel) wrote:
On 3/15/21 7:47 PM, Christian König wrote:
Am 15.03.21
Ping.
Any comment on this patch?
Thanks,
Quanyang
On 3/10/21 12:59 PM, quanyang.w...@windriver.com wrote:
From: Quanyang Wang
The Runtime PM subsystem will force the device "fd4a.zynqmp-display"
to enter suspend state while booting if the following conditions are met:
- the usage counte
Am 16.03.21 um 10:35 schrieb Daniel Vetter:
On Mon, Mar 15, 2021 at 05:04:22PM +0100, Christian König wrote:
Instead of having a global lock.
Signed-off-by: Christian König
I guess per zone lru lock is a lot more work since then we need to handle
ordering and ABBA deadlocks? s/zone/mem region
On Tue, Mar 16, 2021 at 1:03 PM Christian König
wrote:
>
> Am 16.03.21 um 10:35 schrieb Daniel Vetter:
> > On Mon, Mar 15, 2021 at 05:04:22PM +0100, Christian König wrote:
> >> Instead of having a global lock.
> >>
> >> Signed-off-by: Christian König
> > I guess per zone lru lock is a lot more wo
Den 13.03.2021 12.25, skrev Noralf Trønnes:
> Hi,
>
> A while back I had the idea to turn a Raspberry Pi Zero into a $5
> USB to HDMI/SDTV/DPI display adapter.
>
> The protocol is open so people are free to make displays implementing it and
> use this driver, all that's needed is to add a USB v
On 2021-03-15 08:33, Christoph Hellwig wrote:
On Fri, Mar 12, 2021 at 04:18:24PM +, Robin Murphy wrote:
Let me know what you think of the version here:
http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/iommu-cleanup
I'll happily switch the patch to you as the author if you're
On 14/03/2021 04:15, Laurent Pinchart wrote:
Hi Junlin,
Thank you for the patch.
On Fri, Mar 12, 2021 at 03:14:45PM +0800, angkery wrote:
From: Junlin Yang
r is "u32" always >= 0,mipi_dsi_create_packet may return little than zero.
so r < 0 condition is never accessible.
Fixes coccicheck war
On Tue, Mar 16, 2021 at 12:24 PM Thomas Hellström (Intel)
wrote:
>
>
> On 3/16/21 12:06 PM, Daniel Vetter wrote:
> > On Tue, Mar 16, 2021 at 11:38:53AM +0100, Thomas Hellström (Intel) wrote:
> >> Hi,
> >>
> >> On 3/16/21 10:27 AM, Daniel Vetter wrote:
> >>> On Mon, Mar 15, 2021 at 08:00:30PM +0100
Hi Sebastian, Sam, Thierry,
On 27/02/2021 23:45, Sebastian Reichel wrote:
From: Sebastian Reichel
Disable TE for Droid 4 panel, since implementation is currently
broken. Also disable it for N950 panel, which is untested.
Reported-by: Tony Lindgren
Reported-by: Tomi Valkeinen
Fixes: 4c1b935f
On Tue, Mar 16, 2021 at 3:51 AM Michel Dänzer wrote:
>
> On 2021-03-16 12:10 a.m., Jason Ekstrand wrote:
> > On Mon, Mar 15, 2021 at 4:05 PM Jason Ekstrand wrote:
> >>
> >> Modern userspace APIs like Vulkan are built on an explicit
> >> synchronization model. This doesn't always play nicely with
Am 16.03.21 um 13:05 schrieb Daniel Vetter:
On Tue, Mar 16, 2021 at 1:03 PM Christian König
wrote:
Am 16.03.21 um 10:35 schrieb Daniel Vetter:
On Mon, Mar 15, 2021 at 05:04:22PM +0100, Christian König wrote:
Instead of having a global lock.
Signed-off-by: Christian König
I guess per zone
Hi all,
This are the leftovers from my pull that landed in 5.12:
https://lore.kernel.org/dri-devel/CAKMK7uHQ=6ojcrgucutib456rwdcfwsnexv8pqsfspodtj6...@mail.gmail.com/
Only changes compared to the old submission are:
- dropped vfio and kvm patch
- add patch to just remove follow_pfn at the end
A
Way back it was a reasonable assumptions that iomem mappings never
change the pfn range they point at. But this has changed:
- gpu drivers dynamically manage their memory nowadays, invalidating
ptes with unmap_mapping_range when buffers get moved
- contiguous dma allocations have moved from dedic
The media model assumes that buffers are all preallocated, so that
when a media pipeline is running we never miss a deadline because the
buffers aren't allocated or available.
This means we cannot fix the v4l follow_pfn usage through
mmu_notifier, without breaking how this all works. The only real
Both kvm (in bd2fae8da794 ("KVM: do not assume PTE is writable after
follow_pfn")) and vfio (in 07956b6269d3 ("vfio/type1: Use
follow_pte()")) have lost their callsites of follow_pfn(). All the
other ones have been switched over to unsafe_follow_pfn because they
cannot be fixed without breaking use
On Tue, Mar 16, 2021 at 4:46 PM Christoph Hellwig wrote:
>
> On Tue, Mar 16, 2021 at 04:33:02PM +0100, Daniel Vetter wrote:
> > The media model assumes that buffers are all preallocated, so that
> > when a media pipeline is running we never miss a deadline because the
> > buffers aren't allocated
From: Tvrtko Ursulin
"Watchdog" aka "restoring hangcheck" aka default request/fence expiry - second
post of a somewhat controversial feature, now upgraded to patch status.
I quote the "watchdog" becuase in classical sense watchdog would allow userspace
to ping it and so remain alive.
I quote "r
From: Tvrtko Ursulin
Disallow sentinel requests follow previous sentinels to make request
cancellation work better when faced with a chain of requests which have
all been marked as in error.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
1 file c
From: Chris Wilson
Currently, we cancel outstanding requests within a context when the
context is closed. We may also want to cancel individual requests using
the same graceful preemption mechanism.
v2 (Tvrtko):
* Cancel waiters carefully considering no timeline lock and RCU.
* Fixed selftests
From: Tvrtko Ursulin
With the watchdog cancelling requests asynchronously to preempt-to-busy we
need to relax one assert making it apply only to requests not in error.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 -
1 file changed, 4 insertions
From: Tvrtko Ursulin
Prepares the plumbing for setting request/fence expiration time. All code
is put in place but is never activeted due yet missing ability to actually
configure the timer.
Outline of the basic operation:
A timer is started when request is ready for execution. If the request
c
From: Tvrtko Ursulin
A new Kconfig option CONFIG_DRM_I915_REQUEST_TIMEOUT is added, defaulting
to 12s, and this timeout is applied to all users contexts using the
previously added watchdog facility.
Result of this is that any user submission will simply fail after this
timeout, either causing a
From: Tvrtko Ursulin
Module parameter is added (request_timeout_ms) to allow configuring the
default request/fence expiry.
Default value is inherited from CONFIG_DRM_I915_REQUEST_TIMEOUT.
Signed-off-by: Tvrtko Ursulin
Cc: Daniel Vetter
Acked-by: Daniel Vetter
---
drivers/gpu/drm/i915/gem/i9
Hi Dave & Daniel -
drm-intel-next-2021-03-16:
Highlights:
- Alderlake S enabling, via topic branch (Aditya, Anusha, Caz, José, Lucas,
Matt, Tejas)
- Refactor display code to shrink intel_display.c etc. (Dave)
- Support more gen 9 and Tigerlake PCH combinations (Lyude, Tejas)
- Add eDP MSO suppor
On Wed, Feb 3, 2021 at 2:14 PM Rob Clark wrote:
>
> On Wed, Feb 3, 2021 at 1:46 PM Will Deacon wrote:
> >
> > On Tue, Feb 02, 2021 at 11:56:27AM +0530, Sai Prakash Ranjan wrote:
> > > On 2021-02-01 23:50, Jordan Crouse wrote:
> > > > On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
> >
On Tue, Mar 16, 2021 at 10:04 AM Rob Clark wrote:
>
> On Wed, Feb 3, 2021 at 2:14 PM Rob Clark wrote:
> >
> > On Wed, Feb 3, 2021 at 1:46 PM Will Deacon wrote:
> > >
> > > On Tue, Feb 02, 2021 at 11:56:27AM +0530, Sai Prakash Ranjan wrote:
> > > > On 2021-02-01 23:50, Jordan Crouse wrote:
> > >
Correction, we have 7 candidates for 4 positions.
I seem to have overlooked Walter Harms's nomination email. My sincerest
apologies. His personal affiliation, statement of contribution, and
personal statement are below.
The full slate of candidates can be found at
https://wiki.freedesktop.or
On 3/16/21 3:07 PM, Daniel Vetter wrote:
On Tue, Mar 16, 2021 at 12:24 PM Thomas Hellström (Intel)
wrote:
On 3/16/21 12:06 PM, Daniel Vetter wrote:
On Tue, Mar 16, 2021 at 11:38:53AM +0100, Thomas Hellström (Intel) wrote:
Hi,
On 3/16/21 10:27 AM, Daniel Vetter wrote:
On Mon, Mar 15, 2021
https://bugzilla.kernel.org/show_bug.cgi?id=212293
--- Comment #3 from Sefa Eyeoglu (cont...@scrumplex.net) ---
This took some time, as I apparently went wrong paths sometimes.
Anyways.
I bisected between tags v5.10 (good) and v5.11 (bad), while only looking at
path "drivers/gpu/drm/amd".
At th
https://bugzilla.kernel.org/show_bug.cgi?id=212293
--- Comment #4 from Sefa Eyeoglu (cont...@scrumplex.net) ---
Created attachment 295887
--> https://bugzilla.kernel.org/attachment.cgi?id=295887&action=edit
git bisect log
--
You may reply to this email to add a comment.
You are receiving this
https://bugzilla.kernel.org/show_bug.cgi?id=212293
--- Comment #5 from Sefa Eyeoglu (cont...@scrumplex.net) ---
I was unable to add Simon Ser to CC
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On Tue, Mar 16, 2021 at 7:18 PM Thomas Hellström (Intel)
wrote:
>
>
> On 3/16/21 3:07 PM, Daniel Vetter wrote:
> > On Tue, Mar 16, 2021 at 12:24 PM Thomas Hellström (Intel)
> > wrote:
> >>
> >> On 3/16/21 12:06 PM, Daniel Vetter wrote:
> >>> On Tue, Mar 16, 2021 at 11:38:53AM +0100, Thomas Hellst
On 3/16/21 7:28 PM, Daniel Vetter wrote:
On Tue, Mar 16, 2021 at 7:18 PM Thomas Hellström (Intel)
wrote:
On 3/16/21 3:07 PM, Daniel Vetter wrote:
On Tue, Mar 16, 2021 at 12:24 PM Thomas Hellström (Intel)
wrote:
On 3/16/21 12:06 PM, Daniel Vetter wrote:
On Tue, Mar 16, 2021 at 11:38:53AM +
https://bugzilla.kernel.org/show_bug.cgi?id=212293
--- Comment #6 from Sefa Eyeoglu (cont...@scrumplex.net) ---
Okay I tried to debug it by printing.
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 573cf17262da..8e6b890ad611
Den 15.03.2021 20.37, skrev Peter Stuge:
> Hi Noralf,
>
> super fair call with the BE testing, let's hope for some testing soonish.
>
>
> I was thinking about my device doing protocol STALL when I try to
> return 0 bytes, and while it *is* a bug in my device, from a standards
> point of view i
Hi Quanyang,
Thank you for the patch.
On Wed, Mar 10, 2021 at 12:59:45PM +0800, quanyang.w...@windriver.com wrote:
> From: Quanyang Wang
>
> The Runtime PM subsystem will force the device "fd4a.zynqmp-display"
> to enter suspend state while booting if the following conditions are met:
> - t
This adds an entry to simple panel for the timings of a panel that
might be attached to the board sc7180-trogdor-pompom.
As talked about in the previous patch ("dt-bindings: display: simple:
Add the panel on sc7180-trogdor-pompom") any number of panels might be
attached. These panels might have di
The sc7180-trogdor-pompom board might be attached to any number of a
pile of eDP panels. At the moment I'm told that the list might include:
- KD KD116N21-30NV-A010
- KD KD116N09-30NH-A016
- Starry 2081116HHD028001-51D
- Sharp LQ116M1JW10
It should be noted that while the EDID programmed in the fi
As talked about in the previous patch ("dt-bindings: display: simple:
Add the panel on sc7180-trogdor-pompom") any number of panels might be
attached.
Let's stop specifying a single panel and just specify that we have a
"pompom panel".
Signed-off-by: Douglas Anderson
---
Before landing this we n
On Tue, Mar 9, 2021 at 10:14 AM Pekka Paalanen wrote:
>
> On Mon, 8 Mar 2021 16:52:58 -0800
> "Navare, Manasi" wrote:
>
> > On Thu, Mar 04, 2021 at 10:42:23AM +0200, Pekka Paalanen wrote:
> > > On Wed, 3 Mar 2021 12:44:33 -0800
> > > "Navare, Manasi" wrote:
> > >
> > > > On Wed, Mar 03, 2021 at
Hi Doug,
On Mon, Mar 15, 2021 at 09:25:37AM -0700, Doug Anderson wrote:
> On Sat, Mar 13, 2021 at 1:17 PM Laurent Pinchart wrote:
> > On Thu, Mar 04, 2021 at 03:52:01PM -0800, Douglas Anderson wrote:
> > > In commit 58074b08c04a ("drm/bridge: ti-sn65dsi86: Read EDID blob over
> > > DDC") we attemp
On Mon, Mar 08, 2021 at 03:03:58PM +0100, Sebastian Reichel wrote:
> Hi,
>
> On Sat, Mar 06, 2021 at 11:56:45AM -0800, Rob Herring wrote:
> > On Tue, Feb 23, 2021 at 02:26:57AM +0100, Sebastian Reichel wrote:
> > > On Mon, Feb 22, 2021 at 10:26:26PM +0100, Alexandre Belloni wrote:
> > > > On 22/02
This is a permanent workaround for TGL,RKL,DG1 and ADLS.
Signed-off-by: Swathi Dhanavanthri
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 23 +
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/in
On Wed, Mar 10, 2021 at 05:55:31PM +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qm/qxp Control and Status Registers module.
>
> Signed-off-by: Liu Ying
> ---
> v4->v5:
> * Newly introduced in v5. (Rob)
>
> .../devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml | 202
> +++
On Wed, 10 Mar 2021 17:55:32 +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
>
> Signed-off-by: Liu Ying
> ---
> v4->v5:
> * No change.
>
> v3->v4:
> * Add 'fsl,sc-resource' property. (Rob)
>
> v2->v3:
> * Drop 'fsl,syscon' property. (Rob)
> * Mention
15.03.2021 21:39, Dmitry Osipenko пишет:
>>> + /*
>>> +* Horizontal downscale needs a lower memory latency, which roughly
>>> +* depends on the scaled width. Trying to tune latency of a memory
>>> +* client alone will likely result in a strong negative impact on
>>> +* other memo
[CC trimmed - excluded Marek]
Too bad Jan,
'configure' works, now. But compilation brakes after that.
How can we add '-cl-no-stdinc' only to CMAKE_CLC_FLAGS and NOT CXX flags
(see below)?
Tried
libclc/build> pwd
/opt/llvm-project/libclc/build
libclc/build> cmake ../ -DLLVM_CONFIG=/usr/loca
On Tue, 16 Mar 2021 at 21:35, Daniel Vetter wrote:
> On Tue, Mar 9, 2021 at 10:14 AM Pekka Paalanen
> wrote:
> > On Mon, 8 Mar 2021 16:52:58 -0800
> > "Navare, Manasi" wrote:
> > > Hmm well after the actual real commit, since the second crtc is stolen
> > > even though it is not being used for
This is a permanent workaround for TGL,RKL,DG1 and ADLS.
Signed-off-by: Swathi Dhanavanthri
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 +
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/in
Hi,
On Tue, Mar 16, 2021 at 2:46 PM Laurent Pinchart
wrote:
>
> Hi Doug,
>
> On Mon, Mar 15, 2021 at 09:25:37AM -0700, Doug Anderson wrote:
> > On Sat, Mar 13, 2021 at 1:17 PM Laurent Pinchart wrote:
> > > On Thu, Mar 04, 2021 at 03:52:01PM -0800, Douglas Anderson wrote:
> > > > In commit 58074b0
From: Qingqing Zhuo
[ Upstream commit 7afa0033d6f7fb8a84798ef99d1117661c4e696c ]
[Why]
pflip interrupt would not be enabled promptly if a pipe is disabled
and re-enabled, causing flip_done timeout error during DP
compliance tests
[How]
Enable pflip interrupt upon pipe enablement
Tested-by: Dan
From: Sung Lee
[ Upstream commit b0075d114c33580f5c9fa9cee8e13d06db41471b ]
[WHY & HOW]
Using values provided by DF for latency may cause hangs in
multi display configurations. Revert change to previous value.
Tested-by: Daniel Wheeler
Signed-off-by: Sung Lee
Reviewed-by: Haonan Wang
Acked-b
From: Nirmoy Das
[ Upstream commit 521f04f9e3ffc73ef96c776035f8a0a31b4cdd81 ]
FB BO should not be ttm_bo_type_kernel type and
amdgpufb_create_pinned_object() pins the FB BO anyway.
Signed-off-by: Nirmoy Das
Acked-by: Christian König
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Zhan Liu
[ Upstream commit eda29602f1a8b2b32d8c8c354232d9d1ee1c064d ]
[Why]
For DGPU Navi, the wm_table.nv_entries are used. These entires are not
populated for DCN301 Vangogh APU, but instead wm_table.entries are.
[How]
Use DCN21 Renoir style wm calculations.
Signed-off-by: Leo Li
Sign
From: Christian König
[ Upstream commit cba2afb65cb05c3d197d17323fee4e3c9edef9cd ]
When AGP is compiled as module radeon must be compiled as module as
well.
Signed-off-by: Christian König
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/K
From: Dillon Varone
[ Upstream commit d2c91285958a3e77db99c352c136af4243f8f529 ]
[Why & How]
Ported logic from dcn21 for reading in pipe fusing to dcn30.
Supported configurations are 1 and 6 pipes. Invalid fusing
will revert to 1 pipe being enabled.
Tested-by: Daniel Wheeler
Signed-off-by: Dil
From: Sung Lee
[ Upstream commit b0075d114c33580f5c9fa9cee8e13d06db41471b ]
[WHY & HOW]
Using values provided by DF for latency may cause hangs in
multi display configurations. Revert change to previous value.
Tested-by: Daniel Wheeler
Signed-off-by: Sung Lee
Reviewed-by: Haonan Wang
Acked-b
From: Christian König
[ Upstream commit cba2afb65cb05c3d197d17323fee4e3c9edef9cd ]
When AGP is compiled as module radeon must be compiled as module as
well.
Signed-off-by: Christian König
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/K
From: Nirmoy Das
[ Upstream commit 521f04f9e3ffc73ef96c776035f8a0a31b4cdd81 ]
FB BO should not be ttm_bo_type_kernel type and
amdgpufb_create_pinned_object() pins the FB BO anyway.
Signed-off-by: Nirmoy Das
Acked-by: Christian König
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Sung Lee
[ Upstream commit b0075d114c33580f5c9fa9cee8e13d06db41471b ]
[WHY & HOW]
Using values provided by DF for latency may cause hangs in
multi display configurations. Revert change to previous value.
Tested-by: Daniel Wheeler
Signed-off-by: Sung Lee
Reviewed-by: Haonan Wang
Acked-b
From: Christian König
[ Upstream commit cba2afb65cb05c3d197d17323fee4e3c9edef9cd ]
When AGP is compiled as module radeon must be compiled as module as
well.
Signed-off-by: Christian König
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/K
From: Nirmoy Das
[ Upstream commit 521f04f9e3ffc73ef96c776035f8a0a31b4cdd81 ]
FB BO should not be ttm_bo_type_kernel type and
amdgpufb_create_pinned_object() pins the FB BO anyway.
Signed-off-by: Nirmoy Das
Acked-by: Christian König
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Christian König
[ Upstream commit cba2afb65cb05c3d197d17323fee4e3c9edef9cd ]
When AGP is compiled as module radeon must be compiled as module as
well.
Signed-off-by: Christian König
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/K
From: Christian König
[ Upstream commit cba2afb65cb05c3d197d17323fee4e3c9edef9cd ]
When AGP is compiled as module radeon must be compiled as module as
well.
Signed-off-by: Christian König
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/K
Quoting Maxime Ripard (2021-03-03 00:45:27)
> Hi Stephen,
>
> On Tue, Mar 02, 2021 at 03:18:58PM -0800, Stephen Boyd wrote:
> > Quoting Maxime Ripard (2021-02-25 07:59:02)
> > > Some devices might need to access the current available range of a clock
> > > to discover their capabilities. Let's add
On 3/15/21 6:35 PM, Thomas Hellström (Intel) wrote:
On 3/15/21 9:38 PM, Daniel Vetter wrote:
On Mon, Mar 15, 2021 at 6:57 PM Zack Rusin wrote:
On 3/12/21 5:06 AM, Thomas Hellström (Intel) wrote:
On 3/12/21 12:02 AM, Zack Rusin wrote:
On Mar 11, 2021, at 17:35, Thomas Hellström (Intel)
wrot
On Tue, 2021-03-16 at 16:38 -0600, Rob Herring wrote:
> On Wed, Mar 10, 2021 at 05:55:31PM +0800, Liu Ying wrote:
> > This patch adds bindings for i.MX8qm/qxp Control and Status Registers
> > module.
> >
> > Signed-off-by: Liu Ying
> > ---
> > v4->v5:
> > * Newly introduced in v5. (Rob)
> >
> >
Hi all,
After merging the drm tree, today's linux-next build (arm
multi_v7_defconfig) produced this warning:
drivers/gpu/drm/rockchip/rockchip_drm_vop.c: In function
'vop_plane_atomic_update':
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:882:26: warning: unused variable
'old_state' [-Wunused-var
After spending a non-negligible time trying to figure out why
dpu_kms_init() would dereference a NULL dpu_kms->pdev, it turns out that
in addition to adding the new compatible to the msm_drv of_match_table
one also need to teach add_display_components() to register the child
nodes - which includes
Hi Laurent,
On 3/17/21 4:32 AM, Laurent Pinchart wrote:
Hi Quanyang,
Thank you for the patch.
On Wed, Mar 10, 2021 at 12:59:45PM +0800, quanyang.w...@windriver.com wrote:
From: Quanyang Wang
The Runtime PM subsystem will force the device "fd4a.zynqmp-display"
to enter suspend state whil
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/display/intel_sprite.c
between commit:
92f1d09ca4ed ("drm: Switch to %p4cc format modifier")
from the drm tree and commit:
46d12f911821 ("drm/i915: migrate skl planes code new file (v5)")
fro
Hi,
This is the v6 series to add some DRM bridge drivers support
for i.MX8qm/qxp SoCs.
The bridges may chain one by one to form display pipes to support
LVDS displays. The relevant display controller is DPU embedded in
i.MX8qm/qxp SoCs.
The DPU KMS driver can be found at:
https://www.spinics.ne
This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
The RGB pixels with padding low per component are transmitted on a 30-bit
input bus(10-bit per component) from a display controller or a 36-bit
output bu
This patch adds documentations for RGB666_1X30_CPADLO, RGB888_1X30_CPADLO,
RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp
pixel combiner. The RGB pixels with padding low per component are
transmitted on a 30-bit input bus(10-bit per component) from a display
controller o
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* Add Rob's R-b tag.
v1->v2:
* Use graph schema. (Laurent)
* Use enum instead of oneOf + const for the reg prop
This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner.
The pixel combiner takes two output streams from a single display
controller and manipulates the two streams to support a number
of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured
as either one screen, two scre
This patch adds bindings for i.MX8qm/qxp display pixel link.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* Add Rob's R-b tag.
v1->v2:
* Use graph schema. (Laurent)
* Require all four pixel link output ports. (Lau
This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
The pixel link forms a standard asynchronous linkage between
pixel sources(display controller or camera module) and pixel
consumers(imaging or displays). It consists of two distinct
functions, a pixel transfer function and a c
This patch adds bindings for i.MX8qm/qxp Control and Status Registers module.
Signed-off-by: Liu Ying
---
v5->v6:
* Drop 'select' schema. (Rob)
v4->v5:
* Newly introduced in v5. (Rob)
.../devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml | 192 +
1 file changed, 192 insertions
This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v5->v6:
* Add Rob's R-b tag.
v4->v5:
* No change.
v3->v4:
* Add 'fsl,sc-resource' property. (Rob)
v2->v3:
* Drop 'fsl,syscon' property. (Rob)
* Mention the CSR module control
This patch adds a drm bridge driver for i.MX8qxp pixel link to display
pixel interface(PXL2DPI). The PXL2DPI interfaces the pixel link 36-bit
data output and the DSI controller’s MIPI-DPI 24-bit data input, and
inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap
the pixel color c
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