Add error return code in error hanlding code of amdgpu_acpi_init().
Reported-by: TOTE Robot
Signed-off-by: Jia-Ju Bai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm
The devfreq core code is able to register the devfreq device as a
cooling device if the 'is_cooling_device' flag is set in the profile.
Use this flag and remove the cooling device registering code.
Tested on dragonboard 845c
Signed-off-by: Daniel Lezcano
---
drivers/gpu/drm/msm/msm_gpu.c | 12
The devfreq core code is able to register the devfreq device as a
cooling device if the 'is_cooling_device' flag is set in the profile.
Use this flag and remove the cooling device registering code.
Tested on rock960.
Signed-off-by: Daniel Lezcano
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c
The devfreq core code is able to register the devfreq device as a
cooling device if the 'is_cooling_device' flag is set in the profile.
Use this flag and remove the cooling device registering code.
Signed-off-by: Daniel Lezcano
---
drivers/gpu/drm/lima/lima_devfreq.c | 14 +-
driver
From: Alex Deucher
[ Upstream commit 25951362db7b3791488ec45bf56c0043f107b94b ]
It works fine and was only disabled because primary GPUs
don't enter runpm if there is a console bound to the fbdev due
to the kmap. This will at least allow runpm on secondary cards.
Reviewed-by: Evan Quan
Review
From: Alex Deucher
[ Upstream commit 25951362db7b3791488ec45bf56c0043f107b94b ]
It works fine and was only disabled because primary GPUs
don't enter runpm if there is a console bound to the fbdev due
to the kmap. This will at least allow runpm on secondary cards.
Reviewed-by: Evan Quan
Review
https://bugzilla.kernel.org/show_bug.cgi?id=211277
--- Comment #14 from kolAflash (kolafl...@kolahilft.de) ---
(In reply to Jerome C from comment #13)
I don't get how you got to your results.
There's no straight path from 5.10.4 to 5.11-rc5, as they are on different
branches (5.10.y and master).
The struct is giant, and triggers an order-7 allocation (512K). There is
no reason for this to be kmalloc-type memory, so switch to vmalloc. This
should help loading nouveau on low-memory and/or long-running systems.
Reported-by: Nathan E. Egge
Signed-off-by: Ilia Mirkin
Cc: sta...@vger.kernel.o
https://bugzilla.kernel.org/show_bug.cgi?id=212107
Bug ID: 212107
Summary: Temperature increase by 15°C on radeon gpu
Product: Drivers
Version: 2.5
Kernel Version: 5.11
Hardware: x86-64
OS: Linux
Tree: Mainlin
https://bugzilla.kernel.org/show_bug.cgi?id=212107
--- Comment #1 from Martin (martin...@gmx.com) ---
Created attachment 295703
--> https://bugzilla.kernel.org/attachment.cgi?id=295703&action=edit
kernel config
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The devfreq core code is able to register the devfreq device as a
cooling device if the 'is_cooling_device' flag is set in the profile.
Use this flag and remove the cooling device registering code.
Tested on dragonboard 845c
Signed-off-by: Daniel Lezcano
---
drivers/gpu/drm/msm/msm_gpu.c | 12
The devfreq core code is able to register the devfreq device as a
cooling device if the 'is_cooling_device' flag is set in the profile.
Use this flag and remove the cooling device registering code.
Tested on rock960.
Signed-off-by: Daniel Lezcano
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c
The devfreq core code is able to register the devfreq device as a
cooling device if the 'is_cooling_device' flag is set in the profile.
Use this flag and remove the cooling device registering code.
Signed-off-by: Daniel Lezcano
---
drivers/gpu/drm/lima/lima_devfreq.c | 14 +-
driver
https://bugzilla.kernel.org/show_bug.cgi?id=212109
Bug ID: 212109
Summary: Analogix ANX6345 bridge fails to initialize after
suspend
Product: Drivers
Version: 2.5
Kernel Version: 5.11.4
Hardware: ARM
OS:
https://bugzilla.kernel.org/show_bug.cgi?id=212109
Jaron Kent-Dobias (ja...@kent-dobias.com) changed:
What|Removed |Added
CC||ja...@kent-dob
The NT39016 panel is a fun beast, even though the documentation states
that the CS line is active-low, it will work just fine if the CS line is
configured as active-high, but it won't work if the CS line is forced
low or forced high.
Since it did actually work with the spi-cs-high property, this i
The NT39016 panel is a fun beast, even though the documentation states
that the CS line is active-low, it will work just fine if the CS line is
configured as active-high, but it won't work if the CS line is forced
low or forced high.
Since it did actually work with the spi-cs-high property, this i
https://bugzilla.kernel.org/show_bug.cgi?id=212109
--- Comment #1 from Jaron Kent-Dobias (ja...@kent-dobias.com) ---
Created attachment 295707
--> https://bugzilla.kernel.org/attachment.cgi?id=295707&action=edit
dmesg log ending immediately after bug in question
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You may reply to this email
https://bugzilla.kernel.org/show_bug.cgi?id=212109
--- Comment #2 from Jaron Kent-Dobias (ja...@kent-dobias.com) ---
Additional information: the 5.10 and 5.11 series appear to attempt different
suspends: the 5.10 enters "s2idle" suspend, while the 5.11 enters "deep"
suspend.
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Rework of my previous patchset which added support for GEM buffers
backed by non-coherent memory to the ingenic-drm driver.
Having GEM buffers backed by non-coherent memory is interesting in
the particular case where it is faster to render to a non-coherent
buffer then sync the data cache, than to
This function can be used by drivers that need to create a GEM object
with non-coherent backing memory.
Creating non-coherent CMA objects is useful on architectures where
writing to a buffer with the non-coherent cache attribute set then
invalidating the cache is faster than writing to the same bu
This function can be used by drivers to create dumb buffers with
non-coherent backing memory.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/drm_gem_cma_helper.c | 37 +---
include/drm/drm_gem_cma_helper.h | 5
2 files changed, 38 insertions(+), 4 deletions(-)
This function can be used by drivers that need to mmap dumb buffers
created with non-coherent backing memory.
v2: Use dma_to_phys() since cma_obj->paddr isn't a phys_addr_t but a
dma_addr_t.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/drm_gem_cma_helper.c | 67 +---
This function can be used by drivers that use damage clips and have
CMA GEM objects backed by non-coherent memory. Calling this function
in a plane's .atomic_update ensures that all the data in the backing
memory have been written to RAM.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/drm_gem_
With the module parameter ingenic-drm.cached_gem_buffers, it is possible
to specify that we want GEM buffers backed by non-coherent memory.
This dramatically speeds up software rendering on Ingenic SoCs, even for
tasks where write-combine memory should in theory be faster (e.g. simple
blits).
Lea
https://bugzilla.kernel.org/show_bug.cgi?id=212107
Dieter Nützel (die...@nuetzel-hh.de) changed:
What|Removed |Added
CC||die...@nuetzel-hh.d
From: Dave Airlie
The index variable should only be increased in one place.
Noticed this while trying to track down another oops.
Fixes: f295c8cfec83 ("drm/nouveau: fix dma syncing warning with debugging on.")
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 4 ++--
1 fil
Hello Jan,
I very much appreciate your advice.
Tried several places...
...where to put it?
Dieter
Am 06.03.2021 17:56, schrieb Jan Vesely:
Not Marek, but hope this answer will help.
libclc uses clang CLC preprocessor on .ll files, llvm/clang-13 started
including clc declarations by default (cl
On Fri, 2021-03-05 at 16:03 +0100, Robert Foss wrote:
> Hey Liu,
>
> This patch seems to be included in both this series and the "Add some
> DRM bridge drivers support for i.MX8qm/qxp SoCs" series. Instead of
> having the two series have a conflict I would suggest either merging
> them (if that ma
On Fri, 2021-03-05 at 16:22 +0100, Robert Foss wrote:
> Hey Liu,
>
> Looking at this series[1], all but patch#2 has been reviewed, and #2
> looks good to me. So I think this series is ready to have v4 re-spun
> and and all of the r-bs from v3 added to the relevant patches.
Will respin this series
Fix the following coccicheck warnings:
./drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c:561:34-39: WARNING:
conversion to bool not needed here.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +-
1 file changed, 1 insertion(+),
https://bugzilla.kernel.org/show_bug.cgi?id=210849
--- Comment #18 from JerryD (jvdeli...@charter.net) ---
(In reply to JerryD from comment #17)
> Possible fixed in this commit:
>
> https://github.com/torvalds/linux/commit/
> a81bfdf8bf5396824d7d139560180854cb599b06
No noy fixed. I ahve tried u
Fix the following coccicheck warnings:
./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1600:40-45: WARNING: conversion
to bool not needed here.
./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1598:40-45: WARNING: conversion
to bool not needed here.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
Hi,
This series adds i.MX8qxp LVDS PHY mode support for the Mixel PHY in the
Freescale i.MX8qxp SoC.
The Mixel PHY is MIPI DPHY + LVDS PHY combo, which can works in either
MIPI DPHY mode or LVDS PHY mode. The PHY mode is controlled by i.MX8qxp
SCU firmware. The PHY driver would call a SCU funct
The Northwest Logic MIPI DSI host controller embedded in i.MX8qxp
works with a Mixel MIPI DPHY + LVDS PHY combo to support either
a MIPI DSI display or a LVDS display. So, this patch calls
phy_set_mode() from nwl_dsi_enable() to set PHY mode to MIPI DPHY
explicitly.
Cc: Guido Günther
Cc: Robert
This patch allows LVDS PHYs to be configured through
the generic functions and through a custom structure
added to the generic union.
The parameters added here are based on common LVDS PHY
implementation practices. The set of parameters
should cover all potential users.
Cc: Kishon Vijay Abraham
This patch converts the mixel,mipi-dsi-phy binding to
DT schema format using json-schema.
Comparing to the plain text version, the new binding adds
the 'assigned-clocks', 'assigned-clock-parents' and
'assigned-clock-rates' properites, otherwise 'make dtbs_check'
would complain that there are mis-m
Add support for Mixel MIPI DPHY + LVDS PHY combo IP
as found on Freescale i.MX8qxp SoC.
Cc: Guido Günther
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Cc: Rob Herring
Cc: NXP Linux Team
Reviewed-by: Rob Herring
Reviewed-by: Guido Günther
Signed-off-by: Liu Ying
---
v3->v4:
* Add Rob's and Gui
i.MX8qxp SoC embeds a Mixel MIPI DPHY + LVDS PHY combo which supports
either a MIPI DSI display or a LVDS display. The PHY mode is controlled
by SCU firmware and the driver would call a SCU firmware function to
configure the PHY mode. The single LVDS PHY has 4 data lanes to support
a LVDS display
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