Problem: random stucks on reboot stage about 1/20 stuck/reboots
// debug kernel log
[4.496660] reboot: kernel restart prepare CMD:(null)
[4.498114] meson_ee_pwrc c883c000.system-controller:power-controller:
shutdown begin
[4.503949] meson_ee_pwrc c883c000.system-controller:power-contro
https://bugzilla.kernel.org/show_bug.cgi?id=212019
Bug ID: 212019
Summary: [drm:drm_atomic_helper_wait_for_flip_done
[drm_kms_helper]] *ERROR* [CRTC:67:crtc-0] flip_done
timed out
Product: Drivers
Version: 2.5
On Saturday, 27 February 2021 2:59:09 AM AEDT Christoph Hellwig wrote:
> > - struct page *page = migration_entry_to_page(entry);
> > + struct page *page = pfn_to_page(swp_offset(entry));
>
> I wonder if keeping a single special_entry_to_page() helper would still
> me a useful.
https://bugzilla.kernel.org/show_bug.cgi?id=212019
--- Comment #1 from Fruhwirth Clemens (clem...@endorphin.org) ---
Created attachment 295571
--> https://bugzilla.kernel.org/attachment.cgi?id=295571&action=edit
kernel log
--
You may reply to this email to add a comment.
You are receiving thi
On Tuesday, 2 March 2021 11:05:59 AM AEDT Jason Gunthorpe wrote:
> On Fri, Feb 26, 2021 at 06:18:29PM +1100, Alistair Popple wrote:
>
> > +/**
> > + * make_device_exclusive_range() - Mark a range for exclusive use by a
device
> > + * @mm: mm_struct of assoicated target process
> > + * @start: sta
https://bugzilla.kernel.org/show_bug.cgi?id=211875
--- Comment #3 from Erhard F. (erhar...@mailbox.org) ---
Created attachment 295573
--> https://bugzilla.kernel.org/attachment.cgi?id=295573&action=edit
kernel .config (kernel 5.12-rc1, A10-9700E)
Same for kernel v5.12-rc1. Backtrace looks sligh
On Tuesday, 2 March 2021 10:14:56 AM AEDT Ralph Campbell wrote:
> > From: Alistair Popple
> > Sent: Thursday, February 25, 2021 11:19 PM
> > To: linux...@kvack.org; nouv...@lists.freedesktop.org;
> > bske...@redhat.com; a...@linux-foundation.org
> > Cc: linux-...@vger.kernel.org; linux-ker...@vger
Hi,
if there are no further comments on this patch, I intend to merge it via
drm-misc.
Best regards
Thomas
Am 01.03.21 um 10:31 schrieb Thomas Zimmermann:
USB devices cannot perform DMA and hence have no dma_mask set in their
device structure. Therefore importing dmabuf into a USB-based driv
On Mon, Mar 01, 2021 at 10:31:27AM +0100, Thomas Zimmermann wrote:
> USB devices cannot perform DMA and hence have no dma_mask set in their
> device structure. Therefore importing dmabuf into a USB-based driver
> fails, which breaks joining and mirroring of display in X11.
>
> For USB devices, pic
Hi
Am 02.03.21 um 04:29 schrieb Tong Zhang:
Hi Tomas,
I think the issue could be possibly caused by the following,
Please correct me if I'm wrong.
drm_fb_helper_single_fb_probe() can fail with
"Cannot find any crtc or sizes"
which will cause fb_helper->funcs->fb_probe not being called,
thus fb
The hdcp_i2c_offsets[] array did not have an entry for
HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE so it led to an off by one
read overflow. I added an entry and copied the 0x0 value for the offset
from similar code in drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c.
I also declared several of
:
Hi Oak,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip linus/master v5.12-rc1 next-20210302]
[cannot apply to tegra-drm/drm/tegra/for-next drm-exynos/exynos-drm-next
drm/drm-next]
[If your pat
Hey,
A single regression fix here that I noticed while testing a bunch of
boards for something else, not sure where this got lost! Prevents 3D
driver from initialising on some GPUs.
Ben.
The following changes since commit f6df392dddbb9e637b785e7e3d9337a74923dc10:
drm/nouveau/top/ga100: initi
From: AngeloGioacchino Del Regno
[ Upstream commit 8f03c30cb814213e36032084a01f49a9e604a3e3 ]
The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets
programmed to some different values on a per-model basis.
At least, this is what we intend to do here;
Unfortunately, though, this register i
From: AngeloGioacchino Del Regno
[ Upstream commit 8f03c30cb814213e36032084a01f49a9e604a3e3 ]
The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets
programmed to some different values on a per-model basis.
At least, this is what we intend to do here;
Unfortunately, though, this register i
From: AngeloGioacchino Del Regno
[ Upstream commit 8f03c30cb814213e36032084a01f49a9e604a3e3 ]
The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets
programmed to some different values on a per-model basis.
At least, this is what we intend to do here;
Unfortunately, though, this register i
From: AngeloGioacchino Del Regno
[ Upstream commit 8f03c30cb814213e36032084a01f49a9e604a3e3 ]
The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets
programmed to some different values on a per-model basis.
At least, this is what we intend to do here;
Unfortunately, though, this register i
From: AngeloGioacchino Del Regno
[ Upstream commit 8f03c30cb814213e36032084a01f49a9e604a3e3 ]
The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets
programmed to some different values on a per-model basis.
At least, this is what we intend to do here;
Unfortunately, though, this register i
As explained by a long comment block, on VLV intel_setup_outputs()
sometimes thinks there might be an eDP panel connected while there is none.
In this case intel_setup_outputs() will call intel_dp_init() to check.
In this scenario vlv_find_free_pps() ends up selecting pipe A for the pps,
even thou
Hi All,
Here is a resend of my patch-set to deal with an
"transcoder A assertion failure (expected off, current on)"
error + WARN (and backtrace) seen on some Bay Trail devices with a DSI panel.
I've rebased it on the latest drm-intel-next, so this time around the CI
should be able to actually ap
Factor the code to check if a pipe is currently enabled out of
assert_pipe() and put it in a new intel_pipe_is_enabled() helper,
so that it can be re-used without copy-pasting it.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_display.c | 20 ++--
drivers/gpu
On Tuesday, 2 March 2021 7:52:53 PM AEDT Alistair Popple wrote:
> On Saturday, 27 February 2021 2:59:09 AM AEDT Christoph Hellwig wrote:
> > > - struct page *page = migration_entry_to_page(entry);
> > > + struct page *page = pfn_to_page(swp_offset(entry));
> >
> > I wonder if keepi
On Tue, Mar 02, 2021 at 07:57:58PM +1100, Alistair Popple wrote:
> The intent was a driver could use HMM or some other mechanism to keep PTEs
> synchronised if required. However I just looked at patch 8 in the series
> again
> and it appears I got this wrong when converting from the old migrati
This series adds memory bandwidth management to the NVIDIA Tegra DRM driver,
which is done using interconnect framework. It fixes display corruption that
happens due to insufficient memory bandwidth.
Tegra memory drivers already got the interconnect API support and DRM patches
were a part of the s
Display controller (DC) performs isochronous memory transfers, and thus,
has a requirement for a minimum memory bandwidth that shall be fulfilled,
otherwise framebuffer data can't be fetched fast enough and this results
in a DC's data-FIFO underflow that follows by a visual corruption.
The Memory
It's useful to know the total number of underflow events and currently
the debug stats are getting reset each time CRTC is being disabled. Let's
account the overall number of events that doesn't get a reset.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
dr
On Tue, 02 Mar 2021, Hans de Goede wrote:
> Factor the code to check if a pipe is currently enabled out of
> assert_pipe() and put it in a new intel_pipe_is_enabled() helper,
> so that it can be re-used without copy-pasting it.
>
> Signed-off-by: Hans de Goede
Does what it says on the box.
Revi
Without we get an "Specify missing connector_type" warning.
Fixes: ddb8e853dc85 ("drm/panel: panel-simple: validate panel description")
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/panel/panel-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-sim
Hi Laurent,
>> > Is this a property of the hardware, that is, are there multiple versions
>> > of this IP core covered by the same compatible string that support HDCP
>> > 1.4 only, DHCP 2.2 only or both ? Or is it a way to select what a given
>> > system will offer ?[]
>>
>> MHDP hardware support
On Tue, 02 Mar 2021, Hans de Goede wrote:
> As explained by a long comment block, on VLV intel_setup_outputs()
> sometimes thinks there might be an eDP panel connected while there is none.
> In this case intel_setup_outputs() will call intel_dp_init() to check.
>
> In this scenario vlv_find_free_p
Hi Dave,
Thanks for your review
On Thu, Feb 25, 2021 at 04:38:37PM +, Dave Stevenson wrote:
> On Thu, 25 Feb 2021 at 15:59, Maxime Ripard wrote:
> >
> > In order to reach the frequencies needed to output at 594MHz, the
> > firmware needs to be configured with the appropriate parameters in th
RGB output doesn't allow to change parent clock rate of the display and
PCLK rate is set to 0Hz in this case. The tegra_dc_commit_state() shall
not set the display clock to 0Hz since this change propagates to the
parent clock. The DISP clock is defined as a NODIV clock by the tegra-clk
driver and a
20.01.2021 19:01, Dmitry Osipenko пишет:
> 01.01.2021 19:54, Yangtao Li пишет:
>> Hi,
>>
>> This patchset add devm_pm_opp_set_clkname, devm_pm_opp_put_clkname,
>> devm_pm_opp_set_regulators, devm_pm_opp_put_regulators,
>> devm_pm_opp_set_supported_hw, devm_pm_opp_of_add_table and
>> devm_pm_opp_reg
Hey Liu,
Thanks for submitting this patch.
I only have one comment below. With that addressed, feel free to add my r-b.
Reviewed-by: Robert Foss
On Thu, 18 Feb 2021 at 04:59, Liu Ying wrote:
>
> This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
> The pixel link forms a s
Hi Dave,
On Thu, Feb 25, 2021 at 04:46:48PM +, Dave Stevenson wrote:
> On Thu, 25 Feb 2021 at 15:59, Maxime Ripard wrote:
> >
> > Signed-off-by: Maxime Ripard
>
> Other than no commit text body (which is hardly needed in this case)
>
> Reviewed-by: Dave Stevenson
Yeah the last two patche
From: Colin Ian King
Currently if stream->signal is neither SIGNAL_TYPE_DISPLAY_PORT_MST or
SIGNAL_TYPE_DISPLAY_PORT then variable ret is uninitialized and this is
checked for > 0 at the end of the function. Ret should be initialized,
I believe setting it to zero is a correct default.
Addresses
Hey Liu,
Thanks for submitting this patch.
On Thu, 18 Feb 2021 at 04:59, Liu Ying wrote:
>
> This patch adds a helper to support LDB drm bridge drivers for
> i.MX SoCs. Helper functions exported from this driver should
> implement common logics for all LDB modules embedded in i.MX SoCs.
>
> Sig
Hi Liu Ying,
One comment below.
On Tue, Mar 02, 2021 at 02:33:15PM +0800, Liu Ying wrote:
> This patch introduces i.MX8qm/qxp Display Processing Unit(DPU) DRM support.
>
> DPU is comprised of two main components that include a blit engine for
> 2D graphics accelerations(with composition support)
On Tue, Mar 02, 2021 at 01:00:40PM +0100, Hans de Goede wrote:
> As explained by a long comment block, on VLV intel_setup_outputs()
> sometimes thinks there might be an eDP panel connected while there is none.
> In this case intel_setup_outputs() will call intel_dp_init() to check.
>
> In this sce
On 2021-03-02 9:05 a.m., Colin King wrote:
From: Colin Ian King
Currently if stream->signal is neither SIGNAL_TYPE_DISPLAY_PORT_MST or
SIGNAL_TYPE_DISPLAY_PORT then variable ret is uninitialized and this is
checked for > 0 at the end of the function. Ret should be initialized,
I believe settin
On Tue, 2 Mar 2021 at 13:02, Maxime Ripard wrote:
>
> Hi Dave,
>
> Thanks for your review
>
> On Thu, Feb 25, 2021 at 04:38:37PM +, Dave Stevenson wrote:
> > On Thu, 25 Feb 2021 at 15:59, Maxime Ripard wrote:
> > >
> > > In order to reach the frequencies needed to output at 594MHz, the
> > >
https://bugzilla.kernel.org/show_bug.cgi?id=211981
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
Implement the new connector_attach/detach bridge ops. This makes it
possible to associate a CEC adapter with a drm connector, which helps
userspace determine which cec device node belongs to which drm connector.
Signed-off-by: Hans Verkuil
---
drivers/gpu/drm/omapdrm/dss/hdmi4.c | 27 +++
This series improves the drm_bridge support for CEC by introducing two
new bridge ops in the first patch, and using those in the second patch.
This makes it possible to call cec_s_conn_info() and set
CEC_CAP_CONNECTOR_INFO for the CEC adapter, so userspace can associate
the CEC adapter with the co
Add bridge connector_attach/detach ops. These ops are called when a
bridge is attached or detached to a drm_connector. These ops can be
used to register and unregister an HDMI CEC adapter for a bridge that
supports CEC.
Signed-off-by: Hans Verkuil
---
drivers/gpu/drm/drm_bridge_connector.c | 9
The cec clock is required as well in order to support HDMI CEC,
document this.
Signed-off-by: Hans Verkuil
---
Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/ti/ti,oma
Switch to using cec_s_phys_addr_from_edid() instead of a two-step process
of calling cec_get_edid_phys_addr() followed by cec_s_phys_addr().
Signed-off-by: Hans Verkuil
Reviewed-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/hdmi4.c | 13 ++---
drivers/gpu/drm/omapdrm/dss/hdmi4_
Add cec clock to the dra7 and omap5 device trees.
Signed-off-by: Hans Verkuil
Acked-by: Tony Lindgren
---
arch/arm/boot/dts/dra7.dtsi | 5 +++--
arch/arm/boot/dts/omap5.dtsi | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dt
Add HDMI CEC support for OMAP5.
Signed-off-by: Hans Verkuil
---
drivers/gpu/drm/omapdrm/Kconfig | 8 +
drivers/gpu/drm/omapdrm/Makefile | 1 +
drivers/gpu/drm/omapdrm/dss/hdmi.h | 1 +
drivers/gpu/drm/omapdrm/dss/hdmi5.c | 63 +--
drivers/gpu/drm/omapdrm/ds
On Fri, Feb 26, 2021 at 10:40:24PM +0530, Jagan Teki wrote:
> On Fri, Feb 26, 2021 at 10:27 PM Maxime Ripard wrote:
> >
> > Hi,
> >
> > On Mon, Feb 15, 2021 at 01:11:01AM +0530, Jagan Teki wrote:
> > > Use drm_panel_bridge to replace manual panel handling code.
> > >
> > > This simplifies the driv
https://bugzilla.kernel.org/show_bug.cgi?id=211875
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
On Tue, Mar 2, 2021 at 10:05 PM Maxime Ripard wrote:
>
> On Fri, Feb 26, 2021 at 10:40:24PM +0530, Jagan Teki wrote:
> > On Fri, Feb 26, 2021 at 10:27 PM Maxime Ripard wrote:
> > >
> > > Hi,
> > >
> > > On Mon, Feb 15, 2021 at 01:11:01AM +0530, Jagan Teki wrote:
> > > > Use drm_panel_bridge to re
Applied. Thanks!
Alex
On Tue, Mar 2, 2021 at 10:03 AM Harry Wentland wrote:
>
> On 2021-03-02 9:05 a.m., Colin King wrote:
> > From: Colin Ian King
> >
> > Currently if stream->signal is neither SIGNAL_TYPE_DISPLAY_PORT_MST or
> > SIGNAL_TYPE_DISPLAY_PORT then variable ret is uninitialized and
On Thu, Feb 25, 2021 at 10:01 AM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> clang points out that the new logic uses an always-uninitialized
> array index:
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9810:38: warning:
> variable 'i' is uninitialized when used here [-Wun
STM ltdc driver uses an empty implementation for its encoder.
Replace the code with the generic simple encoder.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/stm/ltdc.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/
On Mon, Mar 1, 2021 at 12:11 PM Mark Yacoub wrote:
>
> When creating a new framebuffer, verify that the bo size associated with
> it can handle the fb size.
> drm_gem_fb_init_with_funcs implements this check by calculating the
> minimum expected size of each plane. amdgpu now uses this function to
Applied. Thanks!
Alex
On Mon, Mar 1, 2021 at 1:50 AM Jiapeng Chong
wrote:
>
> Fix the following coccicheck warnings:
>
> ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c:298:33-38:
> WARNING: conversion to bool not needed here.
>
> Reported-by: Abaci Robot
> Signed-off-by: Jiapeng Chong
https://bugzilla.kernel.org/show_bug.cgi?id=211875
--- Comment #5 from Erhard F. (erhar...@mailbox.org) ---
I don't know. This is a new machine and have seen this since 5.10.x which was
the first kernel I tried on it.
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You may reply to this email to add a comment.
You are receiving this mail
Just a silly mistake
Signed-off-by: Lionel Landwerlin
Suggested-by: Ben Widawsky
---
include/uapi/drm/drm_mode.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index b49fbf2bdc408..93b494f704b91 100644
--- a/include/
Good catch!
Reviewed-by: Simon Ser
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Thanks Simon. Do you have the rights to push this patch?
-Lionel
On 02/03/2021 20:46, Simon Ser wrote:
Good catch!
Reviewed-by: Simon Ser
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On Tuesday, March 2nd, 2021 at 7:47 PM, Lionel Landwerlin
wrote:
> Thanks Simon. Do you have the rights to push this patch?
Ah, since you're asking about this, it probably means you don't have the
rights. I'll push the patch now to drm-misc-next.
___
[AMD Official Use Only - Internal Distribution Only]
Thanks
Reviewed-by: Bhawanpreet Lakha
From: Dan Carpenter
Sent: March 2, 2021 6:15 AM
To: Wentland, Harry ; Lakha, Bhawanpreet
Cc: Li, Sun peng (Leo) ; Deucher, Alexander
; Koenig, Christian ;
David Airlie
In case of a modeset where a mode gets split across mutiple CRTCs
in the driver specific implementation (bigjoiner in i915) we wrongly count
the affected CRTCs based on the drm_crtc_mask and indicate the stolen CRTC as
an affected CRTC in atomic_check_only().
This triggers a warning since affected
Hi Kieran,
On Mon, Mar 01, 2021 at 11:52:26AM +, Kieran Bingham wrote:
> On 01/03/2021 10:30, Geert Uytterhoeven wrote:
> > On Thu, Jan 14, 2021 at 11:00 AM Geert Uytterhoeven wrote:
> >> On Wed, Jan 13, 2021 at 6:02 PM Kieran Bingham wrote:
> >>> The encoder allocation was converted to a DRM
On 26 Feb 2021, at 2:18, Alistair Popple wrote:
> Migration is currently implemented as a mode of operation for
> try_to_unmap_one() generally specified by passing the TTU_MIGRATION flag
> or in the case of splitting a huge anonymous page TTU_SPLIT_FREEZE.
>
> However it does not have much in comm
rove:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip linus/master v5.12-rc1 next-20210302]
[cannot apply to tegra-drm/drm/tegra/for-next drm-exynos/exynos-drm-next
drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop
ioremap buffer according to TTM mem caching setting
If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.
This wasn't necessary before as device memory was never mapped
as cached from CPU side. It becomes necessary for aldebaran as
device
On Wed, 3 Mar 2021 at 08:45, Zeng, Oak wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
>
> Hi Daniel, Thomas, Dan,
>
>
>
> Does below message mean the calling ioremap_cache failed intel’s driver
> build? I can see both ioremap_cache and ioremap_wc are defined in
> arch/x86/mm/i
Quoting Maxime Ripard (2021-02-25 07:59:02)
> Some devices might need to access the current available range of a clock
> to discover their capabilities. Let's add those accessors.
This needs more than two sentences to describe what's required.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/c
From: Colin Ian King
Currently the ioctl command RADEON_INFO_SI_BACKEND_ENABLED_MASK can
copy back uninitialised data in value_tmp that pointer *value points
to. This can occur when rdev->family is less than CHIP_BONAIRE and
less than CHIP_TAHITI. Fix this by adding in a missing -EINVAL
so that
ioremap buffer according to TTM mem caching setting
If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.
This wasn't necessary before as device memory was never mapped
as cached from CPU side. It becomes necessary for aldebaran as
device
updated to use drmm_vram_helper_init().
Signed-off-by: Tian Tao
---
drivers/gpu/drm/vboxvideo/vbox_ttm.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/vboxvideo/vbox_ttm.c
b/drivers/gpu/drm/vboxvideo/vbox_ttm.c
index 0066a3c..fd8a53a 100644
--- a/dri
Now that we can print FourCC codes directly using printk, make use of the
feature in nouveau.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
b/
Hi Oak,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip linus/master v5.12-rc1 next-20210303]
[cannot apply to tegra-drm/drm/tegra/for-next drm-exynos/exynos-drm-next
drm/drm-next]
[If your patch is
On Tue, 2021-03-02 at 16:36 +0200, Laurentiu Palcu wrote:
> Hi Liu Ying,
>
> One comment below.
>
> On Tue, Mar 02, 2021 at 02:33:15PM +0800, Liu Ying wrote:
> > This patch introduces i.MX8qm/qxp Display Processing Unit(DPU) DRM support.
> >
> > DPU is comprised of two main components that inclu
On 27/02/2021 23:45, Sebastian Reichel wrote:
From: Sebastian Reichel
Disable TE for Droid 4 panel, since implementation is currently
broken. Also disable it for N950 panel, which is untested.
Reported-by: Tony Lindgren
Reported-by: Tomi Valkeinen
Fixes: 4c1b935fea54 ("drm/omap: dsi: move TE
Hi Robert,
On Tue, 2021-03-02 at 14:53 +0100, Robert Foss wrote:
> Hey Liu,
>
> Thanks for submitting this patch.
>
> I only have one comment below. With that addressed, feel free to add my r-b.
>
> Reviewed-by: Robert Foss
Thanks for reviewing this patch.
>
> On Thu, 18 Feb 2021 at 04:59,
Hi Robert,
On Tue, 2021-03-02 at 15:22 +0100, Robert Foss wrote:
> Hey Liu,
>
> Thanks for submitting this patch.
Thanks for reviewing this patch.
>
> On Thu, 18 Feb 2021 at 04:59, Liu Ying wrote:
> > This patch adds a helper to support LDB drm bridge drivers for
> > i.MX SoCs. Helper functi
Am 03.03.21 um 02:17 schrieb Anthony DeRossi:
Freed pages are not subtracted from the allocated_pages counter in
ttm_pool_type_fini(), causing a leak in the count on device removal.
The next shrinker invocation loops forever trying to free pages that are
no longer in the pool:
rcu: INFO: rcu_
On 02-03-21, 16:40, Dmitry Osipenko wrote:
> 20.01.2021 19:01, Dmitry Osipenko пишет:
> > 01.01.2021 19:54, Yangtao Li пишет:
> >> Hi,
> >>
> >> This patchset add devm_pm_opp_set_clkname, devm_pm_opp_put_clkname,
> >> devm_pm_opp_set_regulators, devm_pm_opp_put_regulators,
> >> devm_pm_opp_set_supp
Freed pages are not subtracted from the allocated_pages counter in
ttm_pool_type_fini(), causing a leak in the count on device removal.
The next shrinker invocation loops forever trying to free pages that are
no longer in the pool:
rcu: INFO: rcu_sched self-detected stall on CPU
rcu: 3-:
On 02/03/2021 18:24, Hans Verkuil wrote:
The cec clock is required as well in order to support HDMI CEC,
document this.
Signed-off-by: Hans Verkuil
---
Documentation/devicetree/bindings/display/ti/ti,omap5-dss.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Docume
Am 03.03.21 um 01:27 schrieb Colin King:
From: Colin Ian King
Currently the ioctl command RADEON_INFO_SI_BACKEND_ENABLED_MASK can
copy back uninitialised data in value_tmp that pointer *value points
to. This can occur when rdev->family is less than CHIP_BONAIRE and
less than CHIP_TAHITI. Fix t
On 02/03/2021 18:24, Hans Verkuil wrote:
Add cec clock to the dra7 and omap5 device trees.
Signed-off-by: Hans Verkuil
Acked-by: Tony Lindgren
---
arch/arm/boot/dts/dra7.dtsi | 5 +++--
arch/arm/boot/dts/omap5.dtsi | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/
Am 02.03.21 um 18:57 schrieb Jagan Teki:
STM ltdc driver uses an empty implementation for its encoder.
Replace the code with the generic simple encoder.
Signed-off-by: Jagan Teki
Acked-by: Thomas Zimmermann
---
drivers/gpu/drm/stm/ltdc.c | 12 ++--
1 file changed, 2 insertions
On 02/03/2021 18:24, Hans Verkuil wrote:
Add HDMI CEC support for OMAP5.
Signed-off-by: Hans Verkuil
---
drivers/gpu/drm/omapdrm/Kconfig | 8 +
drivers/gpu/drm/omapdrm/Makefile | 1 +
drivers/gpu/drm/omapdrm/dss/hdmi.h | 1 +
drivers/gpu/drm/omapdrm/dss/hdmi5.c
On 03/03/2021 08:47, Tomi Valkeinen wrote:
> On 02/03/2021 18:24, Hans Verkuil wrote:
>> Add HDMI CEC support for OMAP5.
>>
>> Signed-off-by: Hans Verkuil
>> ---
>> drivers/gpu/drm/omapdrm/Kconfig | 8 +
>> drivers/gpu/drm/omapdrm/Makefile | 1 +
>> drivers/gpu/drm/omapdrm
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