On Tue, Feb 16, 2021 at 09:53:36PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay
>
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaroun
On Tue, Feb 09, 2021 at 02:46:22PM +0100, Thomas Zimmermann wrote:
> (was: drm/ast: Move cursor vmap calls out of commit tail)
>
> Ast has vmap calls in its cursor's atomic_update function. This is not
> supported as vmap might aquire the dma reservation lock. While at it,
> cleanup the whole curs
On Tue, Feb 16, 2021 at 02:46:21PM +0100, Thomas Zimmermann wrote:
>
>
> Am 16.02.21 um 14:27 schrieb Thomas Zimmermann:
> > Hi
> >
> > this is a shadow-buffered plane. Did you consider using the new helpers
> > for shadow-buffered planes? They will map the user BO for you and
> > provide the ma
Hi
Am 17.02.21 um 11:02 schrieb Gerd Hoffmann:
On Tue, Feb 16, 2021 at 02:46:21PM +0100, Thomas Zimmermann wrote:
Am 16.02.21 um 14:27 schrieb Thomas Zimmermann:
Hi
this is a shadow-buffered plane. Did you consider using the new helpers
for shadow-buffered planes? They will map the user BO
Hi,
On Wed, Feb 10, 2021 at 05:22:37PM +0100, Marjan Pascolo wrote:
> On Allwinner SoC interrupt debounce can be controlled by two oscillator
> (32KHz and 24MHz) and a prescale divider.
> Oscillator and prescale divider are set through
> device tree property "input-debounce" which have 1uS accurac
This series attempts to enable V3D on BCM2711, the SoC available on the
Raspberry Pi 4 family of boards.
Due to the lack of documentation some things are taken as it from
testing/downstream implementation[1], which I'm hilighting here:
- It's not clear that the following is 100% true, maybe someo
BCM2711, Raspberry Pi 4's SoC, contains a V3D core. So add its specific
compatible to the bindings.
Signed-off-by: Nicolas Saenz Julienne
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/device
Runtime PM doesn't seem to work correctly on this driver. On top of
that, commit 8b6864e3e138 ("drm/v3d/v3d_drv: Remove unused static
variable 'v3d_v3d_pm_ops'") hints that it most likely never did as the
driver's PM ops were not hooked-up.
So, in order to support regular operation with V3D on BCM
Add compatible string and Kconfig options for bcm2711.
Signed-off-by: Nicolas Saenz Julienne
---
drivers/gpu/drm/v3d/Kconfig | 2 +-
drivers/gpu/drm/v3d/v3d_drv.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/v3d/Kconfig b/drivers/gpu/drm/v3d/Kconfig
inde
This series adds :
1. sync up of i915_pciids.h with kernel
2. Support for ADLS platform
Tejas Upadhyay (2):
intel: sync i915_pciids.h with kernel
intel: add INTEL_ADLS_IDS to the pciids list
intel/i915_pciids.h | 177 --
intel/intel_chipset.c | 1 +
Align with kernel commits:
0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
04057a1afc75 ("drm/i915: Sort EHL/JSL PCI IDs")
0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")
605f9c290c1a ("drm/i915: Sort ICL PCI IDs")
514dc424ce4f ("drm/i915: Sort CNL PCI IDs")
32d4ec9a1681
This enables drm_intel_bufmgr on ADLS
Signed-off-by: Tejas Upadhyay
---
intel/intel_chipset.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c
index 439db3e5..8ec36f82 100644
--- a/intel/intel_chipset.c
+++ b/intel/intel_chipset.c
@@ -35,6 +35,7 @
Deepak Rawat writes:
> DRM driver for hyperv synthetic video device, based on hyperv_fb
> framebuffer driver. Also added config option "DRM_HYPERV" to enabled
> this driver.
>
> v2:
> - Add support for gen2 VM
> - Fixed review comments
>
> v3:
> - Split into multiple files as suggested by Thomas
Hi
Am 16.02.21 um 16:57 schrieb Sakari Ailus:
Hi all,
On merging --- it would seem everyone is happy with merging this
through the drm-misc tree. The last patch should wait until all
users are gone for sure, probably to the next kernel release.
There are no users
Mostly around locking.
v2:
- use 'vmap' instead of 'kmap'.
- rework cursor update workflow.
Gerd Hoffmann (11):
drm/qxl: properly handle device init failures
drm/qxl: more fence wait rework
drm/qxl: use ttm bo priorities
drm/qxl: fix lockdep issue in qxl_alloc_release_reserved
drm/qxl
Specifically do not try release resources which where
not allocated in the first place.
Cc: Tong Zhang
Tested-by: Tong Zhang
Signed-off-by: Gerd Hoffmann
Acked-by: Thomas Zimmermann
---
drivers/gpu/drm/qxl/qxl_display.c | 3 +++
drivers/gpu/drm/qxl/qxl_kms.c | 4
2 files changed, 7 i
Use the correct vmap variant. We don't have a reservation here,
so we can't use the _locked version.
Signed-off-by: Gerd Hoffmann
Acked-by: Thomas Zimmermann
---
drivers/gpu/drm/qxl/qxl_prime.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/qxl/qxl_prim
Add helper functions to create and move the cursor.
Create the cursor_bo in prepare_fb callback, in the
atomic_commit callback we only send the update command
to the host.
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/qxl/qxl_display.c | 248 --
1 file changed, 133
Call qxl_bo_unpin (which does a reservation) without holding the
release_mutex lock. Fixes lockdep (correctly) warning on a possible
deadlock.
Fixes: 65ffea3c6e73 ("drm/qxl: unpin release objects")
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/qxl/qxl_release.c | 13 ++---
1 file cha
Allow to set priorities for buffer objects. Use priority 1 for surface
and cursor command releases. Use priority 0 for drawing command
releases. That way the short-living drawing commands are first in line
when it comes to eviction, making it *much* less likely that
ttm_bo_mem_force_space() pick
Add vmap/vunmap variants which reserve (and pin) the bo.
They can be used in case the caller doesn't hold a reservation
for the bo.
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/qxl/qxl_object.h | 2 ++
drivers/gpu/drm/qxl/qxl_object.c | 36
2 files changed,
Try avoid re-introducing locking bugs.
Signed-off-by: Gerd Hoffmann
Acked-by: Thomas Zimmermann
---
drivers/gpu/drm/qxl/qxl_object.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c
index 82c3bf195ad6..6e26d70f2f07 10064
Move qxl_io_notify_oom() call into wait condition.
That way the driver will call it again if one call
wasn't enough.
Also allows to remove the extra dma_fence_is_signaled()
check and the goto.
Fixes: 5a838e5d5825 ("drm/qxl: simplify qxl_fence_wait")
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/
Append _locked to Make clear that these functions should be called with
reserved bo's only. While being at it also rename kmap -> vmap.
No functional change.
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/qxl/qxl_object.h | 4 ++--
drivers/gpu/drm/qxl/qxl_display.c | 14 +++---
dri
Pure code motion, no functional change.
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/qxl/qxl_display.c | 61 +--
1 file changed, 34 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/qxl/qxl_display.c
b/drivers/gpu/drm/qxl/qxl_display.c
index f106da9178
Use the correct vmap variant. We don't hold a reservation here,
so we can't use the _locked variant. We can drop the pin because
qxl_bo_vmap will do that for us.
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/qxl/qxl_display.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
dif
On Tuesday, February 16th, 2021 at 1:39 AM, Deepak Rawat
wrote:
> +static int hyperv_conn_init(struct hyperv_drm_device *hv)
> +{
> + drm_connector_helper_add(&hv->connector,
> &hyperv_connector_helper_funcs);
> + return drm_connector_init(&hv->dev, &hv->connector,
> +
On 2/17/2021 8:36 AM, Rob Clark wrote:
On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as a ENOENT error,
to fix the case where the kernel was compiled without CONFIG_NVMEM.
Fixes: fe7952c629da ("drm/msm: Add speed-bin support to
Ping
Andrey
On 2/16/21 12:07 PM, Andrey Grodzovsky wrote:
Problem: If scheduler is already stopped by the time sched_entity
is released and entity's job_queue not empty I encountred
a hang in drm_sched_entity_flush. This is because drm_sched_entity_is_idle
never becomes false.
Fix: In drm_sche
Hi Jagan,
On 20/01/2021 12:21, Jagan Teki wrote:
SN65DSI84 is a Single Channel DSI to Dual-link LVDS bridge from
Texas Instruments.
SN65DSI83, SN65DSI85 are variants of the same family of bridge
controllers.
Right now the bridge driver is supporting a single link, dual-link
support requires to
On Tue, 2021-02-16 at 09:21 +0100, Thomas Zimmermann wrote:
> Hi,
>
> fantastic. Thanks for sending an update. There's been a some bitrot
> meanwhile. Review below.
Thanks Thomas for the review. Will update as per review in next
iteration.
>
> Am 16.02.21 um 01:39 schrieb Deepak Rawat:
> > DRM
On Wed, 2021-02-17 at 13:07 +0100, Vitaly Kuznetsov wrote:
> Deepak Rawat writes:
>
> > DRM driver for hyperv synthetic video device, based on hyperv_fb
> > framebuffer driver. Also added config option "DRM_HYPERV" to
> > enabled
> > this driver.
> >
> > v2:
> > - Add support for gen2 VM
> > - F
On Wed, 2021-02-17 at 13:22 +, Simon Ser wrote:
> On Tuesday, February 16th, 2021 at 1:39 AM, Deepak Rawat <
> drawat.fl...@gmail.com> wrote:
>
> > +static int hyperv_conn_init(struct hyperv_drm_device *hv)
> > +{
> > + drm_connector_helper_add(&hv->connector,
> > &hyperv_connector_helpe
Deepak Rawat writes:
> On Wed, 2021-02-17 at 13:07 +0100, Vitaly Kuznetsov wrote:
>> > +++ b/drivers/gpu/drm/hyperv/hyperv_drm.h
>> > @@ -0,0 +1,51 @@
>> > +/* SPDX-License-Identifier: GPL-2.0 */
>> > +/*
>> > + * Copyright 2012-2021 Microsoft
>>
>> Out of pure curiosity, where does '2012' come
Robin Murphy 于2021年2月16日周二 下午10:22写道：
> On 2021-01-05 13:46, Kevin Tang wrote:
> > Adds DPU(Display Processor Unit) support for the Unisoc's display
> subsystem.
> > It's support multi planes, scaler, rotation, PQ(Picture Quality) and
> more.
> >
> > Cc: Orson Zhai
> > Cc: Chunyan Zhang
> > Sig
On Mon 2021-02-15 16:39:26, Andy Shevchenko wrote:
> +Cc: Sakari and printk people
>
> On Mon, Feb 15, 2021 at 4:28 PM Christian König
> wrote:
> > Am 15.02.21 um 15:21 schrieb Andy Shevchenko:
> > > We have already few similar implementation and a lot of code that can
> > > benefit
> > > of the
Add hbr3_hbr2 voltage and pre-emphasis swing table to support
HBR3 link rate
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_panel.c | 4
drivers/phy/qualcomm/phy-qcom-qmp.c | 24 ++--
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/g
On Wed, 17 Feb 2021, Petr Mladek wrote:
> On Mon 2021-02-15 16:39:26, Andy Shevchenko wrote:
>> +Cc: Sakari and printk people
>>
>> On Mon, Feb 15, 2021 at 4:28 PM Christian König
>> wrote:
>> > Am 15.02.21 um 15:21 schrieb Andy Shevchenko:
>> > > We have already few similar implementation and a
When mmapping the shmem, it would previously adjust the pgoff in the
vm_area_struct to remove the fake offset that is added to be able to
identify the buffer. This patch removes the adjustment and makes the
fault handler use the vm_fault address to calculate the page offset
instead. Although using
https://bugzilla.kernel.org/show_bug.cgi?id=203905
m11.1l1@gmail.com changed:
What|Removed |Added
CC||m11.1l1@gmail.com
--- Comment
https://bugzilla.kernel.org/show_bug.cgi?id=203905
--- Comment #24 from m11.1l1@gmail.com ---
Related to the previous post:
https://www.linux.org/threads/failed-to-start-load-save-screen-backlight-brightness-of-amdgpu_bl1.31998/#post-113058
--
You may reply to this email to add a comment.
Hey Adrien,
Thanks for submitting this!
On Mon, 15 Feb 2021 at 00:31, Adrien Grassein wrote:
>
> Lontium Lt8912 is a DSI to HDMI bridge.
>
> Signed-off-by: Adrien Grassein
> ---
> MAINTAINERS | 1 +
> drivers/gpu/drm/bridge/Kconfig | 14 +
> drivers/gpu/
Quoting Kuogee Hsieh (2021-02-17 08:58:42)
> Add hbr3_hbr2 voltage and pre-emphasis swing table to support
> HBR3 link rate
>
> Signed-off-by: Kuogee Hsieh
> ---
> drivers/gpu/drm/msm/dp/dp_panel.c | 4
> drivers/phy/qualcomm/phy-qcom-qmp.c | 24 ++--
This spans to su
From: Tejas Upadhyay
For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.
v2:
* Move Wa_14010685332 into it's own function - vsyrjala
* Add TODO comment about figuring out if we can move this workaround - imre
v3:
* Rename cnp_irq_post_reset() to cnp_display_clock_wa()
* Add T
On Tue, 2021-02-16 at 14:34 +0200, Imre Deak wrote:
> It's possible to modeset a connector/mst port that has a 0 full_pbn
> value: if the sink on the port deasserts its HPD and a branch device
> reports this via a CSN with the port's ddps=0 and pdt!=NONE the driver
> clears full_pbn, but the corres
On Tue, Feb 16, 2021 at 09:53:37PM -0500, Lyude Paul wrote:
> While reviewing patches for handling workarounds related to gen9 bc, Imre
> from Intel discovered that we're using spt_hpd_irq_setup() on ICP+ PCHs
> despite it being almost the same as icp_hpd_irq_setup(). Since we need to
> be calling
On Wed, Feb 17, 2021 at 01:07:11PM -0500, Lyude Paul wrote:
> On Tue, 2021-02-16 at 14:34 +0200, Imre Deak wrote:
> > It's possible to modeset a connector/mst port that has a 0 full_pbn
> > value: if the sink on the port deasserts its HPD and a branch device
> > reports this via a CSN with the port
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen wrote:
> On 2/17/2021 8:36 AM, Rob Clark wrote:
> >On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
> >>
> >>Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as a ENOENT error,
> >>to fix the case where the kernel was compiled
Am 17.02.21 um 13:32 schrieb Gerd Hoffmann:
Move qxl_io_notify_oom() call into wait condition.
That way the driver will call it again if one call
wasn't enough.
Also allows to remove the extra dma_fence_is_signaled()
check and the goto.
Fixes: 5a838e5d5825 ("drm/qxl: simplify qxl_fence_wait")
Am 17.02.21 um 13:32 schrieb Gerd Hoffmann:
Allow to set priorities for buffer objects. Use priority 1 for surface
and cursor command releases. Use priority 0 for drawing command
releases. That way the short-living drawing commands are first in line
when it comes to eviction, making it *much
Am 17.02.21 um 13:32 schrieb Gerd Hoffmann:
Call qxl_bo_unpin (which does a reservation) without holding the
release_mutex lock. Fixes lockdep (correctly) warning on a possible
deadlock.
Fixes: 65ffea3c6e73 ("drm/qxl: unpin release objects")
Signed-off-by: Gerd Hoffmann
Acked-by: Thomas Zi
Am 17.02.21 um 13:32 schrieb Gerd Hoffmann:
Append _locked to Make clear that these functions should be called with
reserved bo's only. While being at it also rename kmap -> vmap.
No functional change.
Signed-off-by: Gerd Hoffmann
Acked-by: Thomas Zimmermann
---
drivers/gpu/drm/qxl/q
Am 17.02.21 um 13:32 schrieb Gerd Hoffmann:
Add vmap/vunmap variants which reserve (and pin) the bo.
They can be used in case the caller doesn't hold a reservation
for the bo.
Signed-off-by: Gerd Hoffmann
Acked-by: Thomas Zimmermann
---
drivers/gpu/drm/qxl/qxl_object.h | 2 ++
driver
Hi Neil,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.11 next-20210217]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as
On Wed, Feb 17, 2021 at 11:08 AM Jordan Crouse wrote:
>
> On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen wrote:
> > On 2/17/2021 8:36 AM, Rob Clark wrote:
> > >On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
> > >>
> > >>Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as
On Sat, 13 Feb 2021 12:15:10 +0200, Mikko Perttunen wrote:
> Convert the original Host1x bindings to YAML and add new bindings for
> NVDEC, now in a more appropriate location. The old text bindings
> for Host1x and engines are still kept at display/tegra/ since they
> encompass a lot more engines t
On Mon, 15 Feb 2021 00:29:03 +0100, Adrien Grassein wrote:
> Lontium LT8912 is a DSI to HDMI bridge.
>
> Signed-off-by: Adrien Grassein
> ---
> .../display/bridge/lontium,lt8912.yaml| 102 ++
> MAINTAINERS | 5 +
> 2 files changed, 107
On 2/17/21 3:18 PM, Rob Clark wrote:
On Wed, Feb 17, 2021 at 11:08 AM Jordan Crouse wrote:
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen wrote:
On 2/17/2021 8:36 AM, Rob Clark wrote:
On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
Ignore nvmem_cell_get() EOPNOTSUPP error
On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay
>
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaroun
On Wed, 2021-02-17 at 23:18 +0200, Imre Deak wrote:
> On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> > From: Tejas Upadhyay
> >
> > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > setup TGP PCH.
> >
> > v2:
> > * Move Wa_14010685332 into it's own function - vsyrjala
>
Am 16.02.21 um 18:07 schrieb Andrey Grodzovsky:
Problem: If scheduler is already stopped by the time sched_entity
is released and entity's job_queue not empty I encountred
a hang in drm_sched_entity_flush. This is because drm_sched_entity_is_idle
never becomes false.
Fix: In drm_sched_fini detac
On 2/17/21 4:32 PM, Christian König wrote:
Am 16.02.21 um 18:07 schrieb Andrey Grodzovsky:
Problem: If scheduler is already stopped by the time sched_entity
is released and entity's job_queue not empty I encountred
a hang in drm_sched_entity_flush. This is because drm_sched_entity_is_idle
never
Am 17.02.21 um 22:36 schrieb Andrey Grodzovsky:
On 2/17/21 4:32 PM, Christian König wrote:
Am 16.02.21 um 18:07 schrieb Andrey Grodzovsky:
Problem: If scheduler is already stopped by the time sched_entity
is released and entity's job_queue not empty I encountred
a hang in drm_sched_entity_fl
Will do.
Andrey
On 2/17/21 4:37 PM, Christian König wrote:
Am 17.02.21 um 22:36 schrieb Andrey Grodzovsky:
On 2/17/21 4:32 PM, Christian König wrote:
Am 16.02.21 um 18:07 schrieb Andrey Grodzovsky:
Problem: If scheduler is already stopped by the time sched_entity
is released and entity's
On Sat, Feb 13, 2021 at 12:15:10PM +0200, Mikko Perttunen wrote:
> Convert the original Host1x bindings to YAML and add new bindings for
> NVDEC, now in a more appropriate location. The old text bindings
> for Host1x and engines are still kept at display/tegra/ since they
> encompass a lot more eng
Hi Tomi,
> Il 17/02/2021 07:41 Tomi Valkeinen ha
> scritto:
>
>
> On 16/02/2021 22:22, Dario Binacchi wrote:
> > The fdd property of the tilcdc_panel_info structure must set the reqdly
> > bit field (bit 12 to 19) of the raster control register. The previous
> > statement set the least signi
Problem: If scheduler is already stopped by the time sched_entity
is released and entity's job_queue not empty I encountred
a hang in drm_sched_entity_flush. This is because drm_sched_entity_is_idle
never becomes false.
Fix: In drm_sched_fini detach all sched_entities from the
scheduler's run queu
On Mon, Feb 15, 2021 at 12:29:03AM +0100, Adrien Grassein wrote:
> Lontium LT8912 is a DSI to HDMI bridge.
>
> Signed-off-by: Adrien Grassein
> ---
> .../display/bridge/lontium,lt8912.yaml| 102 ++
> MAINTAINERS | 5 +
> 2 files changed
On Thursday, 11 February 2021 6:55:10 PM AEDT Christoph Hellwig wrote:
> On Wed, Feb 10, 2021 at 01:59:13PM -0400, Jason Gunthorpe wrote:
> > Really what you want to do here is leave the CPU page in the VMA and
> > the page tables where it started and deny CPU access to the page. Then
> > all the p
Drop limit link rate at HBR2 to support link rate
upto HBR3.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_panel.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c
b/drivers/gpu/drm/msm/dp/dp_panel.c
index 9cc8166..63112fa 100644
--- a/drivers
On Tue, 2021-02-09 at 12:15 -0600, Rob Herring wrote:
> On Wed, Jan 27, 2021 at 04:51:23PM +0800, Liu Ying wrote:
> > This patch adds a drm bridge driver for i.MX8qxp pixel link to display
> > pixel interface(PXL2DPI). The PXL2DPI interfaces the pixel link 36-bit
> > data output and the DSI contro
Hi Rob Herring, thanks for the comments.
On Tue, Feb 09, 2021 at 01:30:10PM -0600, Rob Herring wrote:
> On Thu, Jan 28, 2021 at 11:08:26AM +0800, Xin Ji wrote:
> > Add 'bus-type' and 'data-lanes' define for port0, add HDCP support
> > flag and DP tx lane0 and lane1 swing register array define.
> >
Hi,
This is the v4 series to add some DRM bridge drivers support
for i.MX8qm/qxp SoCs.
The bridges may chain one by one to form display pipes to support
LVDS displays. The relevant display controller is DPU embedded in
i.MX8qm/qxp SoCs.
The DPU KMS driver can be found at:
https://www.spinics.ne
This patch allows LVDS PHYs to be configured through
the generic functions and through a custom structure
added to the generic union.
The parameters added here are based on common LVDS PHY
implementation practices. The set of parameters
should cover all potential users.
Cc: Kishon Vijay Abraham
This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
The RGB pixels with padding low per component are transmitted on a 30-bit
input bus(10-bit per component) from a display controller or a 36-bit
output bu
This patch adds documentations for RGB666_1X30_CPADLO, RGB888_1X30_CPADLO,
RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp
pixel combiner. The RGB pixels with padding low per component are
transmitted on a 30-bit input bus(10-bit per component) from a display
controller o
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v3->v4:
* No change.
v2->v3:
* Add Rob's R-b tag.
v1->v2:
* Use graph schema. (Laurent)
* Use enum instead of oneOf + const for the reg property of pixel combiner
channels. (Rob)
.
This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner.
The pixel combiner takes two output streams from a single display
controller and manipulates the two streams to support a number
of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured
as either one screen, two scre
This patch adds bindings for i.MX8qm/qxp display pixel link.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v3->v4:
* No change.
v2->v3:
* Add Rob's R-b tag.
v1->v2:
* Use graph schema. (Laurent)
* Require all four pixel link output ports. (Laurent)
* Mention pixel link is accessed via S
This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
The pixel link forms a standard asynchronous linkage between
pixel sources(display controller or camera module) and pixel
consumers(imaging or displays). It consists of two distinct
functions, a pixel transfer function and a c
This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
Signed-off-by: Liu Ying
---
v3->v4:
* Add 'fsl,sc-resource' property. (Rob)
v2->v3:
* Drop 'fsl,syscon' property. (Rob)
* Mention the CSR module controls PXL2DPI.
v1->v2:
* Use graph schema. (Laurent)
.../display/bridge/fsl,imx
This patch adds a drm bridge driver for i.MX8qxp pixel link to display
pixel interface(PXL2DPI). The PXL2DPI interfaces the pixel link 36-bit
data output and the DSI controller’s MIPI-DPI 24-bit data input, and
inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap
the pixel color c
This patch adds a helper to support LDB drm bridge drivers for
i.MX SoCs. Helper functions exported from this driver should
implement common logics for all LDB modules embedded in i.MX SoCs.
Signed-off-by: Liu Ying
---
v3->v4:
* No change.
v2->v3:
* Call syscon_node_to_regmap() to get regmap in
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v3->v4:
* Add Rob's R-b tag.
v2->v3:
* Drop 'fsl,syscon' property. (Rob)
* Mention the CSR module controls LDB.
v1->v2:
* Use graph schema. (Laurent)
* Side note i.MX8qxp LDB
This patch adds a drm bridge driver for i.MX8qxp LVDS display bridge(LDB)
which is officially named as pixel mapper. The LDB has two channels.
Each of them supports up to 24bpp parallel input color format and can map
the input to VESA or JEIDA standards. The two channels cannot be used
simultaneo
This patch adds a drm bridge driver for i.MX8qm LVDS display bridge(LDB)
which is officially named as pixel mapper. The LDB has two channels.
Each of them supports up to 30bpp parallel input color format and can
map the input to VESA or JEIDA standards. The two channels can be used
simultaneously
Add myself as the maintainer of DRM bridge drivers for i.MX SoCs.
Signed-off-by: Liu Ying
---
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9d241b8..d96c917 100644
---
On 17-02-21, 09:36, Stephen Boyd wrote:
> Quoting Kuogee Hsieh (2021-02-17 08:58:42)
> > Add hbr3_hbr2 voltage and pre-emphasis swing table to support
> > HBR3 link rate
> >
> > Signed-off-by: Kuogee Hsieh
> > ---
> > drivers/gpu/drm/msm/dp/dp_panel.c | 4
> > drivers/phy/qualcomm/phy-qc
> -Original Message-
> From: Lyude Paul
> Sent: 18 February 2021 02:49
> To: Deak, Imre
> Cc: intel-...@lists.freedesktop.org; Surendrakumar Upadhyay, TejaskumarX
> ; Roper, Matthew D
> ; Jani Nikula ;
> Joonas Lahtinen ; Vivi, Rodrigo
> ; David Airlie ; Daniel Vetter
> ; open list:DRM
On Fri, Feb 05, 2021 at 01:33:46PM +0100, Robert Foss wrote:
> Hey Xin,
Hi Robert Foss, thanks for the comment, I'll split this patch at this seria.
Thanks,
Xin
>
> On Thu, 28 Jan 2021 at 04:12, Xin Ji wrote:
> >
> > Add MIPI rx DPI input support
> >
> > Reported-by: kernel test robot
> > Signed
* Tomi Valkeinen [210217 07:42]:
> On 11/02/2021 19:35, Tony Lindgren wrote:
> > * Tomi Valkeinen [210211 07:35]:
> >> On 08/02/2021 19:55, Tony Lindgren wrote:
> >>> Hi,
> >>>
> >>> * Tomi Valkeinen [201124 12:47]:
> From: Sebastian Reichel
>
> In preparation for removing custom
Hi Nicolas,
On Thu, Feb 11, 2021 at 11:33:55AM +0800, Nicolas Boichat wrote:
> Many of the DSI flags have names opposite to their actual effects,
> e.g. MIPI_DSI_MODE_EOT_PACKET means that EoT packets will actually
> be disabled. Fix this by including _NO_ in the flag names, e.g.
> MIPI_DSI_MODE_N
On Wed, Feb 17, 2021 at 01:14:42PM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 16.02.21 um 16:57 schrieb Sakari Ailus:
> > Hi all,
> >
> > On merging --- it would seem everyone is happy with merging this
> > through the drm-misc tree. The last patch should wait until all
> > users are
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