On 2/10/21 7:49 AM, Dave Stevenson wrote:
> Hi Marc.
>
> On Wed, 10 Feb 2021 at 15:30, Marc Zyngier wrote:
>>
>> Hi Maxime,
>>
>> On 2021-02-10 14:40, Maxime Ripard wrote:
>>> Hi Dave,
>>>
>>> On Tue, Feb 09, 2021 at 09:49:05AM +, Dave Stevenson wrote:
On Mon, 11 Jan 2021 at 14:23, Maxim
On Tue, Feb 9, 2021 at 5:24 PM Jordan Crouse wrote:
>
> On Mon, Feb 08, 2021 at 01:55:54PM -0500, Jonathan Marek wrote:
> > The cleanup patch broke a6xx_gmu_clear_oob, fix it by adding the missing
> > bitshift operation.
> >
> > Fixes: 555c50a4a19b ("drm/msm: Clean up GMU OOB set/clear handling")
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
Use fle
Hey,
This is super late in the cycle, but after talking it over with Dave,
it's probably best to get this in sooner rather than later. The vast
majority of the changes are simple and repetitive, but invasive in
that the constructor function signature of every sub-device module for
every chipset i
On 2/10/21 4:59 AM, Daniel Vetter wrote:
...
GPU atomic operations to sysmem are hard to categorize, because because
application
programmers could easily write programs that do a long series of atomic
operations.
Such a program would be a little weird, but it's hard to rule out.
Yeah, but we
Quoting Maxime Ripard (2021-02-10 02:29:04)
> Hi Mike, Stephen,
>
> On Tue, Feb 09, 2021 at 06:58:56PM +0100, Jernej Skrabec wrote:
> > CLK_SET_RATE_PARENT flag is checked on parent clock instead of current
> > one. Fix that.
> >
> > Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rat
On Tue, Feb 09, 2021 at 04:28:28PM -0500, Lyude Paul wrote:
> Since Intel has introduced the gen9_bc platform, a combination of
> Tigerpoint PCHs and CML CPUs, let's recognize such platforms as valid and
> avoid WARNing on them.
>
> Changes since v4:
> * Split this into it's own patch - vsyrjala
>
On Tue, Feb 09, 2021 at 04:28:30PM -0500, Lyude Paul wrote:
> Next, let's start introducing the HPD pin mappings for Intel's new gen9_bc
> platform in order to make hotplugging display connectors work. Since
> gen9_bc is just a TGP PCH along with a CML CPU, except with the same HPD
> mappings as IC
On Tue, Feb 09, 2021 at 04:28:31PM -0500, Lyude Paul wrote:
> Apparently the new gen9_bc platforms that Intel has introduced don't
> provide us with a STRAP config register to read from for initializing DDI
> B, C, and D detection. So, workaround this by hard-coding our strap config
> in intel_setu
On Wed, 2021-02-10 at 12:33 -0600, Rob Herring wrote:
> On Tue, Feb 09, 2021 at 10:13:12PM +0800, Liu Ying wrote:
> > To complement panel-simple.yaml, create panel-simple-lvds-dual-
> > ports.yaml.
> > panel-simple-lvds-dual-ports.yaml is for all simple LVDS panels
> > that
> > have dual LVDS ports
On Tue, Feb 09, 2021 at 04:28:29PM -0500, Lyude Paul wrote:
> With the introduction of gen9_bc, where Intel combines Cometlake CPUs with
> a Tigerpoint PCH, we'll need to introduce new DDC pin mappings for this
> platform in order to make all of the display connectors work. So, let's do
> that.
>
Many of the DSI flags have names opposite to their actual effects,
e.g. MIPI_DSI_MODE_EOT_PACKET means that EoT packets will actually
be disabled. Fix this by including _NO_ in the flag names, e.g.
MIPI_DSI_MODE_NO_EOT_PACKET.
Signed-off-by: Nicolas Boichat
---
I considered adding _DISABLE_ inste
Hi Omar,
On Wed 2021-02-10 @ 02:31:11 PM, Omar Emara wrote:
> If applying to GSoC will not take much time from you, I think you should apply
> regardless and leave the acceptance decision on a per-project basis.
GSoC works, literally, the other way around. Unfortunately GSoC doesn't start
with st
On Mon, Feb 08, 2021 at 06:38:59PM -0500, Lyude Paul wrote:
> Also, stop printing the DPCD register that failed, and just describe it
> instead. Saves us from having to look up each register offset when reading
> through kernel logs (plus, DPCD dumping with drm.debug |= 0x100 will give
> us that an
On Mon, Feb 08, 2021 at 06:38:58PM -0500, Lyude Paul wrote:
> If we can't read DP_EDP_PWMGEN_BIT_COUNT in
> intel_dp_aux_vesa_calc_max_backlight() but do have a valid PWM frequency
> defined in the VBT, we'll keep going in the function until we inevitably
> fail on reading DP_EDP_PWMGEN_BIT_COUNT_C
On Mon, Feb 08, 2021 at 06:38:55PM -0500, Lyude Paul wrote:
> Get rid of the extraneous switch case in here, and just open code
> edp_backlight_mode as we only ever use it once.
>
> v4:
> * Check that backlight mode is DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD, not
> DP_EDP_BACKLIGHT_CONTROL_MODE_MASK
On Mon, Feb 08, 2021 at 06:39:00PM -0500, Lyude Paul wrote:
> Since we're about to implement eDP backlight support in nouveau using the
> standard protocol from VESA, we might as well just take the code that's
> already written for this and move it into a set of shared DRM helpers.
>
> Note that t
To complement panel-simple.yaml, create panel-simple-lvds-dual-ports.yaml.
panel-simple-lvds-dual-ports.yaml is for all simple LVDS panels that
have dual LVDS ports and require only a single power-supply.
The first port receives odd pixels, and the second port receives even pixels.
Optionally, a ba
Hi Aditya,
Thanks for your review comments.
-Original Message-
From: Aditya Swarup
Sent: Wednesday, February 10, 2021 9:54 PM
To: Ram Moon, AnandX ;
intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Roper,
Matthew D ; Auld, Matthew ;
Surendrakumar Upadhyay, Tejaskumar
Dne četrtek, 11. februar 2021 ob 03:28:00 CET je Stephen Boyd napisal(a):
> Quoting Maxime Ripard (2021-02-10 02:29:04)
>
> > Hi Mike, Stephen,
> >
> > On Tue, Feb 09, 2021 at 06:58:56PM +0100, Jernej Skrabec wrote:
> > > CLK_SET_RATE_PARENT flag is checked on parent clock instead of current
> >
On 11/02/2021, Chema Casanova wrote:
>
> On 5/2/21 13:28, Yukimasa Sugizaki wrote:
>> On 05/02/2021, Eric Anholt wrote:
>>> On Thu, Feb 4, 2021 at 10:09 AM Chema Casanova
>>> wrote:
On 3/9/20 18:48, Yukimasa Sugizaki wrote:
> From: Yukimasa Sugizaki
>
> The default timeout is 5
Currently the FRL training mode (Concurrent, Sequential) and
training type (Normal, Extended) are not defined properly and
are passed as bool values in drm_helpers for pcon
configuration for FRL training.
This patch:
-Add register masks for Sequential and Normal FRL training options.
-Fixes the dr
On Wed, 2021-02-10 at 13:03 -0500, Lyude Paul wrote:
> On Wed, 2021-02-10 at 00:33 -0800, Khaled Almahallawy wrote:
> > The number of AUX retries specified in the DP specs is 7.
> > Currently, to make
> > Dell 4k monitors happier, the number of retries are 32.
> > i915 also retries 5 times (intel_d
On 2/6/2021 1:30 AM, Ville Syrjälä wrote:
On Thu, Feb 04, 2021 at 12:18:41PM +0530, Ankit Nautiyal wrote:
Currently the FRL training mode (Concurrent, Sequential) and
training type (Normal, Extended) are not defined properly and
are passed as bool values in drm_helpers for pcon
configuration fo
On 08/02/2021 19:55, Tony Lindgren wrote:
> Hi,
>
> * Tomi Valkeinen [201124 12:47]:
>> From: Sebastian Reichel
>>
>> In preparation for removing custom DSS calls from the DSI
>> panel driver, this moves support for external tearing event
>> GPIOs into the DSI host driver. This way tearing event
https://bugzilla.kernel.org/show_bug.cgi?id=206987
Jan Kokemüller (jan.kokemuel...@gmail.com) changed:
What|Removed |Added
CC||jan.kokemuel.
101 - 126 of 126 matches
Mail list logo
