From: Yongqiang Niu
ccorr ctm matrix bits will be different in mt8192
Signed-off-by: Yongqiang Niu
Signed-off-by: Hsin-Yi Wang
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 222
drivers/gpu/drm/mediatek/mtk_disp_dr
Hi Christoph,
Christoph Hellwig writes:
> diff --git a/kernel/module.c b/kernel/module.c
> index 981302f616b411..6772fb2680eb3e 100644
> --- a/kernel/module.c
> +++ b/kernel/module.c
> @@ -668,7 +668,6 @@ static struct module *find_module_all(const char *name,
> size_t len,
>
> struct modu
From: Yongqiang Niu
enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
ovl will hang up when more than 1 layer enabled.
Signed-off-by: Yongqiang Niu
Signed-off-by: Hsin-Yi Wang
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +
1 file changed, 17 insertio
On Fri, 2021-01-29 at 14:24 +0800, Hsin-Yi Wang wrote:
> On Fri, Jan 29, 2021 at 9:33 AM CK Hu wrote:
> >
> > Hi, Hsin-Yi:
> >
> > On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> > > From: Yongqiang Niu
> > >
> > > for 5 or 6 bpc panel, we need enable dither function
> > > to improve the
From: Yongqiang Niu
add support for mediatek SOC MT8192
Signed-off-by: Yongqiang Niu
Signed-off-by: Hsin-Yi Wang
---
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c| 6 +++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 ++
drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 1 +
driver
From: Yongqiang Niu
This patch add component RDMA4
Signed-off-by: Yongqiang Niu
Reviewed-by: Chun-Kuang Hu
Signed-off-by: Hsin-Yi Wang
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gp
Fixes coccicheck warning:
./drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c:616:2-8: WARNING: NULL check
before some
freeing functions is not needed.
./drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c:618:2-8: WARNING: NULL check
before some
freeing functions is not needed.
./drivers/gpu/drm/etnaviv/etn
On Thu, 28 Jan 2021 16:33:02 +0200
Andy Shevchenko wrote:
> On Thu, Jan 28, 2021 at 2:58 PM Carlis wrote:
>
> Thanks for your contribution, my comments below.
>
> > From: zhangxuezhi
>
> You probably have to configure your Git to use the same account for
> author and committer.
hi,you mea
On Fri, 2021-01-29 at 14:46 +0800, Hsin-Yi Wang wrote:
> On Fri, Jan 29, 2021 at 2:30 PM Yongqiang Niu
> wrote:
> >
> > On Fri, 2021-01-29 at 14:24 +0800, Hsin-Yi Wang wrote:
> > > On Fri, Jan 29, 2021 at 9:33 AM CK Hu wrote:
> > > >
> > > > Hi, Hsin-Yi:
> > > >
> > > > On Thu, 2021-01-28 at 19:2
This series are based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next
This series also depends on component support in mmsys[1]:
- [v4,06/10] soc: mediatek: mmsys: add component OVL_2L2
- [v4,07/10] soc: mediatek: mmsys: add component POSTMASK
- [v4,08/10] soc: mediatek: mmsys: add component
From: Quanyang Wang
When run xrandr to change resolution on Beaglebone Black board, it will
print the error information:
root@beaglebone:~# xrandr -display :0 --output HDMI-1 --mode 720x400
[drm:drm_crtc_commit_wait] *ERROR* flip_done timed out
[drm:drm_atomic_helper_wait_for_dependencies] *ERRO
On Fri, Jan 29, 2021 at 2:30 PM Yongqiang Niu
wrote:
>
> On Fri, 2021-01-29 at 14:24 +0800, Hsin-Yi Wang wrote:
> > On Fri, Jan 29, 2021 at 9:33 AM CK Hu wrote:
> > >
> > > Hi, Hsin-Yi:
> > >
> > > On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> > > > From: Yongqiang Niu
> > > >
> > > >
From: Yongqiang Niu
matrix bits of mt8183 is 12
matrix bits of mt8192 is 13
Signed-off-by: Yongqiang Niu
Signed-off-by: Hsin-Yi Wang
---
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediat
From: Yongqiang Niu
This patch add component OVL_2L2
Signed-off-by: Yongqiang Niu
Reviewed-by: Chun-Kuang Hu
Signed-off-by: Hsin-Yi Wang
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/
On Fri, Jan 29, 2021 at 9:33 AM CK Hu wrote:
>
> Hi, Hsin-Yi:
>
> On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> > From: Yongqiang Niu
> >
> > for 5 or 6 bpc panel, we need enable dither function
> > to improve the display quality
> >
> > Signed-off-by: Yongqiang Niu
> > Signed-off-by:
On Fri, Jan 29, 2021 at 3:42 PM Yongqiang Niu
wrote:
>
> On Fri, 2021-01-29 at 14:46 +0800, Hsin-Yi Wang wrote:
> > On Fri, Jan 29, 2021 at 2:30 PM Yongqiang Niu
> > wrote:
> > >
> > > On Fri, 2021-01-29 at 14:24 +0800, Hsin-Yi Wang wrote:
> > > > On Fri, Jan 29, 2021 at 9:33 AM CK Hu wrote:
> >
From: Yongqiang Niu
This patch add component POSTMASK,
Signed-off-by: Yongqiang Niu
Signed-off-by: Hsin-Yi Wang
---
drivers/gpu/drm/mediatek/Makefile| 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 ++
From: Yongqiang Niu
Add mtk mutex support for MT8192 SoC.
Signed-off-by: Yongqiang Niu
Signed-off-by: Hsin-Yi Wang
---
drivers/soc/mediatek/mtk-mutex.c | 35
1 file changed, 35 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK,
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/Makefile| 1 +
> drivers/gpu/drm/mediatek/mtk_disp_dr
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
> ovl will hang up when more than 1 layer enabled.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-
On Fri, 2021-01-29 at 16:32 +0800, Yongqiang Niu wrote:
> On Fri, 2021-01-29 at 16:18 +0800, CK Hu wrote:
> > Hi, Hsin-Yi:
> >
> > On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> > > From: Yongqiang Niu
> > >
> > > This patch add component POSTMASK,
> > >
> > > Signed-off-by: Yongqiang
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> matrix bits of mt8183 is 12
> matrix bits of mt8192 is 13
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 22 +++---
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8192 SoC.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 35 +
On Mon, Jan 11, 2021 at 07:45:04PM +0530, Sai Prakash Ranjan wrote:
> Add a new page protection flag IOMMU_LLC which can be used
> by non-coherent masters to set cacheable memory attributes
> for an outer level of cache called as last-level cache or
> system cache. Initial user of this page protect
Support for Moorestown and Medfield platforms is being removed from
the kernel. So here's a patch to remove the related code from the
gma500 driver. On top of that I also cleaned up the configuration
a bit.
Note that Poulsbo and Cedartrail is still there and will remain. With
the MID platforms gon
Remove the CONFIG_X86 conditionals from the source code. The driver
already depends on X86 in the Kconfig file. Also, no one has been
trying to build it on a non-x86 platform recently, or they would have
noticed that drm_ttm_cache_flush() doesn't exist.
Signed-off-by: Thomas Zimmermann
---
drive
The gma500 driver does not use TTM.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/gma500/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/gma500/Kconfig b/drivers/gpu/drm/gma500/Kconfig
index 02de5970d490..405f718b884c 100644
--- a/drivers/gpu/drm/gma500/Kconfig
With support for the MID-related chips removed, only support for
desktop chips is left in the driver. So just build the complete
driver if DRM_GMA500 has been selected. Anyone who wants to enable
the Poulsbo code would probably also want the Cedarview code.
Signed-off-by: Thomas Zimmermann
---
d
On Fri, Jan 29, 2021 at 7:01 AM carlis wrote:
> On Thu, 28 Jan 2021 16:33:02 +0200
> Andy Shevchenko wrote:
> > On Thu, Jan 28, 2021 at 2:58 PM Carlis wrote:
> >
> > Thanks for your contribution, my comments below.
> >
> > > From: zhangxuezhi
> >
> > You probably have to configure your Git to u
On Fri, Jan 29, 2021 at 12:23:08PM +0200, Andy Shevchenko wrote:
> On Fri, Jan 29, 2021 at 7:01 AM carlis wrote:
> > On Thu, 28 Jan 2021 16:33:02 +0200
> > Andy Shevchenko wrote:
> > > On Thu, Jan 28, 2021 at 2:58 PM Carlis wrote:
> > >
> > > Thanks for your contribution, my comments below.
> >
On Fri, Jan 29, 2021 at 10:56 AM Thomas Zimmermann wrote:
>
> Support for Moorestown and Medfield platforms is being removed from
> the kernel. So here's a patch to remove the related code from the
> gma500 driver. On top of that I also cleaned up the configuration
> a bit.
>
> Note that Poulsbo a
Hi Rob,
Any comments on this series, please?
On Tue, Jan 19, 2021 at 8:15 PM Fabio Estevam wrote:
>
> Issuing a 'reboot' command in i.MX5 leads to the following flow:
>
> [ 24.557742] [] (msm_atomic_commit_tail) from []
> (commit_tail+0xa4/0x1b0)
> [ 24.566349] [] (commit_tail) from []
> (dr
Hi
Am 29.01.21 um 11:46 schrieb Patrik Jakobsson:
On Fri, Jan 29, 2021 at 10:56 AM Thomas Zimmermann wrote:
Support for Moorestown and Medfield platforms is being removed from
the kernel. So here's a patch to remove the related code from the
gma500 driver. On top of that I also cleaned up the
From: Colin Ian King
Currently there are three error return paths that don't kfree object
caps. Fix this by performing the allocation of caps after the checks
and error return paths to avoid the premature allocation and memory
leaking.
Addresses-Coverity: ("Resource leak")
Fixes: 555fc7fbb2a2 (
On Fri, Oct 16, 2020 at 12:04 PM John Stultz wrote:
>
> On Thu, Oct 8, 2020 at 4:51 AM Brian Starkey wrote:
> > On Sat, Oct 03, 2020 at 04:02:57AM +, John Stultz wrote:
> > > @@ -393,6 +424,16 @@ static int system_heap_allocate(struct dma_heap
> > > *heap,
> > > /* just return,
Am 28.01.21 um 11:01 schrieb Pekka Paalanen:
On Wed, 27 Jan 2021 12:01:55 +0100
Christian König wrote:
Somewhat correct. This interface here really doesn't make sense since
the file descriptor representation of DMA-buf is only meant to be used
for short term usage.
E.g. the idea is that you c
Factor the code to check if a pipe is currently enabled out of
assert_pipe() and put it in a new intel_pipe_is_enabled() helper,
so that it can be re-used without copy-pasting it.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_display.c | 20 ++--
drivers/gpu
As explained by a long comment block, on VLV intel_setup_outputs()
sometimes thinks there might be an eDP panel connected while there is none.
In this case intel_setup_outputs() will call intel_dp_init() to check.
In this scenario vlv_find_free_pps() ends up selecting pipe A for the pps,
even thou
On Fri, Jan 29, 2021 at 2:47 PM carlis wrote:
> On Fri, 29 Jan 2021 12:23:08 +0200
> Andy Shevchenko wrote:
> > On Fri, Jan 29, 2021 at 7:01 AM carlis wrote:
> > > On Thu, 28 Jan 2021 16:33:02 +0200
> > > Andy Shevchenko wrote:
> > > > On Thu, Jan 28, 2021 at 2:58 PM Carlis
> > > > wrote:
...
On Fri, Jan 29, 2021 at 2:54 PM carlis wrote:
> On Fri, 29 Jan 2021 12:23:08 +0200
> Andy Shevchenko wrote:
> > On Fri, Jan 29, 2021 at 7:01 AM carlis wrote:
> > > On Thu, 28 Jan 2021 16:33:02 +0200
> > > Andy Shevchenko wrote:
...
> > This one is not like I suggested.
> I don't think I have
On Fri, 29 Jan 2021 13:18:01 +0100
Christian König wrote:
> Am 28.01.21 um 11:01 schrieb Pekka Paalanen:
> > On Wed, 27 Jan 2021 12:01:55 +0100
> > Christian König wrote:
> >
> >> Somewhat correct. This interface here really doesn't make sense since
> >> the file descriptor representation of D
On Friday, January 29th, 2021 at 3:13 PM, Pekka Paalanen
wrote:
> > Re-importing it adds quite a huge CPU overhead to both userspace as well
> > as the kernel.
>
> Perhaps, but so far it seems no-one has noticed the overhead, with Mesa
> at least.
>
> I happily stand corrected.
Note, all of thi
Am 29.01.21 um 15:17 schrieb Simon Ser:
On Friday, January 29th, 2021 at 3:13 PM, Pekka Paalanen
wrote:
Re-importing it adds quite a huge CPU overhead to both userspace as well
as the kernel.
Perhaps, but so far it seems no-one has noticed the overhead, with Mesa
at least.
I happily stand c
On Fri, Jan 29, 2021 at 10:56 AM Thomas Zimmermann wrote:
>
> Medfield is an outdated mobile platform with apparently no users left.
> Remove it from gma500.
>
> Signed-off-by: Thomas Zimmermann
Great, finally we get rid of that DSI code :)
Signed-off-by: Patrik Jakobsson
_
On Fri, Jan 29, 2021 at 3:56 PM carlis wrote:
> On Fri, 29 Jan 2021 12:23:08 +0200
> Andy Shevchenko wrote:
We are almost there, I have no idea what Noralf or others are going to
say though.
...
> Hi, I apologize for what I said in the previous two emails. I missed
> one email you sent before,
On Fri, Jan 29, 2021 at 10:56 AM Thomas Zimmermann wrote:
>
> Moorestown is an outdated mobile platform with apparently no users
> left. Remove it from gma500. The MID chip-setup code in mid_bios.c
> is now unused, so remove it as well.
>
> Signed-off-by: Thomas Zimmermann
As stated earlier. Thi
On Fri, Jan 29, 2021 at 10:56 AM Thomas Zimmermann wrote:
>
> With support for the MID-related chips removed, only support for
> desktop chips is left in the driver. So just build the complete
> driver if DRM_GMA500 has been selected. Anyone who wants to enable
> the Poulsbo code would probably al
On Fri, Jan 29, 2021 at 10:56 AM Thomas Zimmermann wrote:
>
> The gma500 driver does not use TTM.
>
> Signed-off-by: Thomas Zimmermann
Thanks!
Signed-off-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/Kconfig | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/gma500
On Fri, Jan 29, 2021 at 10:56 AM Thomas Zimmermann wrote:
>
> Remove the CONFIG_X86 conditionals from the source code. The driver
> already depends on X86 in the Kconfig file. Also, no one has been
> trying to build it on a non-x86 platform recently, or they would have
> noticed that drm_ttm_cache
Hi Patrik
Am 29.01.21 um 15:33 schrieb Patrik Jakobsson:
On Fri, Jan 29, 2021 at 10:56 AM Thomas Zimmermann wrote:
With support for the MID-related chips removed, only support for
desktop chips is left in the driver. So just build the complete
driver if DRM_GMA500 has been selected. Anyone wh
Am 28.01.21 um 18:23 schrieb Andrey Grodzovsky:
On 1/19/21 1:59 PM, Christian König wrote:
Am 19.01.21 um 19:22 schrieb Andrey Grodzovsky:
On 1/19/21 1:05 PM, Daniel Vetter wrote:
[SNIP]
So say writing in a loop to some harmless scratch register for many
times both for plugged
and unplugge
On Fri, Jan 29, 2021 at 4:12 PM Thomas Zimmermann wrote:
>
> Hi Patrik
>
> Am 29.01.21 um 15:33 schrieb Patrik Jakobsson:
> > On Fri, Jan 29, 2021 at 10:56 AM Thomas Zimmermann
> > wrote:
> >>
> >> With support for the MID-related chips removed, only support for
> >> desktop chips is left in the
On 21/01/2021 01:56, Yongqiang Niu wrote:
> On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
>> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
>>> move register operation into mmsys path select function
>>
>> Why do you want to do that. It seems the register access patt
From: Jake Wang
[ Upstream commit 901c1ec05ef277ce9d43cb806a225b28b3efe89a ]
[WHY]
dram clock change latencies get updated using ddr4 latency table, but
does that update does not happen before validation. This value
should not be the default and should be number received from
df for better mode
From: Aric Cyr
[ Upstream commit 8bc3d461d0a95bbcc2a0a908bbadc87e198a86a8 ]
[Why]
When no displays are currently enabled, display driver should not
disallow PSTATE switching.
[How]
Allow PSTATE switching if either the active configuration supports it,
or there are no active displays.
Tested-by
From: Vladimir Stempen
[ Upstream commit 4b08d8c78360241d270396a9de6eb774e88acd00 ]
[why]
Heavy corruption or blank screen reported on wake,
with 6k display connected and FEC enabled
[how]
When Disable/Enable stream for display pipes on HPDRX,
DC should take into account ODM split pipes.
Teste
From: Bing Guo
[ Upstream commit 4716a7c50c5c66d6ddc42401e1e0ba13b492e105 ]
Why:
Function decide_dp_link_settings() loops infinitely when required bandwidth
can't be supported.
How:
Check the required bandwidth against verified_link_cap before trying to
find a link setting for it.
Tested-by: D
From: Nicholas Kazlauskas
[ Upstream commit c74f865f14318217350aa33363577cb95b06eb82 ]
[Why & How]
These can differ per ASIC or not be present. Don't call the dcn20 ones
directly but rather the ones defined by the ASIC init table.
Tested-by: Daniel Wheeler
Signed-off-by: Nicholas Kazlauskas
R
From: Jake Wang
[ Upstream commit 901c1ec05ef277ce9d43cb806a225b28b3efe89a ]
[WHY]
dram clock change latencies get updated using ddr4 latency table, but
does that update does not happen before validation. This value
should not be the default and should be number received from
df for better mode
From: Bing Guo
[ Upstream commit 4716a7c50c5c66d6ddc42401e1e0ba13b492e105 ]
Why:
Function decide_dp_link_settings() loops infinitely when required bandwidth
can't be supported.
How:
Check the required bandwidth against verified_link_cap before trying to
find a link setting for it.
Tested-by: D
The commit a6a1f036c74e ("drm/scheduler: Job timeout handler returns
status (v3)") incorrectly uses "enum drm_task_status" for v3d and causes
a build failure. "enum drm_task_status" got changed into "enum
drm_gpu_sched_status" in v3 of the patch but the change for v3d got
lost.
Fixes: ("drm/schedu
On 1/29/21 10:16 AM, Christian König wrote:
Am 28.01.21 um 18:23 schrieb Andrey Grodzovsky:
On 1/19/21 1:59 PM, Christian König wrote:
Am 19.01.21 um 19:22 schrieb Andrey Grodzovsky:
On 1/19/21 1:05 PM, Daniel Vetter wrote:
[SNIP]
So say writing in a loop to some harmless scratch register
Am 29.01.21 um 18:35 schrieb Andrey Grodzovsky:
On 1/29/21 10:16 AM, Christian König wrote:
Am 28.01.21 um 18:23 schrieb Andrey Grodzovsky:
On 1/19/21 1:59 PM, Christian König wrote:
Am 19.01.21 um 19:22 schrieb Andrey Grodzovsky:
On 1/19/21 1:05 PM, Daniel Vetter wrote:
[SNIP]
So say wri
On Thu, Jan 28, 2021 at 2:45 PM Abaci Team
wrote:
>
> Fix the following coccicheck warning:
> ./drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:3137:35-40:
> WARNING: conversion to bool not needed here
>
> Reported-by: Abaci Robot
> Suggested-by: Yang Li
> Signed-off-by: Abaci Team
A
On Fri, Jan 29, 2021 at 7:08 AM Colin King wrote:
>
> From: Colin Ian King
>
> Currently there are three error return paths that don't kfree object
> caps. Fix this by performing the allocation of caps after the checks
> and error return paths to avoid the premature allocation and memory
> leaki
Hi Dave,
The following changes since commit 5c8fe583cce542aa0b84adc939ce85293de36e5e:
Linux 5.11-rc1 (2020-12-27 15:30:22 -0800)
are available in the Git repository at:
ssh://git.freedesktop.org/git/tegra/linux.git tags/drm/tegra/for-5.12-rc1
for you to fetch changes up to dcdfe2712b68f1e9
Quoting Vinicius Tinti (2021-01-29 18:15:19)
> By enabling -Wunreachable-code-aggressive on Clang the following code
> paths are unreachable.
That code exists as commentary and, especially for sdvo, library
functions that we may need in future.
The ivb-gt1 case => as we now set the gt level for i
The pull request you sent on Fri, 29 Jan 2021 13:46:34 +1000:
> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2021-01-29
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/6305d15e013a70a7f1c4ee65d3e035cd705e3517
Thank you!
--
Deet-doot-dot, I am a bot.
https://k
Hi Dave, Daniel,
Fixes for 5.12.
The following changes since commit a6b8720c2f85143561c3453e1cf928a2f8586ac0:
Merge tag 'amd-drm-next-5.12-2021-01-20' of
https://gitlab.freedesktop.org/agd5f/linux into drm-next (2021-01-20 13:08:18
+0100)
are available in the Git repository at:
https://g
Am 2021-01-29 um 5:28 p.m. schrieb Alex Deucher:
> drm/amdgpu: Make contiguous pinning optional
This one needs a follow-up fix, as it breaks pinning in GTT. Xinhui
should have the fix ready very soon. You may want to hold this back
until the fix lands.
Regards,
Felix
_
[AMD Public Use]
> -Original Message-
> From: Kuehling, Felix
> Sent: Friday, January 29, 2021 5:33 PM
> To: Alex Deucher ; amd-
> g...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
> airl...@gmail.com; daniel.vet...@ffwll.ch
> Cc: Deucher, Alexander ; Pan, Xinhui
> ; Koenig, Ch
Hi Dave and Daniel,
On my last pull request I incorrectly stated that
Async flips were enabled for all ilk+ platforms, while it
was only on SKL. I'm sorry about that.
I hope there's still time to include a few changes including
the actual patches that make this statement true for 5.12.
Along wit
On Thu, Jan 28, 2021 at 11:17:16AM -0800, Eric Anholt wrote:
> On Thu, Jan 28, 2021 at 10:52 AM Jordan Crouse wrote:
> >
> > On Wed, Jan 27, 2021 at 03:39:44PM -0800, Eric Anholt wrote:
> > > We were using the same force-poweron bit in the two codepaths, so they
> > > could race to have one of the
Thanks, applied to drm-misc-next.
Regards,
Qiang
On Fri, Nov 27, 2020 at 5:42 PM Qinglang Miao wrote:
>
> pm_runtime_get_sync will increment pm usage counter even it
> failed. Forgetting to putting operation will result in a
> reference leak here.
>
> A new function pm_runtime_resume_and_get is
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