This converts the v3d bindings to yaml format.
Signed-off-by: Stefan Wahren
---
Changes in V3:
- drop redundant maxItems in case we already have items defined
- fix order of reg-names enum
- tag required items in description
- add reg-names to required properties
- drop clock-names
.../devicet
On Tue, Jan 05, 2021 at 07:23:08PM +0100, Christian König wrote:
> Drivers are not supposed to init the page pool directly any more.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/radeon/radeon_ttm.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r
Hi Maxime,
Am 29.12.20 um 16:36 schrieb Stefan Wahren:
> During startup of Raspberry Pi 4 there seems to be a race between
> VC4 probing and Pulseaudio trying to open its PCM device:
>
> ASoC: error at snd_soc_dai_startup on fef05700.hdmi: -19
>
> Avoid these errors by returning EPROBE_DEFER i
> Konrad, can you please test this below change without your change?
This brings no difference, a BUG still happens. We're still calling to_a6xx_gpu
on ANY device that's probed! Too bad it won't turn my A330 into an A640..
Also, relying on disabling LLCC in the config is out of question as it ma
Replace a comma between expression statements by a semicolon.
Signed-off-by: Zheng Yongjun
---
drivers/video/fbdev/pxa3xx-gcu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fbdev/pxa3xx-gcu.c b/drivers/video/fbdev/pxa3xx-gcu.c
index 4279e13a3b58..1d26be9d
Based on the drm_connector_mode_valid, if the hibmc implementation
of mode_valid only returns MODE_OK, then we can not implement the
mode_valid function.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers
On 2021-01-08 19:09, Konrad Dybcio wrote:
Konrad, can you please test this below change without your change?
This brings no difference, a BUG still happens. We're still calling
to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330
into an A640..
Also, relying on disabling LLCC
Hi!
Thanks for the series
On Fri, Jan 08, 2021 at 03:08:05PM +0100, Thomas Zimmermann wrote:
> Daniel recently pointed out that vc4 has test in it's vmap code that
> cannot really fail. [1] I took the opportunity to cleanup vc'4 vmap
> and mmap implementations.
>
> The patches got smoke-tested b
Hi,
Thanks for those patches
On Thu, Jan 07, 2021 at 03:30:32AM +0100, Giulio Benetti wrote:
> From: Giulio Benetti
>
> It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is
> dedicated to invert DCLK polarity and this makes thing really easier than
> before. So let's handle
Hi,
Quote "
I'm not really sure why we need the first patch of this series here?
That patch only seem to undo what you did in patch 1
"
And another question (probably could be a stupid one):
in "/[PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling/" I
see you deleted:
-
Hi Marjan,
On 1/8/21 10:32 AM, Marjan Pascolo wrote:
Hi,
please don't top post, answer in-line as we do, and please use
plain-test instead of HTML. These are the standards in Mailing Lists(ML).
Quote "
I'm not really sure why we need the first patch of this series here?
That patch only se
On 19/12/20, Oliver Graute wrote:
> Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD
> to panel-simple.
>
> The panel spec from Variscite can be found at:
> https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf
some clue what bus_format and bus_flags I have t
Hi,
On 1/8/21 10:23 AM, Maxime Ripard wrote:
Hi,
Thanks for those patches
On Thu, Jan 07, 2021 at 03:30:32AM +0100, Giulio Benetti wrote:
From: Giulio Benetti
It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is
dedicated to invert DCLK polarity and this makes thing rea
Hi,
On Fri, Jan 08, 2021 at 01:23:54PM -0800, Dixit, Ashutosh wrote:
> On Tue, 24 Nov 2020 04:44:57 -0800, Tomi Valkeinen wrote:
> >
> > From: Sebastian Reichel
> >
> > The panel driver is no longer using any OMAP specific APIs, so
> > let's move it into the generic panel directory.
> >
> > Signe
Standard DRM panel driver for DSI command mode panel used by omapfb2 is also
available now. Just like the other panels its module name clashes with the
module from drivers/video/fbdev/omap2/omapfb/displays, part of the deprecated
omapfb2 fbdev driver. As omapfb2 can only be compiled when the omapdr
Hi Rob, Konrad,
On 2021-01-07 22:56, Rob Clark wrote:
> On Wed, Jan 6, 2021 at 8:50 PM Sai Prakash Ranjan
> wrote:
>>
>> On 2021-01-05 01:00, Konrad Dybcio wrote:
>> > Using this code on A5xx (and probably older too) causes a
>> > smmu bug.
>> >
>> > Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add suppor
On 1/8/21 12:36 AM, Rob Clark wrote:
> On Thu, Jan 7, 2021 at 9:20 AM Rob Clark wrote:
>>
>> On Sat, Jan 2, 2021 at 12:26 PM Iskren Chernev
>> wrote:
>>>
>>> The msm_gem_get_iova should be guarded with gpu != NULL and not aspace
>>> != NULL, because aspace is NULL when using vram carveout.
>>
On 2021-01-08 11:55, John Stultz wrote:
On Thu, Jan 7, 2021 at 12:53 AM Veera Sundaram Sankaran
wrote:
Some drivers have hardware capability to get the precise timestamp of
certain events based on which the fences are triggered. This allows it
to
set accurate timestamp factoring out any softw
On 1/8/21 2:13 AM, Philipp Zabel wrote:
> If CONFIG_OF is disabled, of_get_drm_display_mode is not compiled in,
> and drivers using it fail to build:
>
> ld: drivers/gpu/drm/imx/parallel-display.o: in function
> `imx_pd_connector_get_modes':
> parallel-display.c:(.text+0x8d): undefined refere
From: Heiko Stuebner
The Innolux n116bge panel has an eDP connector and 3*6 bits bus format.
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/panel/panel-simple.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
Not all DPU versions that are supported in this driver are supposed
to have a 8-Levels VIG QoS setting.
Move this flag to SDM845 and SC7180 specific masks.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
1 file changed, 3 insertions(+), 3
The PLL_LOCKDET_RATE_1 was being programmed with a hardcoded value
directly, but the same value was also being specified in the
dsi_pll_regs struct pll_lockdet_rate variable: let's use it!
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 3 ++-
1 file c
The DSI 10nm PLL driver was apparently ported from downstream, but some
of its "features" were not ported over, for a good reason.
Pity is that the removal of the downstream dependencies broke the clock
calculation logic for this driver and that made it impossible to use any
DSI display on at least
Not all DPU interface sub-block versions need the same value for
prog_fetch_lines_worst_case: add this to the INTF_BLK macro, so
that it becomes possible to vary it for other INTF versions.
For example, this is needed to implement support for older SoCs,
like MSM8998 and SDM630/660 and most probab
On at least MSM8998 it's possible to find Adreno 540.0 and 540.1
but I have never found any 540.2. In any case, the patchids 0-1
for A540 are completely supported by this driver and there is no
reason to disallow probing them (as they also share the same
firmware names).
Besides that, the patchid
On DPUs prior to version 4 the VBIF_XINL_QOS_LVL_REMAP_000 register
is at 0x570 offset from vbif base instead of 0x590, due to the
VBIF_XINL_QOS_RP_REMAP_000 having less instances (less possible XINs).
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 9
Add a function that returns whether the requested CTL is active or not:
this will be used in a later commit to fix command mode panel issues.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 7 +
When configuring the tearcheck, the parameters for the engine were
being set mostly as they should've been, but then it wasn't getting
configured to get the vsync indication from the TE GPIO input
because it was assumed that autorefresh could be enabled:
since a previous commit makes sure to disabl
The DSPP_BLK macro was ad-hoc made for SC7180, but this is wrong
because not all of the DPU DSPP versions can use the same DSPP block
configuration, and not all of them have got the same features.
For this reason, add two more params to the DSPP_BLK macro, so that
it is possible to specify the fea
In function dsi_pll_calc_dec_frac we are calculating the decimal
div start parameter by dividing the decimal multiple by the
fractional multiplier: the remainder of that operation is stored
to then get programmed to the fractional divider registers of
the PLL.
It's useless to call div_u64_rem to g
DRM_DEV_ERROR should be used across this entire source: convert the
pr_err prints to the first as a cleanup.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/ms
This patch series brings some fixes to the Qualcomm DPU driver, aim is
to get it prepared for "legacy" SoCs (like MSM8998, SDM630/660) and to
finally get command-mode displays working on this driver.
The series was tested against MSM8998 (the commit that introduces it to
the hw-catalog is not incl
The VCO rate was being miscalculated due to a big overlook during
the process of porting this driver from downstream to upstream:
here we are really recalculating the rate of the VCO by reading
the appropriate registers and returning a real frequency, while
downstream the driver was doing something
The number of fractional registers bits is known and already set in
the frac_bits variable of the dsi_pll_config struct here in 10nm:
remove the TODO by simply using that variable.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 4 ++--
1 file changed,
When a command mode display is used, it may be retaining the bootloader
configuration which, in most of the cases, enables the autorefresh
feature in order to keep the splash up.
Since there is no autorefresh management in this driver, wire up the
autorefresh ops in the dpu_hw_pingpong and disable
The call to dpu_encoder_phys_cmd_prepare_for_kickoff is useless as
it's unused because the serialize_wait4pp variable is never set to
true by .. anything, literally: remove the call.
While at it, also reduce indentation by inverting the check for
dpu_encoder_phys_cmd_is_master.
Signed-off-by: Ange
In function dpu_encoder_phys_cmd_wait_for_commit_done we are always
checking if the relative CTL is started by waiting for an interrupt
to fire: it is fine to do that, but then sometimes we call this
function while the CTL is up and has never been put down, but that
interrupt gets raised only when
Hi Oliver,
On Fri, Jan 8, 2021 at 7:24 PM Oliver Graute wrote:
>
> On 19/12/20, Oliver Graute wrote:
> > Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD
> > to panel-simple.
> >
> > The panel spec from Variscite can be found at:
> > https://www.variscite.com/wp-content/uploads/
Hi, Matthias:
Chun-Kuang Hu 於 2020年12月3日 週四 上午7:59寫道：
>
> rx_callback is a standard mailbox callback mechanism and could
> cover the function of proprietary cmdq_task_cb, so it is better
> to use the standard one instead of the proprietary one. But
> register rx_callback should before mbox_reques
With modifiers one can actually have different format_info structs
for the same format, which now matters for AMDGPU since we convert
implicit modifiers to explicit modifiers with multiple planes.
I checked other drivers and it doesn't look like they end up triggering
this case so I think this is
40 matches
Mail list logo
