Adhere to kernel coding style.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Christian König
Acked-by: Alex Deucher
Acked-by: Sam Ravnborg
Cc: Alex Deucher
Cc: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --
Using struct drm_device.pdev is deprecated. Convert hibmc to struct
drm_device.dev. No functional changes.
v3:
* rebased
Signed-off-by: Thomas Zimmermann
Reviewed-by: Tian Tao
Acked-by: Sam Ravnborg
Cc: Xinliang Liu
Cc: Tian Tao
Cc: John Stultz
Cc: Xinwei Kong
Cc: Chen Feng
---
Using struct drm_device.pdev is deprecated. Convert amdgpu to struct
drm_device.dev. No functional changes.
v3:
* rebased
Signed-off-by: Thomas Zimmermann
Acked-by: Christian König
Acked-by: Alex Deucher
Acked-by: Sam Ravnborg
Cc: Alex Deucher
Cc: Christian König
---
drivers/gpu/dr
I merged many of the patches that were ready in v2 into drm-misc-next. In
v3 remain only patches that need an r-b/a-b (i915/gt/gvt) or required
a change from v2.
The pdev field in struct drm_device points to a PCI device structure and
goes back to UMS-only days when all DRM drivers were for PCI de
Using struct drm_device.pdev is deprecated. Convert nouveau to struct
drm_device.dev. No functional changes.
v3:
* fix nv04_dfp_update_backlight() as well (Jeremy)
Signed-off-by: Thomas Zimmermann
Reviewed-by: Jeremy Cline
Cc: Ben Skeggs
---
drivers/gpu/drm/nouveau/dispnv04/arb.c
Using struct drm_device.pdev is deprecated. Convert i915 to struct
drm_device.dev. No functional changes.
v3:
* rebased
v2:
* move gt/ and gvt/ changes into separate patches
Signed-off-by: Thomas Zimmermann
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/
Using struct drm_device.pdev is deprecated. Convert i915 to struct
drm_device.dev. No functional changes.
Signed-off-by: Thomas Zimmermann
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/gvt/cfg_space.c | 5 +++--
drivers/gpu/drm/i915/gvt/firmware.c | 10 +-
We have DRM drivers based on USB, SPI and platform devices. All of them
are fine with storing their device reference in struct drm_device.dev.
PCI devices should be no exception. Therefore struct drm_device.pdev is
deprecated.
Instead upcast from struct drm_device.dev with to_pci_dev(). PCI-specif
Using struct drm_device.pdev is deprecated. Convert i915 to struct
drm_device.dev. No functional changes.
Signed-off-by: Thomas Zimmermann
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 10
Hi!
Follow-up on the v5 [1], things have gotten significantly
better in the last 9 months, thanks to the efforts on Bifrost
support by the Collabora team (and probably others I'm not
aware of).
I've been testing this series on a MT8183/kukui device, with a
chromeos-5.10 kernel [2], and got basic
Define a compatible string for the Mali Bifrost GPU found in
Mediatek's MT8183 SoCs.
Signed-off-by: Nicolas Boichat
Reviewed-by: Alyssa Rosenzweig
---
Changes in v7:
- Fix GPU ID in commit message
Changes in v6:
- Rebased, actually tested with recent mesa driver.
- No change
Changes in v5:
GPUs with more than a single regulator (e.g. G72 on MT8183) will
require platform-specific handling, disable devfreq for now.
Signed-off-by: Nicolas Boichat
---
Changes in v7:
- Fix GPU ID in commit message
Changes in v6:
- New change
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 9
Add support for MT8183's G72 Bifrost.
Signed-off-by: Nicolas Boichat
---
Changes in v7:
- Fix GPU ID in commit message
Changes in v6:
- Context conflicts, reflow the code.
- Use ARRAY_SIZE for power domains too.
Changes in v5:
- Change power domain name from 2d to core2.
Changes in v4:
-
On 1/7/21 9:26 AM, Nicolas Boichat wrote:
GPUs with more than a single regulator (e.g. G72 on MT8183) will
require platform-specific handling, disable devfreq for now.
Signed-off-by: Nicolas Boichat
---
Changes in v7:
- Fix GPU ID in commit message
Changes in v6:
- New change
drivers/g
On Thu, Jan 7, 2021 at 4:31 PM Tomeu Vizoso wrote:
>
> On 1/7/21 9:26 AM, Nicolas Boichat wrote:
> > GPUs with more than a single regulator (e.g. G72 on MT8183) will
> > require platform-specific handling, disable devfreq for now.
> >
> > Signed-off-by: Nicolas Boichat
> > ---
> >
> > Changes in
On 1/7/21 9:49 AM, Nicolas Boichat wrote:
On Thu, Jan 7, 2021 at 4:31 PM Tomeu Vizoso wrote:
On 1/7/21 9:26 AM, Nicolas Boichat wrote:
GPUs with more than a single regulator (e.g. G72 on MT8183) will
require platform-specific handling, disable devfreq for now.
Signed-off-by: Nicolas Boichat
rdma fifo size may be different even in same SOC, add this
property to the corresponding rdma
Signed-off-by: Yongqiang Niu
---
.../devicetree/bindings/display/mediatek/mediatek,disp.txt | 9 +
1 file changed, 9 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/
On Wed, Dec 23, 2020 at 09:35:12PM +0100, Stefan Wahren wrote:
> From: Phil Elwell
>
> Both coherent_dma_mask and dma_mask act as constraints on allocations
> and bounce buffer usage, so be sure to set dma_mask to the appropriate
> value otherwise the effective mask could be incorrect.
>
> Signe
Use resource_size rather than a verbose computation on
the end and start fields.
Signed-off-by: Zheng Yongjun
---
drivers/video/fbdev/pxa3xx-gcu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fbdev/pxa3xx-gcu.c b/drivers/video/fbdev/pxa3xx-gcu.c
index 427
This series are based on 5.11-rc1 and provide 11 patch
to support mediatek SOC MT8183
Change since v8
- fix some review comment in v8
- separate gamma module for mt8183 has no dither function in gamma
- enable dither function for 5 or 6 bpc panel display
- separate ddp mutex patch from the whole S
1. add ovl private data
2. add rdma private data
3. add gamma privte data
4. add main and external path module for crtc create
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 1 +
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +
drivers/gpu/drm/mediatek
On Wed, Dec 23, 2020 at 08:24:33PM +0100, Stefan Wahren wrote:
> Adding the missing property power-domains to the bcm2835-vec schema to fix
> the following dtbs_check issue:
>
> vec@7e806000: 'power-domains' does not match any of the regexes: ...
>
> Signed-off-by: Stefan Wahren
Acked-by: Maxim
On 1/5/21 7:30 PM, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20210105:
on x86_64:
ld: drivers/gpu/drm/imx/dw_hdmi-imx.o: in function `dw_hdmi_imx_probe':
dw_hdmi-imx.c:(.text+0x29f): undefined reference to `of_drm_find_bridge'
Full randconfig file is attached.
--
~Randy
Reported-by
Some drivers have hardware capability to get the precise timestamp of
certain events based on which the fences are triggered. This allows it to
set accurate timestamp factoring out any software and IRQ latencies. Add
a timestamp variant of fence signal function, dma_fence_signal_timestamp
to allow
for 5 or 6 bpc panel, we need enable dither function
to improve the display quality
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 38 -
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_
Dne sreda, 06. januar 2021 ob 21:46:30 CET je Jernej Skrabec napisal(a):
> From: Roman Stratiienko
>
> To set blending channel order register software needs to know state and
> position of each channel, which impossible at plane commit stage.
>
> Move this procedure to atomic_flush stage, where
Dne sreda, 06. januar 2021 ob 20:27:59 CET je Giulio Benetti napisal(a):
> During commit "88bc4178568b8e0331143cc0616640ab72f0cba1" DRM_BUS_FLAG_*
Please use same commit referencing approach as for "Fixes" tag.
> macros have been changed to avoid ambiguity but just because of this
> ambiguity pre
property name must include only lowercase and '-'
Signed-off-by: Yongqiang Niu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5b782a4..
From: Giulio Benetti
During commit 88bc4178568b ("drm: Use new
DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") DRM_BUS_FLAG_*
macros have been changed to avoid ambiguity but just because of this
ambiguity previous DRM_BUS_FLAG_PIXDATA_(POS/NEG)EDGE were used meaning
_SAMPLE_ not _DRIVE_. This
On 2021-01-05 01:00, Konrad Dybcio wrote:
Using this code on A5xx (and probably older too) causes a
smmu bug.
Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system
cache(LLC)")
Signed-off-by: Konrad Dybcio
Tested-by: AngeloGioacchino Del Regno
---
Reviewed-by: Sai Prakash Ranj
From: Roman Stratiienko
To set blending channel order register software needs to know state and
position of each channel, which impossible at plane commit stage.
Move this procedure to atomic_flush stage, where all necessary information
is available.
Fixes: f88c5ee77496 ("drm/sun4i: Implement z
于 2021年1月6日 GMT+08:00 下午5:47:20, Jagan Teki 写到:
>On Sat, Nov 28, 2020 at 6:23 PM Icenowy Zheng wrote:
>>
>> Attaching the panel can fail, so cleanup work is necessary, otherwise
>> a pointer to freed struct drm_panel* will remain in drm_panel code.
>>
>> Do the cleanup if panel attaching failed
05.01.2021 06:47, Chanwoo Choi пишет:
> You might remove the 'devm_pm_opp_remove_all_dynamic(&pdev->dev)
> under ' remove_opp' goto statement.
Good catch, thank you.
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop
On 1/6/21 9:30 AM, Philipp Zabel wrote:
> The i.MX6 HDMI driver uses of_drm_find_bridge() and thus cannot be built
> with CONFIG_OF disabled:
>
> ld: drivers/gpu/drm/imx/dw_hdmi-imx.o: in function `dw_hdmi_imx_probe':
> dw_hdmi-imx.c:(.text+0x29f): undefined reference to `of_drm_find_bridg
From: Giulio Benetti
First patch is a tested by me fix, while the second need testing to
understand if it works correctly with any sunxi SoC with DE peripheral.
Already tested SoCs are:
- A20
- A33
Need testing:
- A10
- A10s
- A13
Giulio Benetti (2):
drm/sun4i: tcon: fix inverted DCLK polarit
mt8183 gamma is different with mt8173
remove mt8173 compatible name for mt8183 gamma
Signed-off-by: Yongqiang Niu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/med
This patch adds an initial DRM driver for the Loongson LS7A1000
bridge chip(LS7A). The LS7A bridge chip contains two display
controllers, support dual display output. The maximum support for
each channel display is to 1920x1080@60Hz.
At present, DC device detection and DRM driver registration are
c
not all SoC has dither function in gamma module
dd private data to control this function setting
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
On Wed, Dec 23, 2020 at 09:35:14PM +0100, Stefan Wahren wrote:
> This converts the v3d bindings to yaml format.
>
> Signed-off-by: Stefan Wahren
> ---
> .../devicetree/bindings/gpu/brcm,bcm-v3d.txt | 33 --
> .../devicetree/bindings/gpu/brcm,bcm-v3d.yaml | 76
> ++
mt8183 gamma module will different with mt8173
separate gamma for add private data
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 185
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |
On Wed, Dec 23, 2020 at 09:35:13PM +0100, Stefan Wahren wrote:
> From: Phil Elwell
>
> MMU exception conditions are reported in the V3D_MMU_CTRL register as
> write-1-to-clear (W1C) bits. The MMU interrupt handling code clears any
> exceptions, but does so by masking out any other bits and writin
On Wed, Dec 23, 2020 at 09:35:11PM +0100, Stefan Wahren wrote:
> From: Nicolas Saenz Julienne
>
> Aside from being more correct, the non optional version of the function
> prints an error when failing to find the IRQ.
>
> Signed-off-by: Nicolas Saenz Julienne
> Signed-off-by: Stefan Wahren
Ap
Add DDP support for MT8167 SoC.
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 48 ++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 1f99db6..1308046
This patch add RDMA fifo size error handle
rdma fifo size will not always bigger than the calculated threshold
if that case happened, we need set fifo size as the threshold
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4
1 file changed, 4 insertions(+)
diff -
From: Giulio Benetti
It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is
dedicated to invert DCLK polarity and this makes thing really easier than
before. So let's handle DCLK polarity by adding
SUN4I_TCON0_IO_POL_DCLK_POSITIVE as bit 26 and activating according to
bus_flags
Get the fifo size from device tree
because each rdma in the same SoC may have different fifo size
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rd
The explicit out-fences in crtc are signaled as part of vblank event,
indicating all framebuffers present on the Atomic Commit request are
scanned out on the screen. Though the fence signal and the vblank event
notification happens at the same time, triggered by the same hardware
vsync event, the t
add description for mt8183 display
Signed-off-by: Yongqiang Niu
Reviewed-by: Chun-Kuang Hu
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/displ
Hi!
Follow-up on the v5 [1], things have gotten significantly
better in the last 9 months, thanks to the efforts on Bifrost
support by the Collabora team (and probably others I'm not
aware of).
I've been testing this series on a MT8183/kukui device, with a
chromeos-5.10 kernel [2], and got basic
Define a compatible string for the Mali Bifrost GPU found in
Mediatek's MT8183 SoCs.
Signed-off-by: Nicolas Boichat
Reviewed-by: Alyssa Rosenzweig
---
(no changes since v6)
Changes in v6:
- Rebased, actually tested with recent mesa driver.
- No change
Changes in v5:
- Rename "2d" power dom
GPUs with more than a single regulator (e.g. G72 on MT8183) will
require platform-specific handling, disable devfreq for now.
Signed-off-by: Nicolas Boichat
Reviewed-by: Tomeu Vizoso
---
Changes in v8:
- Use DRM_DEV_INFO instead of ERROR
Changes in v7:
- Fix GPU ID in commit message
Changes
Add support for MT8183's G72 Bifrost.
Signed-off-by: Nicolas Boichat
Reviewed-by: Tomeu Vizoso
---
(no changes since v7)
Changes in v7:
- Fix GPU ID in commit message
Changes in v6:
- Context conflicts, reflow the code.
- Use ARRAY_SIZE for power domains too.
Changes in v5:
- Change powe
On Wed, Jan 06, 2021 at 05:27:21PM -0500, Alex Deucher wrote:
> Hi Dave, Daniel,
>
> New URL. FDO ran out of disk space, so I'm attempting to move to gitlab.
> Let me know if you run into any issues.
Worked fine. Did you puing linux-next to update your tree location? Also
legacy fd.o git seems b
On Tue, Jan 5, 2021 at 12:03 AM Rob Herring wrote:
> DT properties which can have multiple entries need to specify what the
> entries are and define how many entries there can be. In the case of
> only a single entry, just 'maxItems: 1' is sufficient.
>
> Add the missing entry constraints. These
On Wed, Jan 06, 2021 at 10:00:52PM -0500, Felix Kuehling wrote:
> This is the first version of our HMM based shared virtual memory manager
> for KFD. There are still a number of known issues that we're working through
> (see below). This will likely lead to some pretty significant changes in
> MMU
On Thu, Jan 07, 2021 at 09:50:28AM +0200, Jani Nikula wrote:
>
> Hi Dave & Daniel -
>
> Pretty quiet still, but here's some cc: stable fixes.
Pulled, thanks.
-Daniel
>
> (Well, one doesn't have the explicit stable tag, but the Fixes tag
> points at a commit in v3.9...)
>
> drm-intel-fixes-202
'--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Thomas-Zimmermann/drm-Move-struct-drm_device-pdev-to-legacy/20210107-161007
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-s02
'--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Thomas-Zimmermann/drm-Move-struct-drm_device-pdev-to-legacy/20210107-161007
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: microblaze-randconfig-r01
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:11寫道:
>
> rdma fifo size may be different even in same SOC, add this
> property to the corresponding rdma
Reviewed-by: Chun-Kuang Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 9
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:12寫道:
>
> property name must include only lowercase and '-'
Reviewed-by: Chun-Kuang Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
On Thu, Dec 17, 2020 at 11:12 AM Maarten Lankhorst
wrote:
>
> drm-misc-next-2020-12-17:
> drm-misc-next for v5.12:
>
> UAPI Changes:
> - Not necessarily one, but we document that userspace needs to force probe
> connectors.
>
> Cross-subsystem Changes:
> - Require FB_ATY_CT for aty on sparc64.
>
On Wed, Dec 23, 2020 at 10:14:58AM +0200, Jani Nikula wrote:
>
> Hi Maarten, Maxime, and Thomas -
>
> Here's the DP-HDMI2.1 PCON support topic pull consisting of the series
> [1]. The series is split roughly 50-50 between drm helpers and i915, so
> a topic branch seemed to be the right way to go.
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:12寫道:
>
> Get the fifo size from device tree
> because each rdma in the same SoC may have different fifo size
Reviewed-by: Chun-Kuang Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++-
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:11寫道:
>
> add description for mt8183 display
Applied to mediatek-drm-next [1], thanks.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu
>
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:12寫道:
>
> mt8183 gamma module will different with mt8173
> separate gamma for add private data
I've applied series "Decouple Mediatek DRM sub driver" [1] into
mediatek-drm-next [2] and this patch would conflict with
mediatek-drm-next, so please re
On Mon, Jan 04, 2021 at 06:10:31PM +0100, Philipp Zabel wrote:
> Hi Dave, Daniel,
>
> this PR includes the drmm encoder/plane/crtc allocation functions and
> converts the imx-drm driver to use them.
>
> The following changes since commit 5c8fe583cce542aa0b84adc939ce85293de36e5e:
>
> Linux 5.11
Hi Daniel
Am 11.12.20 um 10:50 schrieb Daniel Vetter:
[...]
+/**
+ * drm_gem_shmem_vmap_local - Create a virtual mapping for a shmem GEM object
+ * @shmem: shmem GEM object
+ * @map: Returns the kernel virtual address of the SHMEM GEM object's backing
+ * store.
+ *
+ * This function makes
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:12寫道:
>
> not all SoC has dither function in gamma module
> dd private data to control this function setting
'add' ?
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 12 +---
> 1 file changed, 9 inser
ce-pdev-to-legacy/20210107-161007
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-s021-20210107 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-208-g46a52ca4-dirty
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Philip Yang
Move the HMM get pages function from amdgpu_ttm and to amdgpu_mn. This
common function will be used by new svm APIs.
Signed-off-by: Philip Yang
Signed-off-by: Felix Kuehling
Acked-by: Christian König
---
drivers/gpu/drm/am
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Philip Yang
It will be used by kfd to map svm range to GPU, because svm range does
not have amdgpu_bo and bo_va, cannot use amdgpu_bo_update interface, use
amdgpu vm update interface directly.
Signed-off-by: Philip Yang
Signed-off-by: Felix K
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Alex Sierra
[why]
To support svm bo eviction mechanism.
[how]
If the BO crated has AMDGPU_AMDKFD_CREATE_SVM_BO flag set,
enable_signal callback will be called inside amdgpu_evict_flags.
This also causes gutting of the BO by removing all placem
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Philip Yang
Forgot to reserve a fence slot to use sdma to update page table, cause
below kernel BUG backtrace to handle vm retry fault while application is
exiting.
[ 133.048143] kernel BUG at
/home/yangp/git/compute_staging/kernel/drivers/d
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Philip Yang
If xnack is on, VM retry fault interrupt send to IH ring1, and ring1
will be full quickly. IH cannot receive other interrupts, this causes
deadlock if migrating buffer using sdma and waiting for sdma done while
handling retry fault.
Hi,
On 11/24/20 4:49 PM, Ville Syrjälä wrote:
> On Wed, Nov 18, 2020 at 01:40:58PM +0100, Hans de Goede wrote:
>> Commit 25b4620ee822 ("drm/i915/dsi: Skip delays for v3 VBTs in vid-mode")
>> added an intel_dsi_msleep() helper which skips sleeping if the
>> MIPI-sequences have a version of 3 or new
Add YCbCr encoding and quantization range parameters to
ipu_dp_setup_channel() and configure the CSC DP matrix
accordingly.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 9 ++---
drivers/gpu/ipu-v3/ipu-dp.c | 25 ++---
include/video/imx-ipu-v
Add COLOR_ENCODING and COLOR_RANGE plane properties and use them to
control the DP CSC matrix.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 44 +--
1 file changed, 30 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.
On Mon, Jan 04, 2021 at 01:10:18PM -0800, Rodrigo Vivi wrote:
> Hi Dave and Daniel,
>
> Happy New Year.
>
> Here goes the first pull request targeting 5.12.
>
> drm-intel-next-2021-01-04:
> - Display hotplug fix for gen2/gen3 (Chris)
> - Remove trailing semicolon (Tom)
> - Suppress display warni
Hi, Yongqiang:
Yongqiang Niu 於 2021年1月7日 週四 上午11:12寫道:
>
> Add DDP support for MT8167 SoC.
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 48
> ++
> 1 file changed, 48 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk
Hi Marek,
thanks for the patch. It works fine on stm32mp1 eval board with bridge
DSI & DPI panel.
Tested-by: Yannick Fertré
Best regards
On 12/24/20 7:19 AM, Marek Vasut wrote:
> The drm_display_mode_to_videomode() does not populate DISPLAY_FLAGS_DE_LOW
> or DISPLAY_FLAGS_PIXDATA_NEGEDGE flags
On Wed, Jan 06, 2021 at 12:13:12PM +0100, Maarten Lankhorst wrote:
> drm-misc-next-2021-01-06:
> drm-misc-next for v5.12:
>
> Core Changes:
> - Lots of drm documentation updates by Simor Ser.
Extra kudos for documentation work!
> - Require that each crtc has a unique primary plane.
> - Add fixme
Am 22.12.20 um 14:51 schrieb Daniel Vetter:
On Fri, Dec 18, 2020 at 06:55:38PM +0100, Christian König wrote:
Only initialize the DMA coherent pools if they are used.
Signed-off-by: Christian König
Ah, just realized the answer to my question on patch 2: The pools are
per-device, due to dma_all
Hi Marek,
thanks for the patch. It works fine on stm32mp1 eval board with bridge
DSI & DPI panel.
Tested-by: Yannick Fertré
Best regards
On 12/24/20 7:20 AM, Marek Vasut wrote:
> There is not much value in the extra conversion step, the calculations
> required for the LTDC IP are different tha
SoC will transmit the EoTp (End of Transmission packet) when
MIPI_DSI_MODE_EOT_PACKET flag is set.
Enabling EoTp will make the line time larger, so the hfp and
hbp should be reduced to keep line time.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 8 ++--
1 file changed,
On Wed, Dec 16, 2020 at 10:30 AM Greg Kroah-Hartman
wrote:
>
> On Wed, Dec 16, 2020 at 02:52:25PM +, Deucher, Alexander wrote:
> > [AMD Public Use]
> >
> > > -Original Message-
> > > From: Laurent Pinchart
> > > Sent: Tuesday, December 15, 2020 9:15 PM
> > > To: Koenig, Christian
> >
On Thu, Jan 7, 2021 at 11:28 AM Thomas Zimmermann wrote:
>
> Hi Daniel
>
> Am 11.12.20 um 10:50 schrieb Daniel Vetter:
> [...]
> >> +/**
> >> + * drm_gem_shmem_vmap_local - Create a virtual mapping for a shmem GEM
> >> object
> >> + * @shmem: shmem GEM object
> >> + * @map: Returns the kernel vir
On Thu, Jan 07, 2021 at 10:01:00AM -0500, Alex Deucher wrote:
> On Wed, Dec 16, 2020 at 10:30 AM Greg Kroah-Hartman
> wrote:
> >
> > On Wed, Dec 16, 2020 at 02:52:25PM +, Deucher, Alexander wrote:
> > > [AMD Public Use]
> > >
> > > > -Original Message-
> > > > From: Laurent Pinchart
>
On 05/01/2021 00:11, Nicolas Boichat wrote:
GPUs with more than a single regulator (e.g. G-57 on MT8183) will
require platform-specific handling, disable devfreq for now.
Can you explain what actually goes wrong here? AFAICT the existing code
does support controlling multiple regulators - but
On Thu, Jan 7, 2021 at 4:48 PM xuhuijie wrote:
> This commit 50145474f6ef(fbcon: remove soft scrollback code) remove soft
> scrollback in
> fbcon. So the shift+PageDown and shift+PageUp is missing. But PageUp is a
> vary important
> feature when system panic or reset. I can get log by PageUp bef
Am 2021-01-07 um 5:56 a.m. schrieb Christian König:
> Am 07.01.21 um 04:01 schrieb Felix Kuehling:
>> From: Alex Sierra
>>
>> [why]
>> To support svm bo eviction mechanism.
>>
>> [how]
>> If the BO crated has AMDGPU_AMDKFD_CREATE_SVM_BO flag set,
>> enable_signal callback will be called inside a
On Tue, Jan 05, 2021 at 04:04:16PM -0500, Andrey Grodzovsky wrote:
>
> On 11/23/20 3:01 AM, Christian König wrote:
> > Am 23.11.20 um 05:54 schrieb Andrey Grodzovsky:
> > >
> > > On 11/21/20 9:15 AM, Christian König wrote:
> > > > Am 21.11.20 um 06:21 schrieb Andrey Grodzovsky:
> > > > > Will be
Am 2021-01-07 um 4:23 a.m. schrieb Daniel Vetter:
> On Wed, Jan 06, 2021 at 10:00:52PM -0500, Felix Kuehling wrote:
>> This is the first version of our HMM based shared virtual memory manager
>> for KFD. There are still a number of known issues that we're working through
>> (see below). This will l
On 1/7/21 11:21 AM, Daniel Vetter wrote:
On Tue, Jan 05, 2021 at 04:04:16PM -0500, Andrey Grodzovsky wrote:
On 11/23/20 3:01 AM, Christian König wrote:
Am 23.11.20 um 05:54 schrieb Andrey Grodzovsky:
On 11/21/20 9:15 AM, Christian König wrote:
Am 21.11.20 um 06:21 schrieb Andrey Grodzovsky:
Typo Correction bellow
On 1/7/21 11:26 AM, Andrey Grodzovsky wrote:
Or is the idea to save the struct page * pointer? That feels a bit like
over-optimizing stuff. Better to have a simple implementation first and
then tune it if (and only if) any part of it becomes a problem for normal
usage.
Am 07.01.21 um 17:16 schrieb Felix Kuehling:
Am 2021-01-07 um 5:56 a.m. schrieb Christian König:
Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Alex Sierra
[why]
To support svm bo eviction mechanism.
[how]
If the BO crated has AMDGPU_AMDKFD_CREATE_SVM_BO flag set,
enable_signal callback
On Thu, Jan 07, 2021 at 11:26:52AM -0500, Andrey Grodzovsky wrote:
>
> On 1/7/21 11:21 AM, Daniel Vetter wrote:
> > On Tue, Jan 05, 2021 at 04:04:16PM -0500, Andrey Grodzovsky wrote:
> > > On 11/23/20 3:01 AM, Christian König wrote:
> > > > Am 23.11.20 um 05:54 schrieb Andrey Grodzovsky:
> > > > >
On 1/7/21 11:30 AM, Daniel Vetter wrote:
On Thu, Jan 07, 2021 at 11:26:52AM -0500, Andrey Grodzovsky wrote:
On 1/7/21 11:21 AM, Daniel Vetter wrote:
On Tue, Jan 05, 2021 at 04:04:16PM -0500, Andrey Grodzovsky wrote:
On 11/23/20 3:01 AM, Christian König wrote:
Am 23.11.20 um 05:54 schrieb And
On Thu, Jan 07, 2021 at 01:49:45PM +0100, Christian König wrote:
> Am 22.12.20 um 14:51 schrieb Daniel Vetter:
> > On Fri, Dec 18, 2020 at 06:55:38PM +0100, Christian König wrote:
> > > Only initialize the DMA coherent pools if they are used.
> > >
> > > Signed-off-by: Christian König
> > Ah, jus
On Tue, Jan 05, 2021 at 07:41:52AM +0200, Laurent Pinchart wrote:
> Hi Dave and Daniel,
>
> The following changes since commit 5b2fc08c455bbf749489254a81baeffdf4c0a693:
>
> Merge tag 'amd-drm-fixes-5.11-2020-12-23' of
> git://people.freedesktop.org/~agd5f/linux into drm-next (2020-12-24 10:31:
Am 2021-01-07 um 11:28 a.m. schrieb Christian König:
> Am 07.01.21 um 17:16 schrieb Felix Kuehling:
>> Am 2021-01-07 um 5:56 a.m. schrieb Christian König:
>>
>>> Am 07.01.21 um 04:01 schrieb Felix Kuehling:
From: Alex Sierra
[why]
To support svm bo eviction mechanism.
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