The AMD DRM drivers uAPI headers are licensed under the MIT license,
and carry copies of the license with slight variations. Replace them
with SPDX headers.
Signed-off-by: Laurent Pinchart
---
include/uapi/drm/amdgpu_drm.h | 19 +--
include/uapi/drm/r128_drm.h | 20 +---
The Intel DRM drivers uAPI headers are licensed under the MIT license,
and carry copies of the license with slight variations. Replace them
with SPDX headers.
Signed-off-by: Laurent Pinchart
---
include/uapi/drm/i915_drm.h | 22 +-
include/uapi/drm/vgem_drm.h | 22 +--
The Nvidia Tegra DRM driver uAPI header is licensed under the MIT
license, and carries a copy of the license with slight variations.
Replace it with an SPDX header.
Signed-off-by: Laurent Pinchart
---
include/uapi/drm/tegra_drm.h | 19 +--
1 file changed, 1 insertion(+), 18 delet
The Broadcom DRM drivers uAPI headers are licensed under the MIT
license, and carry copies of the license with slight variations. Replace
them with SPDX headers.
Signed-off-by: Laurent Pinchart
---
include/uapi/drm/v3d_drm.h | 20 +---
include/uapi/drm/vc4_drm.h | 20 +---
The VMware DRM driver uAPI header is licensed under the MIT license, and
carries a copy of the license with slight variations. Replace it with an
SPDX header.
Signed-off-by: Laurent Pinchart
Reviewed-by: Roland Scheidegger
---
include/uapi/drm/vmwgfx_drm.h | 21 +
1 file cha
The DRM drivers uAPI headers are licensed under the MIT license, and
carry copies of the license with slight variations. Replace them with
SPDX headers for headers copyrighted by Red Hat.
Signed-off-by: Laurent Pinchart
---
include/uapi/drm/msm_drm.h | 20 +---
include/uapi/d
Several DRM drivers uAPI headers that are licensed under the GPL carry
both an SPDX header and a copy of the license text. Drop the latter.
Signed-off-by: Laurent Pinchart
Reviewed-by: Daniel Vetter
---
include/uapi/drm/armada_drm.h | 4
include/uapi/drm/etnaviv_drm.h | 12
The legacy DRM drivers uAPI headers are licensed under the MIT license,
and carry copies of the license with slight variations. Replace them
with SPDX headers.
Signed-off-by: Laurent Pinchart
---
include/uapi/drm/mga_drm.h| 20 +---
include/uapi/drm/savage_drm.h | 20 +---
The Nouveau DRM driver uAPI header is licensed under the MIT license,
and carries a copy of the license with slight variations. Replace it
with an SPDX header.
Signed-off-by: Laurent Pinchart
---
include/uapi/drm/nouveau_drm.h | 20 +---
1 file changed, 1 insertion(+), 19 deletio
On Wed, Mar 13, 2019 at 02:00:28AM +0200, Laurent Pinchart wrote:
> On Thu, Feb 21, 2019 at 12:39:24PM +0200, Laurent Pinchart wrote:
> > Forgot to CC Rob, sorry about that.
>
> Rob, could you take this in your tree ?
Gentle ping.
> > On Thu, Feb 21, 2019 at 12:32:08PM +0200, Laurent Pinchart wr
This patch series attempts to add support for a DP-HDMI2.1 Protocol
Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata
E5 to DisplayPort_v2.0:
https://vesa.org/join-vesamemberships/member-downloads/?action=stamp&fileid=42299
The details are mentioned in:
VESA DP-to-HDMI PCON Speci
From: Swati Sharma
The HDMI2.1 extends HFVSDB (HDMI Forum Vendor Specific
Data block) to have fields related to newly defined methods of FRL
(Fixed Rate Link) levels, number of lanes supported, DSC Color bit
depth, VRR min/max, FVA (Fast Vactive), ALLM etc.
This patch adds the new HFVSDB fields
From: Swati Sharma
This patch parses MAX_FRL field to get the MAX rate in Gbps that
the HDMI 2.1 panel can support in FRL mode. Source need this
field to determine the optimal rate between the source and sink
during FRL training.
v2: Fixed minor bugs, and removed extra wrapper function (Uma Shan
This patch parses HFVSDB fields for DSC1.2 capabilities of an
HDMI2.1 sink. These fields are required by a source to understand the
DSC capability of the sink, to set appropriate PPS parameters,
before transmitting compressed data stream.
v2: Addressed following issues as suggested by Uma Shankar:
This patch adds support for configuring a PCON device,
connected as a DP branched device to enable FRL Link training
with a HDMI2.1 + sink.
v2: Fixed typos and addressed other review comments from Uma Shankar.
-changed the commit message for better clarity (Uma Shankar)
-removed unnecessary argume
From: Swati Sharma
There are specific DPCDs defined for detecting link failures between
the PCON and HDMI sink and check the link status. In case of link
failure, PCON will communicate the same using an IRQ_HPD to source.
HDMI sink would have indicated the same to PCON using SCDC interrupt
mechan
DP Specification for DP2.0 to HDMI2.1 Pcon specifies support for conversion
of colorspace from RGB to YCbCr.
https://groups.vesa.org/wg/DP/document/previewpdf/15651
This patch adds the relavant registers and helper functions to
get the capability and set the color conversion bits for rgb->ycbcr
co
This patch adds registers for getting DSC encoder capability for
a HDMI2.1 PCon. It also addes helper functions to configure
DSC between the PCON and HDMI2.1 sink.
v2: Corrected offset for DSC encoder bpc and minor changes.
Also added helper functions for getting pcon dsc encoder capabilities
as s
This patch adds functions to start FRL training for an HDMI2.1 sink,
connected via a PCON as a DP branch device.
This patch also adds a new structure for storing frl training related
data, when FRL training is completed.
v2: As suggested by Uma Shankar:
-renamed couple of variables for better clar
HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON.
This patch captures this in dfp cap structure in intel_dp and uses
this to prune connector modes that cannot be supported by the PCON
and FRL bandwidth.
v2: Addressed review comments from Uma Shankar:
-tweaked the comparison of targ
From: Swati Sharma
In this patch enables support for detecting link failures between
PCON and HDMI sink in i915 driver. HDMI link loss indication to
upstream DP source is indicated via IRQ_HPD. This is followed by
reading of HDMI link configuration status (HDMI_TX_LINK_ACTIVE_STATUS).
If the PCON
This patch calls functions to check FRL training requirements
for an HDMI2.1 sink, when connected through PCON.
The call is made before the DP link training. In case FRL is not
required or failure during FRL training, the TMDS mode is selected
for the pcon.
v2: moved check_frl_training() just afte
This patch adds support to read and store the DSC capabilities of the
HDMI2.1 PCon encoder. It also adds a new field to store these caps,
The caps are read during dfp update and can later be used to get the
PPS parameters for PCON-HDMI2.1 sink pair. Which inturn will be used
to take a call to overr
If PCON has capability to convert RGB->YUV colorspace and also
to 444->420 downsampling then for any YUV420 only mode, we can
let the PCON do all the conversion.
v2: As suggested by Uma Shankar, considered case for colorspace
BT709 and BT2020, and default to BT609. Also appended dir
'display' in c
When a source supporting DSC1.1 is connected to DSC1.2 HDMI2.1 sink
via DP HDMI2.1 PCON, the PCON can be configured to decode the
DSC1.1 compressed stream and encode to DSC1.2. It then sends the
DSC1.2 compressed stream to the HDMI2.1 sink.
This patch configures the PCON for DSC1.1 to DSC1.2 encod
The DP-HDMI2.1 PCON spec provides way for a source to set PPS
parameters: slice height, slice width and bits_per_pixel, based on
the HDMI2.1 sink capabilities. The DSC encoder of the PCON will
respect these parameters, while preparing the 128 byte PPS.
This patch adds helper functions to calculate
On Wed, Dec 16, 2020 at 09:06:50AM +0800, Philip Li wrote:
> On Mon, Dec 14, 2020 at 09:49:17PM +0300, Dan Carpenter wrote:
> > On Sat, Dec 12, 2020 at 04:54:45PM +0800, Philip Li wrote:
> > > On Fri, Dec 11, 2020 at 04:42:00PM +0200, Ville Syrjälä wrote:
> > > > On Fri, Dec 11, 2020 at 01:24:49PM
Am 16.12.20 um 06:41 schrieb Chen Li:
When using e8860(gcn1) on arm64, the kernel crashed on drm/radeon:
[ 11.240414] pc : __memset+0x4c/0x188
[ 11.244101] lr : radeon_uvd_get_create_msg+0x114/0x1d0 [radeon]
[ 11.249995] sp : 0d7eb700
[ 11.253295] x29: 0d7eb700 x28: 8
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