Am 10.12.20 um 23:41 schrieb Hridya Valsaraju:
Thanks again for the reviews!
On Thu, Dec 10, 2020 at 3:03 AM Christian König
wrote:
Am 10.12.20 um 11:56 schrieb Greg KH:
On Thu, Dec 10, 2020 at 11:27:27AM +0100, Daniel Vetter wrote:
On Thu, Dec 10, 2020 at 11:10:45AM +0100, Greg KH wrote:
O
Driver code has no business with the internals of the irq descriptor.
Aside of that the count is per interrupt line and therefore takes
interrupts from other devices into account which share the interrupt line
and are not handled by the graphics driver.
Replace it with a pmu private count which o
On 05.10.20 15:42, Marek Vasut wrote:
The value programmed into horizontal porch and sync registers must be
scaled to the correct number of DSI lanes and bpp, make it so.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Guido Günther
Cc: Jaehoon Chung
Cc: Lucas Stach
Cc: Marek Szyprowski
C
There is absolutely no reason to mimic the x86 deferred affinity
setting. This mechanism is required to handle the hardware induced issues
of IO/APIC and MSI and is not in use when the interrupts are remapped.
XEN does not need this and can simply change the affinity from the calling
context. The
'phys_addr' is of type 'dma_addr_t'.
Use '%pad' instead of '%x' to print this variable in an error message.
Signed-off-by: Christophe JAILLET
---
drivers/video/fbdev/ep93xx-fb.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/video/fbdev/ep93xx-fb.c b/drivers/vid
The irq descriptor is already there, no need to look it up again.
Signed-off-by: Thomas Gleixner
Cc: Christian Borntraeger
Cc: Heiko Carstens
Cc: linux-s...@vger.kernel.org
---
arch/s390/kernel/irq.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/s390/kernel/irq.c
+++ b/a
On 12/10/20 7:40 PM, Rob Clark wrote:
> From: Rob Clark
>
> [ 192.062000] [ cut here ]
> [ 192.062498] WARNING: CPU: 3 PID: 2039 at
drivers/gpu/drm/msm/msm_gem.c:381 put_iova_vmas+0x94/0xa0 [msm]
> [ 192.062870] Modules linked in: snd_hrtimer snd_seq snd_seq_device
r
On 12/10/2020 5:46 AM, Maxime Ripard wrote:
> The BSC controllers used for the HDMI DDC have an interrupt controller
> shared between both instances. Let's add it to avoid polling.
>
> Signed-off-by: Maxime Ripard
Reviewed-by: Florian Fainelli
--
Florian
Provide an accessor to the effective interrupt affinity mask. Going to be
used to replace open coded fiddling with the irq descriptor.
Signed-off-by: Thomas Gleixner
---
include/linux/irq.h |7 +++
1 file changed, 7 insertions(+)
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -9
On Thu, Dec 10 2020 at 17:09, Tvrtko Ursulin wrote:
> On 10/12/2020 16:35, Thomas Gleixner wrote:
>> I'll send out a series addressing irq_to_desc() (ab)use all over the
>> place shortly. i915 is in there...
>
> Yep we don't need atomic, my bad. And we would care about the shared
> interrupt line.
Going through a full irq descriptor lookup instead of just using the proper
helper function which provides direct access is suboptimal.
In fact it _is_ wrong because the chip callback needs to get the chip data
which is relevant for the chip while using the irq descriptor variant
returns the irq c
Hi,
This series adds i.MX8qxp LVDS PHY mode support for the Mixel PHY in the
Freescale i.MX8qxp SoC.
The Mixel PHY is MIPI DPHY + LVDS PHY combo, which can works in either
MIPI DPHY mode or LVDS PHY mode. The PHY mode is controlled by i.MX8qxp
SCU firmware. The PHY driver would call a SCU funct
The Northwest Logic MIPI DSI host controller embedded in i.MX8qxp
works with a Mixel MIPI DPHY + LVDS PHY combo to support either
a MIPI DSI display or a LVDS display. So, this patch calls
phy_set_mode() from nwl_dsi_enable() to set PHY mode to MIPI DPHY
explicitly.
Cc: Guido Günther
Cc: Robert
Use the proper core function.
Signed-off-by: Thomas Gleixner
Cc: Jon Mason
Cc: Dave Jiang
Cc: Allen Hubbe
Cc: linux-...@googlegroups.com
---
drivers/ntb/msi.c |4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
--- a/drivers/ntb/msi.c
+++ b/drivers/ntb/msi.c
@@ -282,15 +282,13 @@ int
From: Markus Elfring
Date: Thu, 10 Dec 2020 17:00:13 +0100
A local variable was used only within an if branch.
Thus move the definition for the variable “page” into the corresponding
code block.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
driver
On Thu, Dec 10 2020 at 18:20, boris ostrovsky wrote:
> On 12/10/20 2:26 PM, Thomas Gleixner wrote:
>> All event channel setups bind the interrupt on CPU0 or the target CPU for
>> percpu interrupts and overwrite the affinity mask with the corresponding
>> cpumask. That does not make sense.
>>
>> The
On Thu, Dec 10, 2020 at 08:25:48PM +0100, Thomas Gleixner wrote:
> The irq descriptor is already there, no need to look it up again.
>
> Signed-off-by: Thomas Gleixner
> Cc: Christian Borntraeger
> Cc: Heiko Carstens
> Cc: linux-s...@vger.kernel.org
> ---
> arch/s390/kernel/irq.c |2 +-
>
On Mon 23 Nov 04:46 CST 2020, Robert Foss wrote:
> 4k requires two dsi pipes, so don't report MODE_OK when only a
> single pipe is configured. But rather report MODE_PANEL to
> signal that requirements of the panel are not being met.
>
> Reported-by: Peter Collingbourne
> Suggested-by: Peter Col
it's not necessary to assign a value of 0 to ret here, because if
the previous functions were executed correctly, ret would be 0.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/drm_drv.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index
add the CONFIG_PM_SLEEP to isolate the function of resume and suspend.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dr
Let the core code do the fiddling with irq_desc.
Signed-off-by: Thomas Gleixner
Cc: Linus Walleij
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-g...@vger.kernel.org
---
drivers/pinctrl/nomadik/pinctrl-nomadik.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/drivers/pinct
On Thu, 2020-12-10 at 23:50 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
>
> Yongqiang Niu 於 2020年12月10日 週四 下午5:08寫道：
> >
> > This patch add RDMA fifo size error handle
> > rdma fifo size will not always bigger than the calculated threshold
> > if that case happened, we need set fifo size as the
Use 'framebuffer_release()' instead of 'kfree()' to undo a
'framebuffer_alloc()' call, both in the error handling path of the probe
function and in remove function.
Signed-off-by: Christophe JAILLET
---
drivers/video/fbdev/ep93xx-fb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
di
irq_set_lockdep_class() is used from modules and requires irq_to_desc() to
be exported. Move it into the core code which lifts another requirement for
the export.
Signed-off-by: Thomas Gleixner
---
include/linux/irqdesc.h | 10 --
kernel/irq/irqdesc.c| 14 ++
2 files
Most users of kstat_irqs_cpu() have the irq descriptor already. No point in
calling into the core code and looking it up once more.
Use it in per_cpu_count_show() to start with.
Signed-off-by: Thomas Gleixner
---
include/linux/irqdesc.h |6 ++
kernel/irq/irqdesc.c|4 ++--
2 file
Using the interrupt affinity mask for checking locality is not really
working well on architectures which support effective affinity masks.
The affinity mask is either the system wide default or set by user space,
but the architecture can or even must reduce the mask to the effective set,
which me
On 2020-12-10 12:25 p.m., Thomas Gleixner wrote:
> Use the proper core function.
>
> Signed-off-by: Thomas Gleixner
> Cc: Jon Mason
> Cc: Dave Jiang
> Cc: Allen Hubbe
> Cc: linux-...@googlegroups.com
Looks good to me.
Reviewed-by: Logan Gunthorpe
> ---
> drivers/ntb/msi.c |4 +---
>
On 12/10/2020 5:46 AM, Maxime Ripard wrote:
> The BCM2711 uses a number of instances of the bcmstb-l2 controller in its
> display engine. Let's allow the driver to be enabled through KConfig.
>
> Signed-off-by: Maxime Ripard
Acked-by: Florian Fainelli
--
Florian
This function uses irq_to_desc() and is going to be used by modules to
replace the open coded irq_to_desc() (ab)usage. The final goal is to remove
the export of irq_to_desc() so driver cannot fiddle with it anymore.
Move it into the core code and fixup the usage sites to include the proper
header.
No more users outside the core code.
Signed-off-by: Thomas Gleixner
---
include/linux/kernel_stat.h |1 -
kernel/irq/irqdesc.c| 19 ++-
2 files changed, 6 insertions(+), 14 deletions(-)
--- a/include/linux/kernel_stat.h
+++ b/include/linux/kernel_stat.h
@@ -67,7 +6
A recent request to export kstat_irqs() pointed to a copy of the same in
the i915 code, which made me look for further usage of irq descriptors in
drivers.
The usage in drivers ranges from creative to broken in all colours.
irqdesc.h clearly says that this is core functionality and the fact C doe
Use flexible-array member introduced in C99 instead of zero-length
array. Most of zero-length array was already taken care in previous
patch [1]. Now modified few more cases which were not handled earlier.
[1]. https://patchwork.kernel.org/patch/11394197/
Signed-off-by: Tian Tao
---
drivers/gpu
On Thu, Dec 10 2020 at 10:45, Tvrtko Ursulin wrote:
> On 10/12/2020 07:53, Joonas Lahtinen wrote:
>> I think later in the thread there was a suggestion to replace this with
>> simple counter increment in IRQ handler.
>
> It was indeed unsafe until recent b00bccb3f0bb ("drm/i915/pmu: Handle
> PCI u
On 12/10/2020 5:46 AM, Maxime Ripard wrote:
> The CEC and hotplug interrupts go through an interrupt controller shared
> between the two HDMI controllers.
>
> Let's add that interrupt controller and the interrupts for both HDMI
> controllers
>
> Signed-off-by: Maxime Ripard
Reviewed-by: Flor
On Thu, Dec 10 2020 at 18:19, boris ostrovsky wrote:
> On 12/10/20 2:26 PM, Thomas Gleixner wrote:
>> -EXPORT_SYMBOL_GPL(bind_evtchn_to_irq_lateeoi);
>
> include/xen/events.h also needs to be updated (and in the next patch for
> xen_set_affinity_evtchn() as well).
Darn, I lost that.
_
No driver has any business with the internals of an interrupt
descriptor. Storing a pointer to it just to use yet another helper at the
actual usage site to retrieve the affinity mask is creative at best. Just
because C does not allow encapsulation does not mean that the kernel has no
limits.
Retr
i.MX8qxp SoC embeds a Mixel MIPI DPHY + LVDS PHY combo which supports
either a MIPI DSI display or a LVDS display. The PHY mode is controlled
by SCU firmware and the driver would call a SCU firmware function to
configure the PHY mode. The single LVDS PHY has 4 data lanes to support
a LVDS display
Going through a full irq descriptor lookup instead of just using the proper
helper function which provides direct access is suboptimal.
In fact it _is_ wrong because the chip callback needs to get the chip data
which is relevant for the chip while using the irq descriptor variant
returns the irq c
Using the interrupt affinity mask for checking locality is not really
working well on architectures which support effective affinity masks.
The affinity mask is either the system wide default or set by user space,
but the architecture can or even must reduce the mask to the effective set,
which me
This patch allows LVDS PHYs to be configured through
the generic functions and through a custom structure
added to the generic union.
The parameters added here are based on common LVDS PHY
implementation practices. The set of parameters
should cover all potential users.
Cc: Kishon Vijay Abraham
On Thu, 2020-12-10 at 23:40 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
>
> Yongqiang Niu 於 2020年12月10日 週四 下午5:22寫道：
> >
> > rdma fifo size may be different even in same SOC, add this
> > property to the corresponding rdma
> >
> > Signed-off-by: Yongqiang Niu
> > ---
> > .../bindings/display/m
The irq descriptor is already there, no need to look it up again.
Signed-off-by: Thomas Gleixner
Cc: "James E.J. Bottomley"
Cc: Helge Deller
Cc: afzal mohammed
Cc: linux-par...@vger.kernel.org
---
arch/parisc/kernel/irq.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/pa
The SMP variant works perfectly fine on UP as well.
Signed-off-by: Thomas Gleixner
Cc: "James E.J. Bottomley"
Cc: Helge Deller
Cc: afzal mohammed
Cc: linux-par...@vger.kernel.org
---
arch/parisc/kernel/irq.c |5 +
1 file changed, 1 insertion(+), 4 deletions(-)
--- a/arch/parisc/kerne
Nothing uses the result and nothing should ever use it in driver code.
Signed-off-by: Thomas Gleixner
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: David Airlie
Cc: Daniel Vetter
Cc: Pankaj Bharadiya
Cc: Chris Wilson
Cc: Wambui Karuga
Cc: intel-...@lists.freedesktop.org
Cc: dri
The irq descriptor is already there, no need to look it up again.
Signed-off-by: Thomas Gleixner
Cc: Mark Rutland
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Marc Zyngier
Cc: linux-arm-ker...@lists.infradead.org
---
arch/arm64/kernel/smp.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
To prepare for interrupt spreading reduce the storage size of
irq_info::spurious_cnt to u8 so the required flag for the spreading logic
will not increase the storage size.
Protect the usage site against overruns.
Signed-off-by: Thomas Gleixner
Cc: Boris Ostrovsky
Cc: Juergen Gross
Cc: Stefano
Hello linux-firmware maintainers,
The following changes since commit 7455a36066741a6e52fba65e04f6451b4cdfd9c4:
Merge branch 'guc_v49' of git://anongit.freedesktop.org/drm/drm-firmware into
main (2020-11-30 09:26:11 -0500)
are available in the Git repository at:
https://github.com/lumag/lin
The irq descriptor is already there, no need to look it up again.
Signed-off-by: Thomas Gleixner
Cc: Marc Zyngier
Cc: Russell King
Cc: linux-arm-ker...@lists.infradead.org
---
arch/arm/kernel/smp.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm/kernel/smp.c
+++ b/arch
All event channel setups bind the interrupt on CPU0 or the target CPU for
percpu interrupts and overwrite the affinity mask with the corresponding
cpumask. That does not make sense.
The XEN implementation of irqchip::irq_set_affinity() already picks a
single target CPU out of the affinity mask and
Signed-off-by: Thomas Gleixner
Cc: Boris Ostrovsky
Cc: Juergen Gross
Cc: Stefano Stabellini
Cc: xen-de...@lists.xenproject.org
---
drivers/xen/events/events_base.c |6 --
1 file changed, 6 deletions(-)
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -1
This function can only ever work when the event channels:
- are already established
- interrupts assigned to them
- the affinity has been set by user space already
because any newly set up event channel is forced to be bound to CPU0 and
the affinity mask of the interrupt is forced to contai
No more (ab)use in modules finally. Remove the export so there won't come
new ones.
Signed-off-by: Thomas Gleixner
---
kernel/irq/irqdesc.c |1 -
1 file changed, 1 deletion(-)
--- a/kernel/irq/irqdesc.c
+++ b/kernel/irq/irqdesc.c
@@ -352,7 +352,6 @@ struct irq_desc *irq_to_desc(unsigned in
Keep track of the assignments of event channels to CPUs and select the
online CPU with the least assigned channels in the affinity mask which is
handed to irq_chip::irq_set_affinity() from the core code.
Signed-off-by: Thomas Gleixner
Cc: Boris Ostrovsky
Cc: Juergen Gross
Cc: Stefano Stabellini
This patch converts the mixel,mipi-dsi-phy binding to
DT schema format using json-schema.
Comparing to the plain text version, the new binding adds
the 'assigned-clocks', 'assigned-clock-parents' and
'assigned-clock-rates' properites, otherwise 'make dtbs_check'
would complain that there are mis-m
No driver has any business with the internals of an interrupt
descriptor. Storing a pointer to it just to use yet another helper at the
actual usage site to retrieve the affinity mask is creative at best. Just
because C does not allow encapsulation does not mean that the kernel has no
limits.
Retr
Add support for Mixel MIPI DPHY + LVDS PHY combo IP
as found on Freescale i.MX8qxp SoC.
Cc: Guido Günther
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Cc: Rob Herring
Cc: NXP Linux Team
Signed-off-by: Liu Ying
---
v2->v3:
* No change.
v1->v2:
* Add the binding for i.MX8qxp Mixel combo PHY base
These checks are used by modules and prevent the removal of the export of
irq_to_desc(). Move the accessor into the core.
Signed-off-by: Thomas Gleixner
---
include/linux/irqdesc.h | 17 +
kernel/irq/manage.c | 17 +
2 files changed, 22 insertions(+), 12 d
Both the per cpu stats and the accumulated count are accessed lockless and
can be concurrently modified. That's intentional and the stats are a rough
estimate anyway. Annotate them with data_race().
Signed-off-by: Thomas Gleixner
---
kernel/irq/irqdesc.c |4 ++--
kernel/irq/proc.c|5
First of all drivers have absolutely no business to dig into the internals
of an irq descriptor. That's core code and subject to change. All of this
information is readily available to /proc/interrupts in a safe and race
free way.
Remove the inspection code which is a blatant violation of subsyste
On Thu, Dec 10, 2020 at 8:42 PM Thomas Gleixner wrote:
> First of all drivers have absolutely no business to dig into the internals
> of an irq descriptor. That's core code and subject to change. All of this
> information is readily available to /proc/interrupts in a safe and race
> free way.
>
>
[Bug][DP501]
If ASPEED P2A (PCI to AHB) bridge is disabled and disallowed for
CVE_2019_6260 item3, and then the monitor's EDID is unable read through
Parade DP501.
The reason is the DP501's FW is mapped to BMC addressing space rather
than Host addressing space.
The resolution is that using "pci_iom
On Friday, December 11th, 2020 at 3:17 AM, Tian Tao
wrote:
> it's not necessary to assign a value of 0 to ret here, because if
> the previous functions were executed correctly, ret would be 0.
>
> Signed-off-by: Tian Tao
Reviewed-by: Simon Ser
___
d
Am 11.12.20 um 08:50 schrieb Thomas Hellström (Intel):
Hi, Christian
Thanks for the reply.
On 12/10/20 11:53 AM, Christian König wrote:
Am 09.12.20 um 17:46 schrieb Thomas Hellström (Intel):
On 12/9/20 5:37 PM, Jason Gunthorpe wrote:
On Wed, Dec 09, 2020 at 05:36:16PM +0100, Thomas Hellström
On Thu, Dec 10, 2020 at 03:50:31PM +, Simon Ser wrote:
> If a primary or cursor plane is not compatible with a CRTC it's attached
> to via the legacy primary/cursor field, things will be broken for legacy
> user-space.
>
> Signed-off-by: Simon Ser
> Cc: Daniel Vetter
> Cc: Pekka Paalanen
Y
On Thu, Dec 10, 2020 at 03:50:35PM +, Simon Ser wrote:
> If a CRTC is missing a legacy primary plane pointer, a lot of things
> will be broken for user-space: fbdev stops working and the entire legacy
> uAPI stops working.
>
> Require all drivers to populate drm_crtc.primary to prevent these
>
On Wed, Dec 09, 2020 at 03:25:22PM +0100, Thomas Zimmermann wrote:
> The existing dma-buf calls dma_buf_vmap() and dma_buf_vunmap() are
> allowed to pin the buffer or acquire the buffer's reservation object
> lock.
>
> This is a problem for callers that only require a short-term mapping
> of the b
On 2020-12-11 at 12:49:35 +0530, Ramalingam C wrote:
> On 2020-12-10 at 11:56:39 +0530, Anshuman Gupta wrote:
> > Add support for HDCP 2.2 DP MST shim callback.
> > This adds existing DP HDCP shim callback for Link Authentication
> > and Encryption and HDCP 2.2 stream encryption
> > callback.
> >
On Wed, Dec 09, 2020 at 03:25:23PM +0100, Thomas Zimmermann wrote:
> This patch adds vmap_local and vunmap_local to struct drm_gem_object_funcs;
> including the PRIME helpers to connect with dma-buf's related interfaces.
>
> Besides the generic DRM core, this will become relevant for fbdev emulati
On 12/11/20 9:57 AM, Christian König wrote:
Am 11.12.20 um 08:50 schrieb Thomas Hellström (Intel):
Hi, Christian
Thanks for the reply.
On 12/10/20 11:53 AM, Christian König wrote:
Am 09.12.20 um 17:46 schrieb Thomas Hellström (Intel):
On 12/9/20 5:37 PM, Jason Gunthorpe wrote:
On Wed, Dec
On Wed, Dec 09, 2020 at 03:25:24PM +0100, Thomas Zimmermann wrote:
> Implementations of the vmap/vunmap GEM callbacks may perform pinning
> of the BO and may acquire the associated reservation object's lock.
> Callers that only require a mapping of the contained memory can thus
> interfere with oth
On Wed, Dec 09, 2020 at 03:25:25PM +0100, Thomas Zimmermann wrote:
> Implementations of the vmap/vunmap GEM callbacks may perform pinning
> of the BO and may acquire the associated reservation object's lock.
> Callers that only require a mapping of the contained memory can thus
> interfere with oth
On Thu, 10 Dec 2020, Ville Syrjälä wrote:
> On Thu, Dec 10, 2020 at 08:25:49PM +0100, Thomas Gleixner wrote:
>> Nothing uses the result and nothing should ever use it in driver code.
>>
>> Signed-off-by: Thomas Gleixner
>> Cc: Jani Nikula
>> Cc: Joonas Lahtinen
>> Cc: Rodrigo Vivi
>> Cc: Davi
On Thu, 10 Dec 2020, Thomas Gleixner wrote:
> Driver code has no business with the internals of the irq descriptor.
>
> Aside of that the count is per interrupt line and therefore takes
> interrupts from other devices into account which share the interrupt line
> and are not handled by the graphic
On Fri, 11 Dec 2020 09:56:07 +0530
Shashank Sharma wrote:
> Hello Simon,
>
> Hope you are doing well,
>
> I was helping out Aurabindo and the team with the design, so I have
> taken the liberty of adding some comments on behalf of the team,
> Inline.
>
> On 11/12/20 3:31 am, Simon Ser wrote:
>
On Wed, Dec 09, 2020 at 03:25:26PM +0100, Thomas Zimmermann wrote:
> Implementations of the vmap/vunmap GEM callbacks may perform pinning
> of the BO and may acquire the associated reservation object's lock.
> It's somewhat inconvenient to callers that simply require a mapping of
> the contained me
On Wed, Dec 09, 2020 at 03:25:27PM +0100, Thomas Zimmermann wrote:
> Fbdev emulation has to lock the BO into place while flushing the shadow
> buffer into the BO's memory. Remove any interference with pinning by
> using vmap_local functionality (instead of full vmap). This requires
> BO reservation
On Fri, Dec 11, 2020 at 10:40:00AM +0100, Daniel Vetter wrote:
> On Wed, Dec 09, 2020 at 03:25:24PM +0100, Thomas Zimmermann wrote:
> > Implementations of the vmap/vunmap GEM callbacks may perform pinning
> > of the BO and may acquire the associated reservation object's lock.
> > Callers that only
On Thu, 10 Dec 2020, Thomas Gleixner wrote:
> First of all drivers have absolutely no business to dig into the internals
> of an irq descriptor. That's core code and subject to change. All of this
> information is readily available to /proc/interrupts in a safe and race
> free way.
>
> Remove the
There is a copy and paste bug so it didn't return the correct error
code.
Fixes: b215212117f7 ("drm: panel: add Khadas TS050 panel driver")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/panel/panel-khadas-ts050.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/
Hi
Am 04.12.20 um 16:11 schrieb Maxime Ripard:
The HVS state now has both unassigned_channels that reflects the
channels that are not used in the associated state, and the in_use
boolean for each channel that says whether or not a particular channel
is in use.
Both express pretty much the same
On Fri, 2020-12-11 at 16:58 +0800, Zheng Yongjun wrote:
> Replace a comma between expression statements by a semicolon.
>
> Signed-off-by: Zheng Yongjun
> ---
> drivers/gpu/drm/imx/parallel-display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/imx/pa
On 10/12/2020 19:25, Thomas Gleixner wrote:
Driver code has no business with the internals of the irq descriptor.
Aside of that the count is per interrupt line and therefore takes
interrupts from other devices into account which share the interrupt line
and are not handled by the graphics driv
On Wed, Dec 09, 2020 at 03:25:20PM +0100, Thomas Zimmermann wrote:
> Vmapping the cursor source BO contains an implicit pin operation,
> so there's no need to do this manually.
>
> Signed-off-by: Thomas Zimmermann
Acked-by: Daniel Vetter
> ---
> drivers/gpu/drm/ast/ast_cursor.c | 10 +
Hi
Am 11.12.20 um 11:01 schrieb Daniel Vetter:
On Wed, Dec 09, 2020 at 03:25:27PM +0100, Thomas Zimmermann wrote:
Fbdev emulation has to lock the BO into place while flushing the shadow
buffer into the BO's memory. Remove any interference with pinning by
using vmap_local functionality (instead
On Wed, Dec 09, 2020 at 03:25:21PM +0100, Thomas Zimmermann wrote:
> The HW cursor's BO used to be mapped permanently into the kernel's
> address space. GEM's vmap operation will be protected by locks, and
> we don't want to lock the BO's for an indefinate period of time.
>
> Change the cursor cod
On 11.12.20 00:20, boris.ostrov...@oracle.com wrote:
On 12/10/20 2:26 PM, Thomas Gleixner wrote:
All event channel setups bind the interrupt on CPU0 or the target CPU for
percpu interrupts and overwrite the affinity mask with the corresponding
cpumask. That does not make sense.
The XEN impleme
Hi Laurent, Daniel,
On Thu, 2020-12-10 at 14:19 +0200, Laurent Pinchart wrote:
> Hi Daniel,
>
> On Wed, Dec 09, 2020 at 10:13:54PM +0100, Daniel Vetter wrote:
> > On Wed, Dec 09, 2020 at 10:10:47PM +0100, Daniel Vetter wrote:
> > > On Tue, Dec 08, 2020 at 04:59:16PM +0100, Philipp Zabel wrote:
>
Am 11.12.20 um 10:55 schrieb Pekka Paalanen:
On Fri, 11 Dec 2020 09:56:07 +0530
Shashank Sharma wrote:
Hello Simon,
Hope you are doing well,
I was helping out Aurabindo and the team with the design, so I have
taken the liberty of adding some comments on behalf of the team,
Inline.
On 11/12/
This is the same series as v1, but with a new patch appended. I've tried
coming up with a wording that isn't too confusing, while still accepting
configurations like amdgpu's.
Each patch changes the docs and the drm_mode_config_validate at the same
time, so that we can easily revert a patch if nee
The previous wording could be understood by user-space evelopers as "a
primary/cursor plane is only compatible with a single CRTC" [1].
Reword the planes description to make it clear the DRM-internal
drm_crtc.primary and drm_crtc.cursor planes are for legacy uAPI.
[1]: https://github.com/swaywm/w
If a primary or cursor plane is not compatible with a CRTC it's attached
to via the legacy primary/cursor field, things will be broken for legacy
user-space.
Signed-off-by: Simon Ser
Reviewed-by: Daniel Vetter
Cc: Pekka Paalanen
---
drivers/gpu/drm/drm_mode_config.c | 16
1 fi
If a CRTC is missing a legacy primary plane pointer, a lot of things
will be broken for user-space: fbdev stops working and the entire legacy
uAPI stops working.
Require all drivers to populate drm_crtc.primary to prevent these
issues. Warn if it's NULL.
Signed-off-by: Simon Ser
Reviewed-by: Dan
User-space expects to be able to pick a primary plane for each CRTC
exposed by the driver. Make sure this assumption holds in
drm_mode_config_validate.
Use the legacy drm_crtc.primary field to check this, because it's
simpler and we require drivers to set it anyways. Accumulate a set of
primary pl
Am 11.12.20 um 11:18 schrieb Daniel Vetter:
On Wed, Dec 09, 2020 at 03:25:21PM +0100, Thomas Zimmermann wrote:
The HW cursor's BO used to be mapped permanently into the kernel's
address space. GEM's vmap operation will be protected by locks, and
we don't want to lock the BO's for an indefinate
On 2020-12-11 at 12:49:35 +0530, Ramalingam C wrote:
> On 2020-12-10 at 11:56:39 +0530, Anshuman Gupta wrote:
> > Add support for HDCP 2.2 DP MST shim callback.
> > This adds existing DP HDCP shim callback for Link Authentication
> > and Encryption and HDCP 2.2 stream encryption
> > callback.
> >
Hi Dan,
I assume your nice tooling found this buggy.
Nice!
On Fri, Dec 11, 2020 at 01:05:50PM +0300, Dan Carpenter wrote:
> There is a copy and paste bug so it didn't return the correct error
> code.
>
> Fixes: b215212117f7 ("drm: panel: add Khadas TS050 panel driver")
> Signed-off-by: Dan Carpe
Hi Tomi,
Thank you for the patch.
On Fri, Dec 11, 2020 at 01:42:36PM +0200, Tomi Valkeinen wrote:
> To support legacy gamma ioctls the drivers need to set
> drm_crtc_funcs.gamma_set either to a custom implementation or to
> drm_atomic_helper_legacy_gamma_set. Most of the atomic drivers do the
> l
Hi Tomi,
Thank you for the patch.
On Fri, Dec 11, 2020 at 01:42:37PM +0200, Tomi Valkeinen wrote:
> The DRM core handles legacy gamma-set ioctl by setting GAMMA_LUT and
> clearing CTM and DEGAMMA_LUT.
>
> This works fine on HW where we have either:
>
> degamma -> ctm -> gamma -> out
>
> or
>
On 12/7/2020 4:12 PM, Akhil P Oommen wrote:
Some GPUs support different max frequencies depending on the platform.
To identify the correct variant, we should check the gpu speedbin
fuse value. Add support for this speedbin detection to a6xx family
along with the required fuse details for a618 gpu
On 12/7/2020 4:12 PM, Akhil P Oommen wrote:
Add support for gpu fuse to help identify the supported opps.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b
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