Re: [PATCH v2 1/2] drm: adi: axi-hdmi-tx: Add support for AXI HDMI TX IP core

Hi Bogdan, I love your patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master v5.10-rc1 next-20201026] [cannot apply to drm/drm-next] [If your patch is applied to

Re: [PATCH v5 10/10] drm/fb_helper: Support framebuffers in I/O memory

Hi Am 24.10.20 um 22:38 schrieb Sam Ravnborg: > Hi Thomas. > > On Tue, Oct 20, 2020 at 02:20:46PM +0200, Thomas Zimmermann wrote: >> At least sparc64 requires I/O-specific access to framebuffers. This >> patch updates the fbdev console accordingly. >> >> For drivers with direct access to the fram

[PATCH v6 41/52] memory: tegra124-emc: Use devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() helper which makes code a bit cleaner. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra124-emc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c ind

[PATCH v6 20/52] ARM: tegra: Correct EMC registers size in Tegra20 device-tree

The Tegra20 EMC registers size should be twice bigger. This patch fixes the size. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 72a4211a61

[PATCH v6 45/52] drm/tegra: dc: Extend debug stats with total number of events

It's useful to know the total number of underflow events and currently the debug stats are getting reset each time CRTC is being disabled. Let's account the overall number of events that doesn't get a reset. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- dr

[PATCH v6 24/52] ARM: tegra: Add nvidia, memory-controller phandle to Tegra20 EMC device-tree

Add nvidia,memory-controller to the Tegra20 External Memory Controller node. This allows to perform a direct lookup of the Memory Controller instead of walking up the whole tree. This puts Tegra20 device-tree on par with Tegra30+. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi

[PATCH v6 15/52] dt-bindings: tegra30-actmon: Document OPP and interconnect properties

Document EMC DFS OPP table and interconnect paths that will be used for scaling of system's memory bandwidth based on memory utilization statistics. Previously ACTMON was supposed to drive EMC clock rate directly, but now it should do it using interconnect framework in order to support shared volta

[PATCH v6 30/52] memory: tegra20-emc: Make driver modular

This patch adds modularization support to the Tegra20 EMC driver. Driver now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/tegra20-emc.c | 17 - 2 files changed, 13 insertions(+), 6

[PATCH v6 21/52] ARM: tegra: Add interconnect properties to Tegra20 device-tree

Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 26 +- 1 file changed, 25 insertions(+), 1

[PATCH v6 25/52] ARM: tegra: Add DVFS properties to Tegra20 EMC device-tree node

Add EMC OPP DVFS/DFS tables and emc-stats subdev that will be used for dynamic memory bandwidth scaling, while EMC itself will perform voltage scaling. Update board device-trees with optional EMC core supply and remove unsupported OPPs. Signed-off-by: Dmitry Osipenko --- .../boot/dts/tegra20-ace

[PATCH v6 19/52] dt-bindings: memory: tegra124: Add memory client IDs

Each memory client have a unique hardware ID, this patch adds these IDs. Signed-off-by: Dmitry Osipenko --- include/dt-bindings/memory/tegra124-mc.h | 68 1 file changed, 68 insertions(+) diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memor

[PATCH v6 29/52] memory: tegra-mc: Add interconnect framework

Now Memory Controller is a memory interconnection provider. This allows us to use interconnect API for tuning of memory configuration. This patch adds common ICC core and adds hooks which should be implemented by the SoC drivers. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Signed-off-by: Dm

[PATCH v6 44/52] drm/tegra: dc: Support memory bandwidth management

Display controller (DC) performs isochronous memory transfers, and thus, has a requirement for a minimum memory bandwidth that shall be fulfilled, otherwise framebuffer data can't be fetched fast enough and this results in a DC's data-FIFO underflow that follows by a visual corruption. The Memory

[PATCH v6 05/52] dt-bindings: memory: tegra20: mc: Document new interconnect property

Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra20-m

Re: [PATCH 1/1] video: fbdev: fix divide error in fbcon_switch

Thanks, adding stable. > On Oct 22, 2020, at 12:34 AM, Thomas Zimmermann wrote: > > Hi > > On 22.10.20 01:57, saeed.mirzamohamm...@oracle.com > wrote: >> From: Saeed Mirzamohammadi > > >> >> This patch fixes the

[PATCH v6 42/52] memory: tegra124: Support interconnect framework

Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig

[PATCH v6 35/52] memory: tegra: Add missing latency allowness entry for Page Table Cache

The PTC memory client misses the latency allowness entry and this patch adds it. This prevents erroneous clearing of MC_INTSTATUS 0x0 register during of the LA programming in tegra_mc_setup_latency_allowance() due to the missing entry. Note that this patch doesn't fix any known problems. Signed-o

[PATCH v6 02/52] soc/tegra: fuse: Export tegra_read_ram_code()

The tegra_read_ram_code() is used by EMC drivers and we're going to make these driver modular, hence this function needs to be exported. Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/fuse/tegra-apbmisc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/tegra/fuse/tegra-ap

[PATCH v6 36/52] memory: tegra: Add FIFO sizes to Tegra30 memory clients

The latency allowness is calculated based on buffering capabilities of memory clients. This patch adds FIFO sizes to the Tegra30 memory clients. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra30.c | 66 ++ 1 file changed, 66 insertions(+) diff --git

[PATCH v6 38/52] memory: tegra30-emc: Continue probing if timings are missing in device-tree

EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-o

[PATCH v6 33/52] memory: tegra20: Support interconnect framework

Now Internal and External Memory Controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 3 +- drivers/memory/tegr

[PATCH v6 09/52] dt-bindings: memory: tegra30: mc: Document new interconnect property

Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra30-m

[PATCH v6 28/52] memory: tegra: Add and use devm_tegra_get_memory_controller()

Multiple Tegra drivers need to retrieve Memory Controller and there is duplication of the retrieval code among the drivers. This patch removes the duplication and fixes put_device() which was missed in the duplicated code. EMC drivers now use new common devm_tegra_get_memory_controller() helper in

Re: [RESEND PATCH v5 2/2] drm/bridge: hx8837: add a Himax HX8837 display controller driver

Hello Sam, On Fri, Oct 16, 2020 at 10:07:34PM +0200, Sam Ravnborg wrote: > Hi Lubomir. > > On Sat, Sep 26, 2020 at 02:07:19AM +0200, Lubomir Rintel wrote: > > Himax HX8837 is used to drive the LCD panel on OLPC platforms. > > > > It controls the panel backlight and is able to refresh it when the

[PATCH v6 18/52] dt-bindings: memory: tegra30: Add memory client IDs

Each memory client have a unique hardware ID, this patch adds these IDs. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- include/dt-bindings/memory/tegra30-mc.h | 67 + 1 file changed, 67 insertions(+) diff --git a/include/dt-bindings/memory/tegra30-mc.h b/inc

[PATCH v2 1/2] drm: adi: axi-hdmi-tx: Add support for AXI HDMI TX IP core

From: Lars-Peter Clausen The AXI HDMI HDL driver is the driver for the HDL graphics core which is used on various FPGA designs. It's mostly used to interface with the ADV7511 bridge driver on some Zynq boards (e.g. ZC702 & ZedBoard). Link: https://wiki.analog.com/resources/tools-software/linux-

[PATCH v6 01/52] clk: tegra: Export Tegra20 EMC kernel symbols

We're going to modularize Tegra EMC drivers and some of the EMC clk driver symbols need to be exported, let's export them. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20-emc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20-emc.c b/drivers/

[PATCH v2 2/2] drm: dt-bindings: adi: axi-hdmi-tx: Add DT bindings for axi-hdmi-tx

Add YAML device tree bindings for Analog Devices Inc. AXI HDMI TX IP core DRM driver. Signed-off-by: Bogdan Togorean --- .../bindings/display/adi/adi,axi-hdmi-tx.yaml | 72 +++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/adi/adi

[PATCH v6 26/52] ARM: tegra: Add DVFS properties to Tegra30 EMC and ACTMON device-tree nodes

Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for dynamic memory bandwidth scaling based on memory utilization statistics. Update board device-trees with optional EMC core supply and remove unsupported OPPs. Note that ACTMON watches all memory interconnect paths, but we use

[PATCH v6 16/52] dt-bindings: host1x: Document new interconnect properties

Most of Host1x devices have at least one memory client. These clients are directly connected to the memory controller. The new interconnect properties represent the memory client's connection to the memory controller. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../display/tegra

[PATCH v6 07/52] dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator

The SoC core voltage can't be changed without taking into account the clock rate of External Memory Controller. Document OPP table that will be used for dynamic voltage frequency scaling, taking into account EMC voltage requirement. Document optional core voltage regulator, which is optional becaus

[PATCH v6 32/52] memory: tegra20-emc: Continue probing if timings are missing in device-tree

EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-o

[PATCH v6 06/52] dt-bindings: memory: tegra20: emc: Document new interconnect property

External Memory Controller is interconnected with memory controller and with external memory. Document new interconnect property which turns EMC into interconnect provider. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt |

[PATCH v6 14/52] dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator

Document new OPP table and voltage regulator properties which are needed for supporting dynamic voltage-frequency scaling of the memory controller. Some boards may have a fixed core voltage regulator, hence it's optional because frequency scaling still may be desired. Signed-off-by: Dmitry Osipenk

[PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property

Tegra20 External Memory Controller talks to DRAM chips and it needs to be reprogrammed when memory frequency changes. Tegra Memory Controller sits behind EMC and these controllers are tightly coupled. This patch adds the new phandle property which allows to properly express connection of EMC and MC

[PATCH v6 22/52] ARM: tegra: Add interconnect properties to Tegra30 device-tree

Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30.dtsi | 27 ++- 1 file changed, 26 insertions(+), 1

[PATCH v6 13/52] dt-bindings: memory: tegra124: emc: Document new interconnect property

External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns External Memory Controller into interconnect provider. Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 7 ++

[PATCH v6 48/52] PM / devfreq: tegra20: Relax Kconfig dependency

The Tegra EMC driver now could be compiled as a loadable kernel module. Currently devfreq driver depends on the EMC/MC drivers in Kconfig, and thus, devfreq is forced to be a kernel module if EMC is compiled as a module. This build dependency could be relaxed since devfreq driver checks MC/EMC pres

[PATCH v6 12/52] dt-bindings: memory: tegra124: mc: Document new interconnect property

Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra124-mc.yaml | 5 +

[PATCH v6 39/52] memory: tegra30: Support interconnect framework

Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. MC driver now supports tuning of memory arbitration latency, which needs to be done for ISO memory cli

[PATCH v6 46/52] opp: Put interconnect paths outside of opp_table_lock

This patch fixes lockup which happens when OPP table is released if interconnect provider uses OPP in the icc_provider->set() callback and bandwidth of the ICC path is set to 0 by the ICC core when path is released. The icc_put() doesn't need the opp_table_lock protection, hence let's move it outsi

[PATCH v6 27/52] ARM: tegra: Add DVFS properties to Tegra124 EMC and ACTMON device-tree nodes

Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for dynamic memory bandwidth scaling based on memory utilization statistics. Remove unsupported EMC OPPs from board device-trees. Note that ACTMON watches all memory interconnect paths, but we use a single CPU-READ interconnect p

[PATCH v6 03/52] dt-bindings: memory: tegra20: emc: Correct registers range in example

There is superfluous zero in the registers base address and registers size should be twice bigger. Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bind

[PATCH v6 10/52] dt-bindings: memory: tegra30: emc: Document new interconnect property

External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns External Memory Controller into interconnect provider. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,teg

[PATCH v6 37/52] memory: tegra30-emc: Make driver modular

This patch adds modularization support to the Tegra30 EMC driver. Driver now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/mc.c | 3 +++ drivers/memory/tegra/tegra30-emc.c | 17 ++

[PATCH v6 50/52] PM / devfreq: tegra30: Silence deferred probe error

Tegra EMC driver was turned into a regular kernel driver, meaning that it could be compiled as a loadable kernel module now. Hence EMC clock isn't guaranteed to be available and clk_get("emc") may return -EPROBE_DEFER. Let's silence the deferred probe error. Acked-by: Chanwoo Choi Signed-off-by:

[PATCH v6 43/52] memory: tegra: Remove superfluous error messages around platform_get_irq()

The platform_get_irq() prints error message telling that interrupt is missing, hence there is no need to duplicated that message in the drivers. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/mc.c | 4 +--- drivers/memory/tegra/tegra20-emc.c | 1 - drivers/memory/tegra/tegra30-

[PATCH v6 47/52] PM / devfreq: tegra20: Silence deferred probe error

Tegra EMC driver was turned into a regular kernel driver, meaning that it could be compiled as a loadable kernel module now. Hence EMC clock isn't guaranteed to be available and clk_get("emc") may return -EPROBE_DEFER. Let's silence the deferred probe error. Acked-by: Chanwoo Choi Signed-off-by:

RE: WARNING in dma_map_page_attrs

Hi Christoph, > From: Jakub Kicinski > Sent: Saturday, October 24, 2020 11:45 PM > > CC: rdma, looks like rdma from the stack trace > > On Fri, 23 Oct 2020 20:07:17 -0700 syzbot wrote: > > syzbot has found a reproducer for the following issue on: > > > > HEAD commit:3cb12d27 Merge tag 'net-

[PATCH v6 08/52] dt-bindings: memory: tegra20: emc: Document mfd-simple compatible and statistics sub-device

External Memory Controller can gather various hardware statistics that are intended to be used for debugging purposes and for dynamic frequency scaling of memory bus. Document the new mfd-simple compatible and EMC statistics sub-device. The subdev contains EMC DFS OPP table and interconnect paths

[PATCH v6 17/52] dt-bindings: memory: tegra20: Add memory client IDs

Each memory client have a unique hardware ID, this patch adds these IDs. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- include/dt-bindings/memory/tegra20-mc.h | 53 + 1 file changed, 53 insertions(+) diff --git a/include/dt-bindings/memory/tegra20-mc.h b/inc

[PATCH v6 31/52] memory: tegra20-emc: Use devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() helper which makes code a bit cleaner. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index

[PATCH v6 23/52] ARM: tegra: Add interconnect properties to Tegra124 device-tree

Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra124.dtsi | 25 + 1 file changed, 25 insertions(+) di

[PATCH v6 40/52] memory: tegra124-emc: Make driver modular

This patch adds modularization support to the Tegra124 EMC driver. Driver now can be compiled as a loadable kernel module. Note that EMC clock must be registered at clk-init time, otherwise PLLM will be disabled as unused clock at boot time if EMC driver is compiled as a module, hence this patch ad

[PATCH v6 34/52] memory: tegra20-emc: Don't parse emc-stats node

EMC device-tree node now contains new emc-stats sub-node which needs to be skipped when timing nodes are parsed by EMC driver, otherwise driver will try to parse the emc-stats as a timing node and will error out. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 14

[PATCH v6 52/52] PM / devfreq: tegra30: Separate configurations per-SoC generation

Previously we were using count-weight of the T124 for T30 in order to get EMC clock rate that was reasonable for T30. In fact the count-weight should be x2 times smaller on T30, but then devfreq was producing a bit too low EMC clock rate for ISO memory clients, like display controller for example.

[PATCH v6 51/52] PM / devfreq: tegra30: Support interconnect and OPPs from device-tree

This patch moves ACTMON driver away from generating OPP table by itself, transitioning it to use the table which comes from device-tree. This change breaks compatibility with older device-trees in order to bring support for the interconnect framework to the driver. This is a mandatory change which

[PATCH v6 11/52] dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator

Document new OPP table and voltage regulator properties which are needed for supporting dynamic voltage-frequency scaling of the memory controller. Some boards may have a fixed core voltage regulator, hence it's optional because frequency scaling still may be desired. Signed-off-by: Dmitry Osipenk

[PATCH v6 00/52] Introduce memory interconnect for NVIDIA Tegra SoCs

Hello, This series brings initial support for memory interconnect to Tegra20, Tegra30 and Tegra124 SoCs. For the starter only display controllers and devfreq devices are getting interconnect API support, others could be supported later on. The display controllers have the biggest demand for inter

[PATCH v6 49/52] PM / devfreq: tegra20: Convert to EMC_STAT driver, support interconnect and device-tree

External (EMC) and Internal Memory Controllers (IMC) have a nearly identical statistics gathering module. This patch switches driver to use EMC_STAT instead of IMC_STAT and adds device-tree support which brings ICC support and makes driver to use bandwidth OPPs defined in device-tree. The previous

Re: [PATCH 2/5] drm: Compile out legacy chunks from struct drm_device

Hi Am 23.10.20 um 14:28 schrieb Daniel Vetter: > This means some very few #ifdef in code, but it allows us to > enlist the compiler to make sure this stuff isn't used anymore. > > More important, only legacy drivers change drm_device (for the > legacy_dev_list shadow attach management), therefore

Re: [PATCH 4/5] drm: Allow const struct drm_driver

Hi Am 23.10.20 um 14:28 schrieb Daniel Vetter: > It's nice if a big function/ioctl table like this is const. Only > downside here is that we need a few more #ifdef to paper over the > differences when CONFIG_DRM_LEGACY is enabled. Maybe provides more > motivation to sunset that horror show :-) >

Re: [PATCH] dt-bindings: More whitespace clean-ups in schema files

On Fri, Oct 23, 2020 at 02:22:58PM -0500, Rob Herring wrote: > Clean-up incorrect indentation, extra spaces, and missing EOF newline in > schema files. Most of the clean-ups are for list indentation which > should always be 2 spaces more than the preceding keyword. > > Found with yamllint (now int

Re: [PATCH 5/5] drm/: Constify struct drm_driver

Hi Am 23.10.20 um 14:28 schrieb Daniel Vetter: > Only the following drivers aren't converted: > - amdgpu, because of the driver_feature mangling due to virt support > - nouveau, because DRIVER_ATOMIC uapi is still not the default on the > platforms where it's supported (i.e. again driver_feature

Re: [PATCH] drm: Don't create the IN_FORMATS blob when the driver does not provide .format_mod_supported()

On Sat, Oct 24, 2020 at 12:52 AM Ville Syrjälä wrote: > > On Fri, Oct 23, 2020 at 10:03:50PM +, Simon Ser wrote: > > On Friday, October 23, 2020 10:39 PM, Ville Syrjala > > wrote: > > > > > From: Ville Syrjälä ville.syrj...@linux.intel.com > > > > > > The code responsible for creating the IN

Re: [PATCH] Implement .format_mod_supported in mxsfb

On Sun, Oct 25, 2020 at 4:52 PM Guido Günther wrote: > > Hi Daniel, > On Sat, Oct 24, 2020 at 04:59:16PM +, Daniel Abrecht wrote: > > This will make sure applications which use the IN_FORMATS blob > > to figure out which modifiers they can use will pick up the > > linear modifier which is need

Re: [PATCH v3 19/20] drm/tegra: Implement new UAPI

On 10/22/20 7:20 AM, Dmitry Osipenko wrote: 20.10.2020 12:18, Mikko Perttunen пишет: I'm asking this question because right now there is only one potential client for this IOCTL, the VIC. If other clients aren't supposed to be a part of the DRM driver, like for example NVDEC which probably sho

Re: [PATCH 5/5] drm/: Constify struct drm_driver

On Mon, Oct 26, 2020 at 9:43 AM Thomas Zimmermann wrote: > > Hi > > Am 23.10.20 um 14:28 schrieb Daniel Vetter: > > Only the following drivers aren't converted: > > - amdgpu, because of the driver_feature mangling due to virt support > > - nouveau, because DRIVER_ATOMIC uapi is still not the defau

[radeon-alex:amd-staging-drm-next 744/765] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:2280 sienna_cichlid_dump_pptable() error: buffer overflow 'pptable->SkuReserved' 8 <= 8

tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next head: 1e5c252665ac026e977cd87fb8fcdb6f0bc0b759 commit: 62b1f5006728492c79182d960635d749d84f71ec [744/765] drm/amd/pm: update driver if file for sienna cichlid config: i386-randconfig-m031-20201022 (attached as .config) co

Re: [PATCH 2/5] drm: Compile out legacy chunks from struct drm_device

On Mon, Oct 26, 2020 at 9:37 AM Thomas Zimmermann wrote: > > Hi > > Am 23.10.20 um 14:28 schrieb Daniel Vetter: > > This means some very few #ifdef in code, but it allows us to > > enlist the compiler to make sure this stuff isn't used anymore. > > > > More important, only legacy drivers change dr

Re: [PATCH v4 23/23] drm/msm: Don't implicit-sync if only a single ring

On Fri, Oct 23, 2020 at 08:49:14PM -0700, Rob Clark wrote: > On Fri, Oct 23, 2020 at 11:20 AM Lucas Stach wrote: > > > > On Fr, 2020-10-23 at 09:51 -0700, Rob Clark wrote: > > > From: Rob Clark > > > > > > If there is only a single ring (no-preemption), everything is FIFO order > > > and there is

[PATCH resend] drm/v3d: Fix double free in v3d_submit_cl_ioctl()

Originally this error path used to leak "bin" but then we accidentally applied two separate commits to fix it and ended up with a double free. Signed-off-by: Dan Carpenter --- Resending a year later because it was confusing at the time who should apply this and it fell through the cracks. For so

Re: [PATCH] drm/v3d: Fix double free in v3d_submit_cl_ioctl()

On Fri, Oct 25, 2019 at 09:09:56AM +1100, Stephen Rothwell wrote: > Hi Dan, > > On Thu, 24 Oct 2019 23:53:06 +0300 Dan Carpenter > wrote: > > > > Originally this error path used to leak "bin" but then we accidentally > > applied two separate commits to fix it and ended up with a double free. > >

Re: [PATCH 05/13] drm/ttm: new TT backend allocation pool

Hi "Christian, I love your patch! Perhaps something to improve: [auto build test WARNING on drm-tip/drm-tip] [cannot apply to drm-exynos/exynos-drm-next drm-intel/for-linux-next tegra-drm/drm/tegra/for-next linus/master drm/drm-next v5.10-rc1 next-20201026] [If your patch is applied t

Re: [PATCH] Implement .format_mod_supported in mxsfb

On Mon, Oct 26, 2020 at 10:05:17AM +0100, Daniel Vetter wrote: > On Sun, Oct 25, 2020 at 4:52 PM Guido Günther wrote: > > > > Hi Daniel, > > On Sat, Oct 24, 2020 at 04:59:16PM +, Daniel Abrecht wrote: > > > This will make sure applications which use the IN_FORMATS blob > > > to figure out whic

[PATCH v4 09/15] media/videbuf1|2: Mark follow_pfn usage as unsafe

The media model assumes that buffers are all preallocated, so that when a media pipeline is running we never miss a deadline because the buffers aren't allocated or available. This means we cannot fix the v4l follow_pfn usage through mmu_notifier, without breaking how this all works. The only real

[PATCH v4 02/15] drm/exynos: Use FOLL_LONGTERM for g2d cmdlists

The exynos g2d interface is very unusual, but it looks like the userptr objects are persistent. Hence they need FOLL_LONGTERM. Signed-off-by: Daniel Vetter Cc: Jason Gunthorpe Cc: Inki Dae Cc: Joonyoung Shim Cc: Seung-Woo Kim Cc: Kyungmin Park Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: And

[PATCH v4 05/15] mm/frame-vector: Use FOLL_LONGTERM

This is used by media/videbuf2 for persistent dma mappings, not just for a single dma operation and then freed again, so needs FOLL_LONGTERM. Unfortunately current pup_locked doesn't support FOLL_LONGTERM due to locking issues. Rework the code to pull the pup path out from the mmap_sem critical se

[PATCH v4 11/15] PCI: Obey iomem restrictions for procfs mmap

There's three ways to access PCI BARs from userspace: /dev/mem, sysfs files, and the old proc interface. Two check against iomem_is_exclusive, proc never did. And with CONFIG_IO_STRICT_DEVMEM, this starts to matter, since we don't want random userspace having access to PCI BARs while a driver is lo

[PATCH v4 03/15] misc/habana: Stop using frame_vector helpers

All we need are a pages array, pin_user_pages_fast can give us that directly. Plus this avoids the entire raw pfn side of get_vaddr_frames. Reviewed-by: John Hubbard Signed-off-by: Daniel Vetter Cc: Jason Gunthorpe Cc: Andrew Morton Cc: John Hubbard Cc: Jérôme Glisse Cc: Jan Kara Cc: Dan Wi

[PATCH v4 00/15] follow_pfn and other iomap races

Hi all Round 3 of my patch series to clamp down a bunch of races and gaps around follow_pfn and other access to iomem mmaps. Previous version: v1: https://lore.kernel.org/dri-devel/20201007164426.1812530-1-daniel.vet...@ffwll.ch/ v2: https://lore.kernel.org/dri-devel/20201009075934.3509076-1-da

[PATCH v4 04/15] misc/habana: Use FOLL_LONGTERM for userptr

These are persistent, not just for the duration of a dma operation. Signed-off-by: Daniel Vetter Cc: Jason Gunthorpe Cc: Andrew Morton Cc: John Hubbard Cc: Jérôme Glisse Cc: Jan Kara Cc: Dan Williams Cc: linux...@kvack.org Cc: linux-arm-ker...@lists.infradead.org Cc: linux-samsung-...@vger.

[PATCH v4 01/15] drm/exynos: Stop using frame_vector helpers

All we need are a pages array, pin_user_pages_fast can give us that directly. Plus this avoids the entire raw pfn side of get_vaddr_frames. Reviewed-by: John Hubbard Signed-off-by: Daniel Vetter Cc: Jason Gunthorpe Cc: Inki Dae Cc: Joonyoung Shim Cc: Seung-Woo Kim Cc: Kyungmin Park Cc: Kukj

[PATCH v4 07/15] mm: Close race in generic_access_phys

Way back it was a reasonable assumptions that iomem mappings never change the pfn range they point at. But this has changed: - gpu drivers dynamically manage their memory nowadays, invalidating ptes with unmap_mapping_range when buffers get moved - contiguous dma allocations have moved from ded

[PATCH v4 06/15] media: videobuf2: Move frame_vector into media subsystem

It's the only user. This also garbage collects the CONFIG_FRAME_VECTOR symbol from all over the tree (well just one place, somehow omap media driver still had this in its Kconfig, despite not using it). Reviewed-by: John Hubbard Acked-by: Mauro Carvalho Chehab Signed-off-by: Daniel Vetter Cc: J

[PATCH v4 14/15] sysfs: Support zapping of binary attr mmaps

We want to be able to revoke pci mmaps so that the same access rules applies as for /dev/kmem. Revoke support for devmem was added in 3234ac664a87 ("/dev/mem: Revoke mappings when a driver claims the region"). The simplest way to achieve this is by having the same filp->f_mapping for all mappings,

[PATCH v4 08/15] mm: Add unsafe_follow_pfn

Way back it was a reasonable assumptions that iomem mappings never change the pfn range they point at. But this has changed: - gpu drivers dynamically manage their memory nowadays, invalidating ptes with unmap_mapping_range when buffers get moved - contiguous dma allocations have moved from dedic

[PATCH v4 10/15] vfio/type1: Mark follow_pfn as unsafe

The code seems to stuff these pfns into iommu pts (or something like that, I didn't follow), but there's no mmu_notifier to ensure that access is synchronized with pte updates. Hence mark these as unsafe. This means that with CONFIG_STRICT_FOLLOW_PFN, these will be rejected. Real fix is to wire u

[PATCH v4 12/15] /dev/mem: Only set filp->f_mapping

When we care about pagecache maintenance, we need to make sure that both f_mapping and i_mapping point at the right mapping. But for iomem mappings we only care about the virtual/pte side of things, so f_mapping is enough. Also setting inode->i_mapping was confusing me as a driver maintainer, sinc

[PATCH v4 13/15] resource: Move devmem revoke code to resource framework

We want all iomem mmaps to consistently revoke ptes when the kernel takes over and CONFIG_IO_STRICT_DEVMEM is enabled. This includes the pci bar mmaps available through procfs and sysfs, which currently do not revoke mappings. To prepare for this, move the code from the /dev/kmem driver to kernel/

[PATCH v4 15/15] PCI: Revoke mappings like devmem

Since 3234ac664a87 ("/dev/mem: Revoke mappings when a driver claims the region") /dev/kmem zaps ptes when the kernel requests exclusive acccess to an iomem region. And with CONFIG_IO_STRICT_DEVMEM, this is the default for all driver uses. Except there's two more ways to access PCI BARs: sysfs and

Re: [PATCH 13/65] drm/omapdrm: Annotate dma-fence critical section in commit path

On 23/10/2020 15:21, Daniel Vetter wrote: > Nothing special, just put the end right after hw_done(). Note that in > one path there's a wait for the flip/update to complete. But as far as > I understand from comments and code that's only relevant for modesets, > and skipped if there wasn't a modeset

Re: [PATCH] Implement .format_mod_supported in mxsfb

On Mon, Oct 26, 2020 at 12:52:07PM +0200, Ville Syrjälä wrote: > On Mon, Oct 26, 2020 at 10:05:17AM +0100, Daniel Vetter wrote: > > On Sun, Oct 25, 2020 at 4:52 PM Guido Günther wrote: > > > > > > Hi Daniel, > > > On Sat, Oct 24, 2020 at 04:59:16PM +, Daniel Abrecht wrote: > > > > This will ma

Re: drm/ttm: new TT backend allocation pool

Am 26.10.20 um 06:23 schrieb Dave Airlie: On Mon, 26 Oct 2020 at 01:41, Christian König wrote: This replaces the spaghetti code in the two existing page pools. First of all depending on the allocation size it is between 3 (1GiB) and 5 (1MiB) times faster than the old implementation. It makes

Re: drm/ttm: new TT backend allocation pool

On Mon, Oct 26, 2020 at 1:01 PM Christian König wrote: > > Am 26.10.20 um 06:23 schrieb Dave Airlie: > > On Mon, 26 Oct 2020 at 01:41, Christian König > > wrote: > >> This replaces the spaghetti code in the two existing page pools. > >> > >> First of all depending on the allocation size it is bet

[PATCH] drm/msm: Add missing stub definition

DRM_MSM fails to build with DRM_MSM_DP=n; add the missing stub. Signed-off-by: Robin Murphy --- drivers/gpu/drm/msm/msm_drv.h | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index b9dd8f8f4887..0b2686b060c7 100644 --- a/drive

Re: [PATCH v6 12/52] dt-bindings: memory: tegra124: mc: Document new interconnect property

On Mon, 26 Oct 2020 01:16:55 +0300, Dmitry Osipenko wrote: > Memory controller is interconnected with memory clients and with the > External Memory Controller. Document new interconnect property which > turns memory controller into interconnect provider. > > Signed-off-by: Dmitry Osipenko > --- >

Re: [PATCH v6 13/52] dt-bindings: memory: tegra124: emc: Document new interconnect property

On Mon, 26 Oct 2020 01:16:56 +0300, Dmitry Osipenko wrote: > External memory controller is interconnected with memory controller and > with external memory. Document new interconnect property which turns > External Memory Controller into interconnect provider. > > Signed-off-by: Dmitry Osipenko >

Re: [PATCH] i915: Add QUIRK_EDP_CHANNEL_EQ for Dell 7200 2-in-1

On Fri, Oct 23, 2020 at 8:48 AM Jason Andryuk wrote: > > We're seeing channel equalization "fail" consistently coming out of DPMS > on the eDP of a Dell Latitude 7200 2-in-1. When the display tries to > come out of DPMS, it briefly flashes on before going dark. This repeats > once per second, an

[PATCH] drm: deprecate DRM_FORMAT_MOD_NONE

DRM_FORMAT_MOD_NONE is in the list of vendors, which is pretty confusing. We already have DRM_FORMAT_MOD_VENDOR_NONE. Move it down in the list of format modifiers. DRM_FORMAT_MOD_NONE is an alias for DRM_FORMAT_MOD_LINEAR, however the name is confusing: NONE doesn't mean that the modifier is impli

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