Hi
Am 21.09.20 um 05:25 schrieb Tian Tao:
> Adding driver implementation to support i2c driver algorithms for
> bit-shift adapters, so hibmc will using the interface provided by
> drm to read edid.
>
> Signed-off-by: Tian Tao
> ---
> drivers/gpu/drm/hisilicon/hibmc/Makefile| 2 +-
> dr
Hi
Am 21.09.20 um 05:25 schrieb Tian Tao:
> Use drm_get_edid to get the resolution, if that fails, set it to
> a fixed resolution.
>
> Signed-off-by: Tian Tao
> ---
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 35
>
> 1 file changed, 29 insertions(+), 6 deletio
Hi
The code looks correcet, but I think this patch should be merged into
patch 2. Anyone who initializes the i2c adapter certainly wants it
cleaned up as well :)
Best regards
Thomas
Am 21.09.20 um 05:25 schrieb Tian Tao:
> Rewrite the desrtoy callback function to release resources.
>
> Signed-
Nothing in modules can use that.
Signed-off-by: Thomas Gleixner
---
mm/highmem.c |2 --
1 file changed, 2 deletions(-)
--- a/mm/highmem.c
+++ b/mm/highmem.c
@@ -108,8 +108,6 @@ static inline wait_queue_head_t *get_pkm
atomic_long_t _totalhigh_pages __read_mostly;
EXPORT_SYMBOL(_totalhigh_
patch #1 add a new file to implements i2c adapters, #2 read the
resolution from the edid, if that fails, set the resolution to fixed.
patch #3 update the destroy callback function to release the i2c adapters.
Tian Tao (3):
drm/hisilicon: Support i2c driver algorithms for bit-shift adapters
drm
Adding driver implementation to support i2c driver algorithms for
bit-shift adapters, so hibmc will using the interface provided by
drm to read edid.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/hisilicon/hibmc/Makefile| 2 +-
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h | 21 +-
On Sat, 19 Sep 2020 12:37:26 -0700 Rob Clark wrote:
> +/**
> + * drm_crtc_set_sched_mode:
> + * @dev: DRM device
> + * @mode: one of DRM_CLIENT_CAP_SCHED_x
> + *
> + * Set the scheduling mode for per-CRTC kthread workers. This controls
> + * whether nonblocking atomic commits will run with SCHED
Signed-off-by: Thomas Gleixner
Cc: Michael Ellerman
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: linuxppc-...@lists.ozlabs.org
---
Note: Completely untested
---
arch/powerpc/Kconfig |1
arch/powerpc/include/asm/highmem.h |6 ++-
arch/powerpc/mm/Makefile |
Signed-off-by: Thomas Gleixner
Cc: Chris Zankel
Cc: Max Filippov
Cc: linux-xte...@linux-xtensa.org
---
Note: Completely untested
---
arch/xtensa/Kconfig |1
arch/xtensa/include/asm/highmem.h |9 +++
arch/xtensa/mm/highmem.c | 44 +++-
On Sun, Sep 20 2020 at 10:23, Daniel Vetter wrote:
> On Sun, Sep 20, 2020 at 08:23:26AM +0200, Thomas Gleixner wrote:
>> On Sat, Sep 19 2020 at 12:37, Daniel Vetter wrote:
>> > On Sat, Sep 19, 2020 at 12:35 PM Daniel Vetter wrote:
>> >> I think it should be the case, but I want to double check: W
Convert X86 to the generic kmap atomic implementation.
Make the iomap_atomic() naming convention consistent while at it.
Signed-off-by: Thomas Gleixner
---
arch/x86/Kconfig |3 +-
arch/x86/include/asm/fixmap.h |1
arch/x86/include/asm/highmem.h | 12 ++--
arch/x86/
On Sat, Sep 19 2020 at 12:37, Daniel Vetter wrote:
> On Sat, Sep 19, 2020 at 12:35 PM Daniel Vetter wrote:
>> I think it should be the case, but I want to double check: Will
>> copy_*_user be allowed within a kmap_temporary section? This would
>> allow us to ditch an absolute pile of slowpaths.
>
Signed-off-by: Thomas Gleixner
Cc: Guo Ren
Cc: linux-c...@vger.kernel.org
---
Note: Completely untested
---
arch/csky/Kconfig |1
arch/csky/include/asm/highmem.h |4 +-
arch/csky/mm/highmem.c | 75
3 files changed, 5 inse
Signed-off-by: Thomas Gleixner
Cc: Michal Simek
---
Note: Completely untested
---
arch/microblaze/Kconfig |1
arch/microblaze/include/asm/highmem.h |6 ++
arch/microblaze/mm/Makefile |1
arch/microblaze/mm/highmem.c | 78 --
Sat, 19 Sep 2020 12:37:25 -0700 Rob Clark wrote:
>
> @@ -1797,6 +1797,7 @@ int drm_atomic_helper_commit(struct drm_device *dev,
>struct drm_atomic_state *state,
>bool nonblock)
> {
> + struct kthread_worker *worker = NULL;
> int
Adopt the map ordering to match the other architectures and the generic
code.
Signed-off-by: Thomas Gleixner
Cc: Vineet Gupta
Cc: linux-snps-...@lists.infradead.org
---
Note: Completely untested
---
arch/arc/Kconfig |1
arch/arc/include/asm/highmem.h |8 ++-
arch/arc/
Rewrite the desrtoy callback function to release resources.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
b/drivers/gpu/drm/hisilicon/hib
Signed-off-by: Thomas Gleixner
Cc: "David S. Miller"
Cc: sparcli...@vger.kernel.org
---
Note: Completely untested
---
arch/sparc/Kconfig |1
arch/sparc/include/asm/highmem.h |7 +-
arch/sparc/mm/Makefile |3 -
arch/sparc/mm/highmem.c | 115 -
On Sun, Sep 20 2020 at 08:41, Thomas Gleixner wrote:
> On Sat, Sep 19 2020 at 10:18, Linus Torvalds wrote:
>> Maybe I've missed something. Is it because the new interface still
>> does "pagefault_disable()" perhaps?
>>
>> But does it even need the pagefault_disable() at all? Yes, the
>> *atomic* o
Signed-off-by: Thomas Gleixner
---
include/linux/highmem.h | 65 ++--
mm/highmem.c| 28 +---
2 files changed, 28 insertions(+), 65 deletions(-)
--- a/include/linux/highmem.h
+++ b/include/linux/highmem.h
@@ -94,27 +94,6
Instead of storing the map per CPU provide and use per task storage. That
prepares for temporary kmaps which are preemptible.
The context switch code is preparatory and not yet in use because
kmap_atomic() runs with preemption disabled. Will be made usable in the
next step.
Signed-off-by: Thomas
On Sat, Sep 19, 2020 at 10:18:54AM -0700, Linus Torvalds wrote:
> On Sat, Sep 19, 2020 at 2:50 AM Thomas Gleixner wrote:
> >
> > this provides a preemptible variant of kmap_atomic & related
> > interfaces. This is achieved by:
>
> Ack. This looks really nice, even apart from the new capability.
>
Signed-off-by: Thomas Gleixner
Cc: Russell King
Cc: Arnd Bergmann
Cc: linux-arm-ker...@lists.infradead.org
---
Note: Completely untested
---
arch/arm/Kconfig |1
arch/arm/include/asm/highmem.h | 30 +++---
arch/arm/mm/Makefile |1
arch/arm/mm/highmem.c
Now that the kmap atomic index is stored in task struct provide a
preemptible variant. On context switch the maps of an outgoing task are
removed and the map of the incoming task are restored. That's obviously
slow, but highmem is slow anyway.
The kmap_temporary and iomap_temporary interfaces can
Signed-off-by: Thomas Gleixner
Cc: Thomas Bogendoerfer
Cc: linux-m...@vger.kernel.org
---
Note: Completely untested
---
arch/mips/Kconfig |1
arch/mips/include/asm/highmem.h |4 +-
arch/mips/mm/highmem.c | 77
arch/mips/m
The kmap_atomic* interfaces in all architectures are pretty much the same
except for post map operations (flush) and pre- and post unmap operations.
Provide a generic variant for that.
Signed-off-by: Thomas Gleixner
---
include/linux/highmem.h | 87 ---
mm/Kcon
The mapping code is odd and looks broken. See FIXME in the comment.
Signed-off-by: Thomas Gleixner
Cc: Nick Hu
Cc: Greentime Hu
Cc: Vincent Chen
---
Note: Completely untested
---
arch/nds32/Kconfig.cpu |1
arch/nds32/include/asm/highmem.h | 21 +
arch/nds32/mm
On Sat, Sep 19 2020 at 10:18, Linus Torvalds wrote:
> On Sat, Sep 19, 2020 at 2:50 AM Thomas Gleixner wrote:
>>
>> this provides a preemptible variant of kmap_atomic & related
>> interfaces. This is achieved by:
>
> Ack. This looks really nice, even apart from the new capability.
>
> The only thin
On 2020-09-11 13:57, Neil Armstrong wrote:
On 09/09/2020 21:02, Alex Dewar wrote:
kmemdup can be used instead of kmalloc+memcpy. Replace an occurrence of
this pattern.
Friendly ping?
Issue identified with Coccinelle.
Signed-off-by: Alex Dewar
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-ds
First of all, sorry for the horribly big Cc list!
Following up to the discussion in:
https://lore.kernel.org/r/20200914204209.256266...@linutronix.de
this provides a preemptible variant of kmap_atomic & related
interfaces. This is achieved by:
- Consolidating all kmap atomic implementations
On Sun, Sep 20 2020 at 09:57, Linus Torvalds wrote:
> On Sun, Sep 20, 2020 at 1:49 AM Thomas Gleixner wrote:
> Btw, looking at the stack code, Ithink your new implementation of it
> is a bit scary:
>
>static inline int kmap_atomic_idx_push(void)
>{
> - int idx = __this_cpu_inc_retu
Use drm_get_edid to get the resolution, if that fails, set it to
a fixed resolution.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 35
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_dr
Hi Steven, Rob,
Should I send a v3 with the commit log fixes ?
Neil
On 16/09/2020 17:01, Neil Armstrong wrote:
> The T820, G31 & G52 GPUs integrated by Amlogic in the respective GXM,
> G12A/SM1 & G12B
> SoCs needs a quirk in the PWR registers at the GPU reset time.
>
> This serie adds the nece
On Sat, 19 Sep 2020, Tian Tao wrote:
> Update kernel-doc line comments to fix warnings reported by make W=1.
It's really not a fix if it just turns the kernel-doc comments into
regular comments...
Please fix the warnings instead.
BR,
Jani.
>
> drivers/gpu/drm/drm_dp_helper.c:1036: warning: Fun
On 21/09/2020 01:42, Chun-Kuang Hu wrote:
For each client driver, its timeout handler need to dump hardware register
or its state machine information, so remove timeout handler in helper
function and let client driver implement its own timeout handler.
I don't see the implementation of a cl
On Fri, Sep 18, 2020 at 01:12:21PM -0400, Rodrigo Vivi wrote:
> On Fri, Sep 18, 2020 at 11:03:12AM -0400, Alex Deucher wrote:
> > On Fri, Sep 18, 2020 at 9:25 AM Daniel Vetter
> > wrote:
> > >
> > > Hi all,
> > >
> > > These are the leftovers of the leftovers of my initial drmm series to
> > > ma
On 21/09/2020 08:52, Neil Armstrong wrote:
Hi Steven, Rob,
Should I send a v3 with the commit log fixes ?
No need, I've fixed it up and pushed to drm-misc-next.
Thanks,
Steve
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.
On Sat, 19 Sep 2020, Rob Clark wrote:
> From: Rob Clark
>
> This will be used for non-block atomic commits.
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/drm_crtc.c | 11 +++
> include/drm/drm_crtc.h | 8
> 2 files changed, 19 insertions(+)
>
> diff --git a/drivers/
On Sat, Sep 19, 2020 at 12:37:23PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> The android userspace treats the display pipeline as a realtime problem.
> And arguably, if your goal is to not miss frame deadlines (ie. vblank),
> it is. (See https://lwn.net/Articles/809545/ for the best explaina
On Sat, Sep 19, 2020 at 12:37:25PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> This will allow us to more easily switch scheduling rules based on what
> userspace wants.
>
> Signed-off-by: Rob Clark
I still think switching to the highpriority systemwq as a start (like i915
already does) woul
On 20/09/2020 10:24, Daniel Vetter wrote:
> On Sat, Sep 19, 2020 at 9:31 PM Alex Dewar wrote:
>>
>> On 2020-09-11 13:57, Neil Armstrong wrote:
>>> On 09/09/2020 21:02, Alex Dewar wrote:
kmemdup can be used instead of kmalloc+memcpy. Replace an occurrence of
this pattern.
>> Friendly ping
On 20/09/2020 10:24, Daniel Vetter wrote:
> On Sat, Sep 19, 2020 at 9:31 PM Alex Dewar wrote:
>>
>> On 2020-09-11 13:57, Neil Armstrong wrote:
>>> On 09/09/2020 21:02, Alex Dewar wrote:
kmemdup can be used instead of kmalloc+memcpy. Replace an occurrence of
this pattern.
>> Friendly ping
On 9/18/2020 5:21 PM, Ville Syrjälä wrote:
On Fri, Sep 18, 2020 at 02:32:34PM +0530, Karthik B S wrote:
If flip is requested on any other plane, reject it.
Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.
If any of these are modified, reject
On Mon, Sep 21, 2020 at 11:21:54AM +0200, Daniel Vetter wrote:
> So question to rt/worker folks: What's the best way to let userspace set
> the scheduling mode and priorities of things the kernel does on its
> behalf? Surely we're not the first ones where if userspace runs with some
> rt priority
On 9/18/2020 5:23 PM, Ville Syrjälä wrote:
On Fri, Sep 18, 2020 at 12:30:45PM +0530, Karthik B S wrote:
This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.
v7: -Plane ctl n
On 9/18/2020 5:24 PM, Ville Syrjälä wrote:
On Wed, Sep 16, 2020 at 08:38:22PM +0530, Karthik B S wrote:
In Gen 9 and Gen 10 platforms, async address update enable bit is
double buffered. Due to this, during the transition from async flip
to sync flip we have to wait until this bit is updated b
On 9/18/2020 5:28 PM, Ville Syrjälä wrote:
On Wed, Sep 16, 2020 at 08:38:23PM +0530, Karthik B S wrote:
Add the details of the implementation of asynchronous flips for i915.
v7: -Rebased.
v8: -Rebased.
v9: -Rebased.
Signed-off-by: Karthik B S
Signed-off-by: Vandita Kulkarni
---
Documen
On 9/18/2020 5:33 PM, Ville Syrjälä wrote:
On Wed, Sep 16, 2020 at 08:38:24PM +0530, Karthik B S wrote:
Enable asynchronous flips in i915 for gen9+ platforms.
v2: -Async flip enablement should be a stand alone patch (Paulo)
v3: -Move the patch to the end of the series (Paulo)
v4: -Rebased.
Set the Async Address Update Enable bit in plane ctl
when async flip is requested.
v2: -Move the Async flip enablement to individual patch (Paulo)
v3: -Rebased.
v4: -Add separate plane hook for async flip case (Ville)
v5: -Rebased.
v6: -Move the plane hook to separate patch. (Paulo)
-Remov
Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.
Enable the flip done interrupt in IER.
Enable flip done function is called before writing the
surface address register as the write to this register triggers
the flip done interrupt
F
Without async flip support in the kernel, fullscreen apps where game
resolution is equal to the screen resolution, must perform an extra blit
per frame prior to flipping.
Asynchronous page flips will also boost the FPS of Mesa benchmarks.
v2: -Few patches have been squashed and patches have been
Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.
v2: -Moved the async check above vblank_get as it
was causing issues for PSR.
v3: -No need to wait for vblank to pass, as this wait was causing a
16ms delay once
If flip is requested on any other plane, reject it.
Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.
If any of these are modified, reject async flip.
v2: -Replace DRM_ERROR (Paulo)
-Add check for changes in OFFSET, FBC, RC(Paulo)
v3: -Remov
In Gen 9 and Gen 10 platforms, async address update enable bit is
double buffered. Due to this, during the transition from async flip
to sync flip we have to wait until this bit is updated before continuing
with the normal commit for sync flip.
v9: -Rename skl_toggle_async_sync() to skl_disable_as
Enable asynchronous flips in i915 for gen9+ platforms.
v2: -Async flip enablement should be a stand alone patch (Paulo)
v3: -Move the patch to the end of the series (Paulo)
v4: -Rebased.
v5: -Rebased.
v6: -Rebased.
v7: -Rebased.
v8: -Rebased.
v9: -Rebased.
v10: -Rebased.
Signed-off-by: Ka
Add the details of the implementation of asynchronous flips for i915.
v7: -Rebased.
v8: -Rebased.
v9: -Rebased.
v10: Move all documentation changes to this patch. (Ville)
Signed-off-by: Karthik B S
Signed-off-by: Vandita Kulkarni
Reviewed-by: Ville Syrjälä
---
Documentation/gpu/i915.rst
This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.
v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
-Add a vfunc for skl_program_async_surface_address
On Mon, 21 Sep 2020 14:08:48 +0300
Tomi Valkeinen wrote:
> Hi,
>
> On 04/09/2019 23:20, Ilia Mirkin wrote:
>
> >> Implement CTM color management property for OMAP CRTC using DSS
> >> overlay manager's Color Phase Rotation matrix. The CPR matrix does not
> >> exactly match the CTM pr
Hi Dave,
The following changes since commit 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5:
Linux 5.9-rc1 (2020-08-16 13:04:57 -0700)
are available in the Git repository at:
ssh://git.freedesktop.org/git/tegra/linux.git tags/drm/tegra/for-5.10-rc1
for you to fetch changes up to d9f980ebcd01d90a2
Hi
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag
fixing commit: 33b3ad3788ab ("drm/radeon: handle PCIe root ports with
addressing limitations").
The bot has tested the following trees: v5.8.10, v5.4.66.
v5.8.10: Build OK!
v5.4.66: Failed to appl
On Fri, Sep 04, 2020 at 04:53:02PM +0200, Krzysztof Kozlowski wrote:
> All Purism Librem5 phones have three compatibles so they need their own
> entry to fix dbts_check warnings like:
>
> arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dt.yaml: /:
> compatible: ['purism,librem5r2', 'purism,l
On 9/21/20 4:10 PM, Qinglang Miao wrote:
Simplify the return expression.
Signed-off-by: Qinglang Miao
---
drivers/gpu/host1x/cdma.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/host1x/cdma.c b/drivers/gpu/host1x/cdma.c
index e8d3fda91..08a0f9e10 1006
On Mon, Sep 21, 2020 at 04:12:20PM +0300, Mikko Perttunen wrote:
> On 9/21/20 4:10 PM, Qinglang Miao wrote:
> > Simplify the return expression.
> >
> > Signed-off-by: Qinglang Miao
> > ---
> > drivers/gpu/host1x/cdma.c | 8 +---
> > 1 file changed, 1 insertion(+), 7 deletions(-)
> >
> > d
Hi Bernard,
On Mon, 2020-09-21 at 19:11 +0800, Bernard wrote:
> This change will speed-up a bit these ipu_idmac_get &
> ipu_idmac_put processing and there is no need to protect
> kzalloc & kfree.
I don't think that will be measurable, the channel lock is very unlikely
to be contended. It might ma
On Mon, 2020-09-21 at 21:10 +0800, Qinglang Miao wrote:
> Simplify the return expression.
>
> Signed-off-by: Qinglang Miao
> ---
> drivers/gpu/drm/panfrost/panfrost_device.c | 8 +---
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.
Commit 7053e0eab473 ("drm/vram-helper: stop using TTM placement flags")
cleared the BO placement flags if top-down placement had been selected.
Hence, BOs that were supposed to go into VRAM are now placed in a default
location in system memory.
Trying to scanout the incorrectly pinned BO results i
Hi
Am 17.09.20 um 14:32 schrieb Christian König:
> Am 17.09.20 um 14:29 schrieb Thomas Zimmermann:
>> Hi Christian
>>
>> Am 17.09.20 um 13:12 schrieb Christian König:
>>> Hi Thomas,
>>>
>>> Am 17.09.20 um 12:51 schrieb Thomas Zimmermann:
Hi
Am 24.06.20 um 20:26 schrieb Nirmoy Das:
>
First off, I think you all did a fantastic job. I felt that things
ran very smoothly and, as far as the talks themselves go, I think it
went almost as smoothly as an in-person XDC. I'm really quite
impressed. I do have a couple pieces of more nuanced feedback:
1. I think we were maybe a bit to
Hello,
On Mon, Sep 21, 2020 at 11:21:54AM +0200, Daniel Vetter wrote:
> The part I don't like about this is that it all feels rather hacked
> together, and if we add more stuff (or there's some different thing in the
> system that also needs rt scheduling) then it doesn't compose.
>
> So question
Am 21.09.20 um 16:25 schrieb Thomas Zimmermann:
Commit 7053e0eab473 ("drm/vram-helper: stop using TTM placement flags")
cleared the BO placement flags if top-down placement had been selected.
Hence, BOs that were supposed to go into VRAM are now placed in a default
location in system memory.
Try
From: Dennis Li
[ Upstream commit 087d764159996ae378b08c0fdd557537adfd6899 ]
In the resume stage of GPU recovery, start_cpsch will call pm_init
which set pm->allocated as false, cause the next pm_release_ib has
no chance to release ib memory.
Add pm_release_ib in stop_cpsch which will be called
From: Dennis Li
[ Upstream commit 087d764159996ae378b08c0fdd557537adfd6899 ]
In the resume stage of GPU recovery, start_cpsch will call pm_init
which set pm->allocated as false, cause the next pm_release_ib has
no chance to release ib memory.
Add pm_release_ib in stop_cpsch which will be called
From: Bhawanpreet Lakha
[ Upstream commit 875d369d8f75275d30e59421602d9366426abff7 ]
[Why]
DTM topology updates happens by default now. This results in DTM
warnings when hdcp is not even being enabled. This spams the dmesg
and doesn't effect normal display functionality so it is better to log it
From: Michel Dänzer
[ Upstream commit 2f228aab21bbc74e90e267a721215ec8be51daf7 ]
Don't check drm_crtc_state::active for this either, per its
documentation in include/drm/drm_crtc.h:
* Hence drivers must not consult @active in their various
* &drm_mode_config_funcs.atomic_check callback to rej
From: Michel Dänzer
[ Upstream commit 2f228aab21bbc74e90e267a721215ec8be51daf7 ]
Don't check drm_crtc_state::active for this either, per its
documentation in include/drm/drm_crtc.h:
* Hence drivers must not consult @active in their various
* &drm_mode_config_funcs.atomic_check callback to rej
From: Dennis Li
[ Upstream commit 087d764159996ae378b08c0fdd557537adfd6899 ]
In the resume stage of GPU recovery, start_cpsch will call pm_init
which set pm->allocated as false, cause the next pm_release_ib has
no chance to release ib memory.
Add pm_release_ib in stop_cpsch which will be called
From: Jun Lei
[ Upstream commit c4790a8894232f39c25c7c546c06efe074e63384 ]
[why]
Recent characterization shows increased stutter latencies on some SKUs,
leading to underflow.
[how]
Update SOC params to account for this worst case latency.
Signed-off-by: Jun Lei
Acked-by: Aurabindo Pillai
Sig
From: Bhawanpreet Lakha
[ Upstream commit 4cdd7b332ed139b1e37faeb82409a14490adb644 ]
[Why]
Previously we were only calling add_topology when hdcp was being enabled.
Now we call add_topology by default so the ERROR messages are printed if
the firmware is not loaded.
This error message is not rel
From: Jun Lei
[ Upstream commit c4790a8894232f39c25c7c546c06efe074e63384 ]
[why]
Recent characterization shows increased stutter latencies on some SKUs,
leading to underflow.
[how]
Update SOC params to account for this worst case latency.
Signed-off-by: Jun Lei
Acked-by: Aurabindo Pillai
Sig
On 2020-09-21 4:40 p.m., Sasha Levin wrote:
From: Michel Dänzer
[ Upstream commit 2f228aab21bbc74e90e267a721215ec8be51daf7 ]
Don't check drm_crtc_state::active for this either, per its
documentation in include/drm/drm_crtc.h:
* Hence drivers must not consult @active in their various
* &dr
Stop using TTM_PL_FLAG_NO_EVICT.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_gem_vram_helper.c | 37 +++
include/drm/drm_gem_vram_helper.h | 3 ---
2 files changed, 9 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c
b/dri
Stop using TTM_PL_FLAG_NO_EVICT.
Signed-off-by: Christian König
---
drivers/gpu/drm/radeon/radeon.h | 1 -
drivers/gpu/drm/radeon/radeon_display.c | 9 ++
drivers/gpu/drm/radeon/radeon_object.c | 37 ++---
drivers/gpu/drm/radeon/radeon_object.h | 2 +-
driver
Stop using TTM_PL_FLAG_NO_EVICT.
Signed-off-by: Christian König
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 48 +++---
drivers/gpu/drm/nouveau/nouveau_bo.h | 3 --
drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +-
3 files changed, 13 insertions(+), 40 deletions(-)
diff --g
Not used any more.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 40
include/drm/ttm/ttm_bo_api.h | 24 --
2 files changed, 64 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index
Stop using TTM_PL_FLAG_NO_EVICT.
Signed-off-by: Christian König
---
drivers/gpu/drm/vmwgfx/vmwgfx_blit.c | 4 +-
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 48 +++---
drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c| 4 +-
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c| 2 +-
Not used any more.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c| 11 +++
include/drm/ttm/ttm_placement.h | 1 -
2 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 1a4b25083326..5737b3fae
As an alternative to the placement flag add a
pin count to the ttm buffer object.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 9 ++---
drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +-
include/drm/ttm/ttm_bo_api.h | 24
3 files changed, 31 i
Stop using TTM_PL_FLAG_NO_EVICT.
Signed-off-by: Christian König
---
drivers/gpu/drm/qxl/qxl_debugfs.c | 2 +-
drivers/gpu/drm/qxl/qxl_drv.h | 1 -
drivers/gpu/drm/qxl/qxl_ioctl.c | 4 +--
drivers/gpu/drm/qxl/qxl_object.c | 44 +--
drivers/gpu/drm/qxl/qxl_obj
Stop using TTM_PL_FLAG_NO_EVICT.
Signed-off-by: Christian König
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 5 ++-
driv
Hi guys,
The TTM_PL_FLAG_NO_EVICT flag was never a placement flag to begin with. Instead
it affects LRU and eviction handling.
So clean this up and provide the common logic of pinning/unpinning a buffer
object instead.
Since this affects basically all the driver using TTM please comment and/or
Just some dead code cleanup.
Signed-off-by: Christian König
---
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h| 1 -
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 30 --
2 files changed, 31 deletions(-)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
b/drivers/gpu/drm/vmwgfx/
Implement in the driver instead since it is the only user of that function.
Signed-off-by: Christian König
---
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 42 ++
drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c | 6 ++--
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h| 4 +++
driver
On Mon, Sep 21, 2020 at 2:23 AM Daniel Vetter wrote:
>
> On Sat, Sep 19, 2020 at 12:37:25PM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > This will allow us to more easily switch scheduling rules based on what
> > userspace wants.
> >
> > Signed-off-by: Rob Clark
>
> I still think switchin
Hi,
On 04/09/2019 23:20, Ilia Mirkin wrote:
>> Implement CTM color management property for OMAP CRTC using DSS
>> overlay manager's Color Phase Rotation matrix. The CPR matrix does not
>> exactly match the CTM property documentation. On DSS the CPR matrix is
>> applied after gamma
On Mon, Sep 21, 2020 at 2:21 AM Daniel Vetter wrote:
>
> On Sat, Sep 19, 2020 at 12:37:23PM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > The android userspace treats the display pipeline as a realtime problem.
> > And arguably, if your goal is to not miss frame deadlines (ie. vblank),
> >
On Mon, Sep 21, 2020 at 8:16 AM Rob Clark wrote:
>
> On Mon, Sep 21, 2020 at 2:21 AM Daniel Vetter wrote:
> >
> > On Sat, Sep 19, 2020 at 12:37:23PM -0700, Rob Clark wrote:
> > > From: Rob Clark
> > >
> > > The android userspace treats the display pipeline as a realtime problem.
> > > And arguab
Leave the inuse count intact on map failure to keep the accounting
accurate.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/msm_gem_vma.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c
b/drivers/gpu/drm/msm/msm_gem_vma.c
index 80a
In the case where we have a back-to-back submission that shares the same
BO, this BO will be prematurely moved to inactive_list while retiring the
first submit. But it will be still part of the second submit which is
being processed by the GPU. Now, if the shrinker happens to be triggered at
this p
Hi, Matthias:
Matthias Brugger 於 2020年9月21日 週一 下午4:53寫道：
>
>
>
> On 21/09/2020 01:42, Chun-Kuang Hu wrote:
> > For each client driver, its timeout handler need to dump hardware register
> > or its state machine information, so remove timeout handler in helper
> > function and let client driver im
On Mon, Sep 21, 2020 at 8:27 AM Akhil P Oommen wrote:
>
> In the case where we have a back-to-back submission that shares the same
> BO, this BO will be prematurely moved to inactive_list while retiring the
> first submit. But it will be still part of the second submit which is
> being processed b
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