On 18. 08. 20, 9:25, Gerd Hoffmann wrote:
> When going through a disable/enable cycle without changing the
> framebuffer the optimization added by commit 3954ff10e06e ("drm/virtio:
> skip set_scanout if framebuffer didn't change") causes the screen stay
> blank. Add a bool to force an update to fi
I've also given this a spin here, seems to be okay.
I've read the patches and they all seem fine.
Reviewed-by: Dave Airlie
for all 3 patches.
Dave.
On Sat, 22 Aug 2020 at 02:00, Christian König
wrote:
>
> Hi guys,
>
> so I got some hardware and tested this and after hammering out tons of typos
On Sat, 22 Aug 2020 11:59:26 +0200
Michel Dänzer wrote:
> On 2020-08-21 8:07 p.m., Kazlauskas, Nicholas wrote:
> > On 2020-08-21 12:57 p.m., Michel Dänzer wrote:
> >> From: Michel Dänzer
> >>
> >> Don't check drm_crtc_state::active for this either, per its
> >> documentation in include/drm/drm
Hi,
On 15/08/2020 15:05, Ezequiel Garcia wrote:
> Hi Neil,
>
> On Wed, 2020-07-01 at 09:35 +0300, Adrian Ratiu wrote:
>> Hi Neil,
>>
>> On Mon, 29 Jun 2020, Neil Armstrong
>> wrote:
>>> Hi Adrian,
>>>
>>> On 09/06/2020 19:49, Adrian Ratiu wrote:
[...]
>>
>
> It's been a month so I think it'
Hi,
On 12/08/2020 10:36, Algea Cao wrote:
> If plat_data->get_output_bus_format() is exist, we can
> use it to get hdmi output bus format when dw-hdmi is the
> only bridge. The hdmi output bus format can be set by vendor
> properties.
>
> Signed-off-by: Algea Cao
> ---
>
> drivers/gpu/drm/brid
On 12/08/2020 10:34, Algea Cao wrote:
> Introduce previous_pixelclock/previous_tmdsclock to
> determine whether PHY needs initialization. If phy is power off,
> or mpixelclock/mtmdsclock is different to previous value, phy is
> neet to be reinitialized.
>
> Signed-off-by: Algea Cao
> ---
>
> dr
The drm scheduler currently expects that the stop/start sequence is always
executed in the timeout handling, as the job at the head of the hardware
execution list is always removed from the ring mirror before the driver
function is called and only inserted back into the list when starting the
sched
Hi Russell,
Am Sonntag, den 23.08.2020, 20:19 +0100 schrieb Russell King - ARM Linux admin:
> On Sun, Aug 23, 2020 at 09:10:25PM +0200, Christian Gmeiner wrote:
> > Hi
> >
> > > I have formally tested the patch with 5.7.10 - and it doesn't resolve
> > > the issue - sadly :(
> > >
> > > From my t
Am Sonntag, den 23.08.2020, 21:09 +0200 schrieb Christian Gmeiner:
> It looks like that this GPU core triggers an abort when
> reading VIVS_HI_CHIP_PRODUCT_ID and/or VIVS_HI_CHIP_ECO_ID.
>
> I looked at different versions of Vivante's kernel driver and did
> not found anything about this issue or
On Fri, Aug 21, 2020 at 06:27:37PM +0300, Tomer Samara wrote:
> BUG_ON() is removed at ion_page_pool.c
>
> Fixes the following issue:
> Avoid crashing the kernel - try using WARN_ON & recovery code ratherthan
> BUG() or BUG_ON().
>
> Signed-off-by: Tomer Samara
> ---
You should put a note here
On Mon, Aug 24, 2020 at 02:24:57PM +0300, Dan Carpenter wrote:
> On Fri, Aug 21, 2020 at 09:25:26AM -0700, Randy Dunlap wrote:
> > On 8/21/20 8:28 AM, Tomer Samara wrote:
> > > Remove BUG() from ion_sytem_heap.c
> > >
> > > this fix the following checkpatch issue:
> > > Avoid crashing the kernel -
On Fri, Aug 21, 2020 at 09:25:26AM -0700, Randy Dunlap wrote:
> On 8/21/20 8:28 AM, Tomer Samara wrote:
> > Remove BUG() from ion_sytem_heap.c
> >
> > this fix the following checkpatch issue:
> > Avoid crashing the kernel - try using WARN_ON &
> > recovery code ratherthan BUG() or BUG_ON().
> >
>
Hi Robin,
On 20.08.2020 17:08, Robin Murphy wrote:
> Hi all,
>
> After 5 years or so of intending to get round to this, finally the
> time comes! The changes themselves actualy turn out to be relatively
> mechanical; the bigger concern appears to be how to get everything
> merged across about 5 di
On Mon, Aug 24, 2020 at 02:27:08PM +0300, Dan Carpenter wrote:
> On Mon, Aug 24, 2020 at 02:24:57PM +0300, Dan Carpenter wrote:
> > On Fri, Aug 21, 2020 at 09:25:26AM -0700, Randy Dunlap wrote:
> > > On 8/21/20 8:28 AM, Tomer Samara wrote:
> > > > Remove BUG() from ion_sytem_heap.c
> > > >
> > > >
On Mon, Aug 24, 2020 at 01:02:48PM +0200, Lucas Stach wrote:
> The drm scheduler currently expects that the stop/start sequence is always
> executed in the timeout handling, as the job at the head of the hardware
> execution list is always removed from the ring mirror before the driver
> function i
Hi All,
Here is v6 of my patch series converting the i915 driver's code for
controlling the panel's backlight with an external PWM controller to
use the atomic PWM API. See below for the changelog.
This version of the series has been rebased on 5.9-rc1 and has
a Reviewed-by or Acked-by for all pa
The CRC PWM controller has a clock-divider which divides the clock with
a value between 1-128. But as can seen from the PWM_DIV_CLK_xxx
defines, this range maps to a register value of 0-127.
So after calculating the clock-divider we must subtract 1 to get the
register value, unless the requested f
Replace the enable, disable and config pwm_ops with an apply op,
to support the new atomic PWM API.
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v6:
- Rebase on 5.9-rc1
- Use do_div when calculating level because pwm_state.period and .duty_cycle
are now u64
Changes
According to the data-sheet the way the PWM controller works is that
each input clock-cycle the base_unit gets added to a N bit counter and
that counter overflowing determines the PWM output frequency.
So assuming e.g. a 16 bit counter this means that if base_unit is set to 1,
after 65535 input cl
The pwm-crc code is using 2 different enable bits:
1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE)
2. bit 0 of the BACKLIGHT_EN register
So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM,
this commit makes crc_pwm_disable() clear it on disable and makes
crc_pwm_enable() set i
The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM
controller gets poked from the _PS0 method of the graphics-card device:
Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */
If (((Local0 & 0x03) == 0x03))
{
PSAT &= 0xFFFC
Local1 = PSA
When the user requests a high enough period ns value, then the
calculations in pwm_lpss_prepare() might result in a base_unit value of 0.
But according to the data-sheet the way the PWM controller works is that
each input clock-cycle the base_unit gets added to a N bit counter and
that counter ove
The pwm-crc code is using 2 different enable bits:
1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE)
2. bit 0 of the BACKLIGHT_EN register
The BACKLIGHT_EN register at address 0x51 really controls a separate
output-only GPIO which is earmarked to be used as output connected to the
backlight-enable
Implement the pwm_ops.get_state() method to complete the support for the
new atomic PWM API.
Reviewed-by: Andy Shevchenko
Signed-off-by: Hans de Goede
---
Changes in v6:
- Rebase on 5.9-rc1
- Use DIV_ROUND_UP_ULL because pwm_state.period and .duty_cycle are now u64
Changes in v5:
- Fix an inden
Before this commit a suspend + resume of the LPSS PWM controller
would result in the controller being reset to its defaults of
output-freq = clock/256, duty-cycle=100%, until someone changes
to the output-freq and/or duty-cycle are made.
This problem has been masked so far because the main consume
Factor the code which checks and drm_dbg_kms-s the VBT PWM frequency
out of get_backlight_max_vbt().
This is a preparation patch for honering the VBT PWM frequency for
devices which use an external PWM controller (devices using
pwm_setup_backlight()).
Acked-by: Jani Nikula
Signed-off-by: Hans de
The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM
controller gets turned off from the _PS3 method of the graphics-card dev:
Method (_PS3, 0, Serialized) // _PS3: Power State 3
{
...
PWMB = PWMC /* \_SB_.PCI
In the not-enabled -> enabled path pwm_lpss_apply() needs to get a
runtime-pm reference; and then on any errors it needs to release it
again.
This leads to somewhat hard to read code. This commit introduces a new
pwm_lpss_prepare_enable() helper and moves all the steps necessary for
the not-enable
While looking into adding atomic-pwm support to the pwm-crc driver I
noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and
there is a clock-divider which divides this with a value between 1-128,
and there are 256 duty-cycle steps.
The pwm-crc code before this commit assumed that a clo
So far for devices using an external PWM controller (devices using
pwm_setup_backlight()), we have been hardcoding the minimum allowed
PWM level to 0. But several of these devices specify a non 0 minimum
setting in their VBT.
Change pwm_setup_backlight() to use get_backlight_min_vbt() to get
the m
So far for devices using an external PWM controller (devices using
pwm_setup_backlight()), we have been hardcoding the period-time passed to
pwm_config() to 21333 ns.
I suspect this was done because many VBTs set the PWM frequency to 200
which corresponds to a period-time of 500 ns, which grea
Now that the PWM drivers which we use have been converted to the atomic
PWM API, we can move the i915 panel code over to using the atomic PWM API.
The removes a long standing FIXME and this removes a flicker where
the backlight brightness would jump to 100% when i915 loads even if
using the fastse
https://bugzilla.kernel.org/show_bug.cgi?id=208997
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
Em Mon, 24 Aug 2020 08:49:30 +0200
Mauro Carvalho Chehab escreveu:
> Hi John,
>
> Em Wed, 19 Aug 2020 20:28:44 -0700
> John Stultz escreveu:
>
>
> > That said even with the patches I've got on top of your series, I
> > still see a few issues:
> > 1) I'm seeing red-blue swap with your driver.
On Fri, 21 Aug 2020 at 19:24, Paul Cercueil wrote:
>
>
>
> Le sam. 22 août 2020 à 0:11, Paul Boddie a
> écrit :
> > On Friday, 21 August 2020 15:32:46 CEST Ezequiel Garcia wrote:
> >> On Thu, 20 Aug 2020 at 19:49, Paul Boddie
> >> wrote:
> >> >
> >> > It still doesn't work for me. I still get
On 2020-08-23 22:34, Dmitry Osipenko wrote:
21.08.2020 03:11, Robin Murphy пишет:
...
Hello, Robin! Thank you for yours work!
Some drivers, like this Tegra VDE (Video Decoder Engine) driver for
example, do not want to use implicit IOMMU domain.
That isn't (intentionally) changing here - the o
Hi Lucas,
On Mon, Aug 24, 2020 at 8:02 AM Lucas Stach wrote:
>
> The drm scheduler currently expects that the stop/start sequence is always
> executed in the timeout handling, as the job at the head of the hardware
> execution list is always removed from the ring mirror before the driver
> functi
On 2020-08-24 01:26, Laurent Pinchart wrote:
> Hi Stefan,
>
> On Fri, Aug 21, 2020 at 04:53:56PM +0200, Stefan Agner wrote:
>> On 2020-08-13 03:29, Laurent Pinchart wrote:
>> > Additional compatible strings have been added in DT source for the
>> > i.MX6SL, i.MX6SLL, i.MX6UL and i.MX7D without upd
On Sat, Aug 22, 2020 at 5:02 AM Youling Tang wrote:
>
> Remove duplicate semicolons at the end of line.
>
> Signed-off-by: Youling Tang
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
> drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 +-
>
https://bugzilla.kernel.org/show_bug.cgi?id=209017
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
Applied. Thanks!
Alex
On Sun, Aug 23, 2020 at 11:00 PM Quan, Evan wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks for fixing this. The patch is reviewed-by: Evan Quan
>
>
> BR
> Evan
> -Original Message-
> From: Randy Dunlap
> Sent: Monday, August 24, 2020
https://bugzilla.kernel.org/show_bug.cgi?id=209015
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
On Thu, Aug 06, 2020 at 03:46:23AM -0700, syzbot wrote:
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:47ec5303 Merge git://git.kernel.org/pub/scm/linux/kernel/g..
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt?x=16fe1dea90
> kernel
https://bugzilla.kernel.org/show_bug.cgi?id=209019
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
On Fri, Aug 21, 2020 at 01:43:39PM -0400, Lyude Paul wrote:
> [...]
> > The wording is a bit unclear, but as I understand the Standard only
> > calls for the above:
> >
> > """
> > A DP upstream device shall read the capability from DPCD Addresses 00080h
> > through 00083h. A DP Branch device wit
Em Fri, 21 Aug 2020 17:56:50 +0200
Sam Ravnborg escreveu:
> Hi Mauro.
>
> On Fri, Aug 21, 2020 at 04:41:58PM +0200, Mauro Carvalho Chehab wrote:
> > Another quick question:
> >
> > Em Wed, 19 Aug 2020 19:35:58 +0200
> > Sam Ravnborg escreveu:
> >
> > > > +#define DSS_REDUCE(x) ((x) > 0 ? (
From: Xin He
[ Upstream commit 836b194d65782aaec4485a07d2aab52d3f698505 ]
Before setting shmem->pages to NULL, kfree() should
be called.
Signed-off-by: Xin He
Reviewed-by: Qi Liu
Link:
http://patchwork.freedesktop.org/patch/msgid/20200722051851.72662-1-hexin...@bytedance.com
Signed-off-by: G
From: Evan Quan
[ Upstream commit 2c5b8080d810d98e3e59617680218499b17c84a1 ]
The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to
assume the bootup state in SMU based on the dpm status.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-b
From: Anthony Koo
[ Upstream commit e4ed4dbbc8383d42a197da8fe7ca6434b0f14def ]
[Why]
1. There is a calculation that is using frame_time_in_us instead of
last_render_time_in_us to calculate whether choosing an LFC multiplier
would cause the inserted frame duration to be outside of range.
2. We d
From: Evan Quan
[ Upstream commit 266d81d9eed30f4994d76a2b237c63ece062eefe ]
Correct the cached smu feature state on pp_features sysfs
setting.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../drm/amd/powerplay/hwmgr/vega20_hwmg
From: Anthony Koo
[ Upstream commit abba907c7a20032c2d504fd5afe3af7d440a09d0 ]
[Why]
Using FRAME_UPDATE will result in infopacket to be potentially updated
one frame late.
In commit stream scenarios for previously active stream, some stale
infopacket data from previous config might be erroneousl
From: Huang Rui
[ Upstream commit 34174b89bfa495bed9cddcc504fb38feca90fab7 ]
Renoir only has one sdma instance, it will get failed once query the
sdma1 registers. So use switch-case instead of static register array.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Felix Kuehlin
From: Jiansong Chen
[ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
Newly released sdma fw (51.52) provides a fix for the issue.
Signed-off-by: Jiansong Chen
Reviewed-by: Kenneth Feng
Reviewed-by: Tao Zhou
Acked-by: A
From: Guchun Chen
[ Upstream commit 1a68d96f81b8e7eb2a121fbf9abf9e5974e58832 ]
When unloading driver by "modprobe -r amdgpu", one NULL pointer
dereference bug occurs in ras debugfs releasing. The cause is the
duplicated debugfs_remove, as drm debugfs_root dir has been cleaned
up already by drm_m
From: Jiansong Chen
[ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
gfxoff is temporarily disabled for navy_flounder,
since at present the feature has broken some basic
amdgpu test.
Signed-off-by: Jiansong Chen
Reviewed-by: Tao Zhou
Signed-off-by: Alex Deucher
Signed-off-by: Sas
From: Evan Quan
[ Upstream commit 266d81d9eed30f4994d76a2b237c63ece062eefe ]
Correct the cached smu feature state on pp_features sysfs
setting.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../drm/amd/powerplay/hwmgr/vega20_hwmg
From: Anthony Koo
[ Upstream commit abba907c7a20032c2d504fd5afe3af7d440a09d0 ]
[Why]
Using FRAME_UPDATE will result in infopacket to be potentially updated
one frame late.
In commit stream scenarios for previously active stream, some stale
infopacket data from previous config might be erroneousl
From: Anthony Koo
[ Upstream commit e4ed4dbbc8383d42a197da8fe7ca6434b0f14def ]
[Why]
1. There is a calculation that is using frame_time_in_us instead of
last_render_time_in_us to calculate whether choosing an LFC multiplier
would cause the inserted frame duration to be outside of range.
2. We d
From: Xin He
[ Upstream commit 836b194d65782aaec4485a07d2aab52d3f698505 ]
Before setting shmem->pages to NULL, kfree() should
be called.
Signed-off-by: Xin He
Reviewed-by: Qi Liu
Link:
http://patchwork.freedesktop.org/patch/msgid/20200722051851.72662-1-hexin...@bytedance.com
Signed-off-by: G
From: Evan Quan
[ Upstream commit 2c5b8080d810d98e3e59617680218499b17c84a1 ]
The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to
assume the bootup state in SMU based on the dpm status.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-b
From: Jiansong Chen
[ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
gfxoff is temporarily disabled for navy_flounder,
since at present the feature has broken some basic
amdgpu test.
Signed-off-by: Jiansong Chen
Reviewed-by: Tao Zhou
Signed-off-by: Alex Deucher
Signed-off-by: Sas
From: Evan Quan
[ Upstream commit 266d81d9eed30f4994d76a2b237c63ece062eefe ]
Correct the cached smu feature state on pp_features sysfs
setting.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../drm/amd/powerplay/hwmgr/vega20_hwmg
From: Anthony Koo
[ Upstream commit abba907c7a20032c2d504fd5afe3af7d440a09d0 ]
[Why]
Using FRAME_UPDATE will result in infopacket to be potentially updated
one frame late.
In commit stream scenarios for previously active stream, some stale
infopacket data from previous config might be erroneousl
From: Huang Rui
[ Upstream commit 34174b89bfa495bed9cddcc504fb38feca90fab7 ]
Renoir only has one sdma instance, it will get failed once query the
sdma1 registers. So use switch-case instead of static register array.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Felix Kuehlin
From: Guchun Chen
[ Upstream commit 1a68d96f81b8e7eb2a121fbf9abf9e5974e58832 ]
When unloading driver by "modprobe -r amdgpu", one NULL pointer
dereference bug occurs in ras debugfs releasing. The cause is the
duplicated debugfs_remove, as drm debugfs_root dir has been cleaned
up already by drm_m
From: Jiansong Chen
[ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
gfxoff is temporarily disabled for navy_flounder,
since at present the feature has broken some basic
amdgpu test.
Signed-off-by: Jiansong Chen
Reviewed-by: Tao Zhou
Signed-off-by: Alex Deucher
Signed-off-by: Sas
From: Jiansong Chen
[ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
Newly released sdma fw (51.52) provides a fix for the issue.
Signed-off-by: Jiansong Chen
Reviewed-by: Kenneth Feng
Reviewed-by: Tao Zhou
Acked-by: A
From: Jiansong Chen
[ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
Newly released sdma fw (51.52) provides a fix for the issue.
Signed-off-by: Jiansong Chen
Reviewed-by: Kenneth Feng
Reviewed-by: Tao Zhou
Acked-by: A
From: Evan Quan
[ Upstream commit 2c5b8080d810d98e3e59617680218499b17c84a1 ]
The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to
assume the bootup state in SMU based on the dpm status.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-b
https://bugzilla.kernel.org/show_bug.cgi?id=209017
Clément Guérin (li...@protonmail.com) changed:
What|Removed |Added
Status|NEW |RESOLVED
https://bugzilla.kernel.org/show_bug.cgi?id=209017
--- Comment #3 from Alex Deucher (alexdeuc...@gmail.com) ---
Yes, gitlab is preferred.
--
You are receiving this mail because:
You are watching the assignee of the bug.
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dri-d
On Wed, Aug 19, 2020 at 10:51:48PM +0200, Linus Walleij wrote:
> Let's use a common.yaml include for the backlight like we do with
> the LEDs. The LEDs are inherently incompatible so their bindings
> cannot be reused for backlight.
>
> Cc: devicet...@vger.kernel.org
> Suggested-by: Sam Ravnborg
>
On Wed, 19 Aug 2020 22:51:49 +0200, Linus Walleij wrote:
> This adds device tree bindings for the Kinetic KTD253
> white LED backlight driver.
>
> Cc: devicet...@vger.kernel.org
> Cc: Sam Ravnborg
> Signed-off-by: Linus Walleij
> ---
> ChangeLog v2->v3:
> - Drop the pointless cargo-culted "defau
On Mon, 24 Aug 2020 at 13:05, H. Nikolaus Schaller wrote:
>
> Hi Ezequiel,
>
> > Am 24.08.2020 um 15:46 schrieb Ezequiel Garcia
> > :
> >
> > On Fri, 21 Aug 2020 at 19:24, Paul Cercueil wrote:
> >>
> >>
> >>
> >> Le sam. 22 août 2020 à 0:11, Paul Boddie a
> >> écrit :
> >>
> >> If you send clea
On Thu, 2020-08-20 at 21:03 +0300, Imre Deak wrote:
> On Thu, Aug 20, 2020 at 12:27:03PM +1000, Sam McNally wrote:
> > > > [...]
> > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> > > > b/drivers/gpu/drm/drm_dp_mst_topology.c
> > > > index 1ac874e4e7a1..73a2299c2faa 100644
> > > > --- a/d
On Mon, Aug 24, 2020 at 12:36 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
>
> This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
> Newly released sdma fw (51.52) provides a fix for the issue.
>
> Signed-off-by: Jiansong
On Mon, Aug 24, 2020 at 12:36 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
>
> gfxoff is temporarily disabled for navy_flounder,
> since at present the feature has broken some basic
> amdgpu test.
>
> Signed-off-by: Jiansong Chen
On Mon, Aug 24, 2020 at 12:37 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
>
> gfxoff is temporarily disabled for navy_flounder,
> since at present the feature has broken some basic
> amdgpu test.
>
> Signed-off-by: Jiansong Chen
On Mon, Aug 24, 2020 at 12:38 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ]
>
> gfxoff is temporarily disabled for navy_flounder,
> since at present the feature has broken some basic
> amdgpu test.
>
> Signed-off-by: Jiansong Chen
On Mon, Aug 24, 2020 at 12:37 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
>
> This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
> Newly released sdma fw (51.52) provides a fix for the issue.
>
> Signed-off-by: Jiansong
On Mon, Aug 24, 2020 at 12:38 PM Sasha Levin wrote:
>
> From: Jiansong Chen
>
> [ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ]
>
> This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3.
> Newly released sdma fw (51.52) provides a fix for the issue.
>
> Signed-off-by: Jiansong
Not entirely sure why this never came up when I originally tested this
(maybe some BIOSes already have this setup?) but the ->caps_init vfunc
appears to cause the display engine to throw an exception on driver
init, at least on my ThinkPad P72:
nouveau :01:00.0: disp: chid 0 mthd 008c data 000
Since I'm almost certain I didn't get capability checking right for
pre-volta chipsets, let's start logging any caps we find to make things
like this obvious in the future.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 10 ++
1 file changed, 10 insertions(+)
di
This code was using get_user_pages*(), in a "Case 2" scenario
(DMA/RDMA), using the categorization from [1]. That means that it's
time to convert the get_user_pages*() + put_page() calls to
pin_user_pages*() + unpin_user_pages() calls.
There is some helpful background in [2]: basically, this is a
From: Rob Clark
In a later patch, the drvdata will not directly be 'struct msm_gpu *',
so add a helper to reduce the churn.
Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 10 --
drivers/gpu/drm/msm/msm_gpu.c | 6 +++--
From: Jordan Crouse
Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected
by the io-pgtable configuration.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 21 -
drivers/iommu/arm/arm-smmu/arm-smmu.h | 25
From: Rob Clark
This interface will be used for drm/msm to coordinate with the
qcom_adreno_smmu_impl to enable/disable TTBR0 translation.
Once TTBR0 translation is enabled, the GPU's CP (Command Processor)
will directly switch TTBR0 pgtables (and do the necessary TLB inv)
synchronized to the GPU
From: Jordan Crouse
Every Qcom Adreno GPU has an embedded SMMU for its own use. These
devices depend on unique features such as split pagetables,
different stall/halt requirements and other settings. Identify them
with a compatible string so that they can be identified in the
arm-smmu implementat
From: Rob Clark
Sprinkle a few `const`s where helpers don't need write access.
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h
b/drivers/iommu/arm/arm-smmu/arm-sm
From: Rob Clark
Currently it doesn't matter, since we free the ctx immediately. But
when we start refcnt'ing the ctx, we don't want old dangling list
entries to hang around.
Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++-
1 file changed
From: Jordan Crouse
Construct the io-pgtable config before calling the implementation specific
init_context function and pass it so the implementation specific function
can get a chance to change it before the io-pgtable is created.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
dr
From: Jordan Crouse
Each submitqueue is attached to a context. Add a pointer to the
context to the submitqueue at create time and refcount it so
that it stays around through the life of the queue.
Co-developed-by: Rob Clark
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gp
From: Jordan Crouse
Do a bit of prep work to add the upcoming adreno-smmu implementation.
Add an hook to allow the implementation to choose which context banks
to allocate.
Move some of the common structs to arm-smmu.h in anticipation of them
being used by the implementations and update some of
From: Rob Clark
This series adds an Adreno SMMU implementation to arm-smmu to allow GPU hardware
pagetable switching.
The Adreno GPU has built in capabilities to switch the TTBR0 pagetable during
runtime to allow each individual instance or application to have its own
pagetable. In order to tak
From: Jordan Crouse
Add a special implementation for the SMMU attached to most Adreno GPU
target triggered from the qcom,adreno-smmu compatible string.
The new Adreno SMMU implementation will enable split pagetables
(TTBR1) for the domain attached to the GPU device (SID 0) and
hard code it conte
From: Rob Clark
This will be populated by adreno-smmu, to provide a way for coordinating
enabling/disabling TTBR0 translation.
Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 2 --
drivers/gpu/drm/msm/msm_gpu.c | 2 +-
drivers/
From: Jordan Crouse
Add support to create a io-pgtable for use by targets that support
per-instance pagetables. In order to support per-instance pagetables the
GPU SMMU device needs to have the qcom,adreno-smmu compatible string and
split pagetables enabled.
Signed-off-by: Jordan Crouse
Signed-
From: Rob Clark
In $debugfs/gem we already show any vma(s) associated with an object.
Also show process names if the vma's address space is a per-process
address space.
Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
drivers/gpu/drm/msm/msm_g
From: Jordan Crouse
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adre
From: Jordan Crouse
Add support for allocating private address space instances. Targets that
support per-context pagetables should implement their own function to
allocate private address spaces.
The default will return a pointer to the global address space.
Signed-off-by: Jordan Crouse
Signed
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