On Tue, Dec 10, 2019 at 02:30:48PM +0200, Jani Nikula wrote:
> Prefer drm_dbg_atomic().
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_agpsupport.c | 4 +-
> drivers/gpu/drm/drm_atomic.c | 187 +--
> 2 files changed, 102 insertions(+), 89 deletions(-
On Fri, 06 Dec 2019, Chuhong Yuan wrote:
> nv50_msto_disable() does not call nv50_outp_release() to match
> nv50_outp_acquire() like other disable().
> Add the missed call to fix it.
The subject prefix "drm/dp_mst" implies drm core change, but this is
about nouveau. Please fix.
BR,
Jani.
>
> Si
From: Dan Williams
After the removal of the device-public infrastructure there are only 2
->page_free() call backs in the kernel. One of those is a device-private
callback in the nouveau driver, the other is a generic wakeup needed in
the DAX case. In the hopes that all ->page_free() callbacks ca
1. Convert from get_user_pages() to pin_user_pages().
2. As required by pin_user_pages(), release these pages via
put_user_page().
Reviewed-by: Jan Kara
Signed-off-by: John Hubbard
---
arch/powerpc/mm/book3s64/iommu_api.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff -
Hi,
This implements an API naming change (put_user_page*() -->
unpin_user_page*()), and also implements tracking of FOLL_PIN pages. It
extends that tracking to a few select subsystems. More subsystems will
be added in follow up work.
Christoph Hellwig, a point of interest:
a) I've moved the bulk
Convert drm/via to use the new pin_user_pages_fast() call, which sets
FOLL_PIN. Setting FOLL_PIN is now required for code that requires
tracking of pinned pages, and therefore for any code that calls
put_user_page().
In partial anticipation of this work, the drm/via driver was already
calling put_
There are four locations in gup.c that have a fair amount of code
duplication. This means that changing one requires making the same
changes in four places, not to mention reading the same code four
times, and wondering if there are subtle differences.
Factor out the common code into static functi
1. Call the new global pin_user_pages_fast(), from pin_goldfish_pages().
2. As required by pin_user_pages(), release these pages via
put_user_page(). In this case, do so via put_user_pages_dirty_lock().
That has the side effect of calling set_page_dirty_lock(), instead
of set_page_dirty(). This i
An upcoming patch changes and complicates the refcounting and
especially the "put page" aspects of it. In order to keep
everything clean, refactor the devmap page release routines:
* Rename put_devmap_managed_page() to page_is_devmap_managed(),
and limit the functionality to "read only": return
Fix the gup benchmark flags to use the symbolic FOLL_WRITE,
instead of a hard-coded "1" value.
Also, clean up the filtering of gup flags a little, by just doing
it once before issuing any of the get_user_pages*() calls. This
makes it harder to overlook, instead of having little "gup_flags & 1"
phr
Convert infiniband to use the new pin_user_pages*() calls.
Also, revert earlier changes to Infiniband ODP that had it using
put_user_page(). ODP is "Case 3" in
Documentation/core-api/pin_user_pages.rst, which is to say, normal
get_user_pages() and put_page() is the API to use there.
The new pin_u
Convert net/xdp to use the new pin_longterm_pages() call, which sets
FOLL_PIN. Setting FOLL_PIN is now required for code that requires
tracking of pinned pages.
In partial anticipation of this work, the net/xdp code was already
calling put_user_page() instead of put_page(). Therefore, in order to
1. Change v4l2 from get_user_pages() to pin_user_pages().
2. Because all FOLL_PIN-acquired pages must be released via
put_user_page(), also convert the put_page() call over to
put_user_pages_dirty_lock().
Acked-by: Hans Verkuil
Cc: Ira Weiny
Signed-off-by: John Hubbard
---
drivers/media/v4l2-
After DMA is complete, and the device and CPU caches are synchronized,
it's still required to mark the CPU pages as dirty, if the data was
coming from the device. However, this driver was just issuing a
bare put_page() call, without any set_page_dirty*() call.
Fix the problem, by calling set_page_
1. Avoid naming conflicts: rename local static function from
"pin_user_pages()" to "goldfish_pin_pages()".
An upcoming patch will introduce a global pin_user_pages()
function.
Reviewed-by: Jan Kara
Reviewed-by: Jérôme Glisse
Reviewed-by: Ira Weiny
Signed-off-by: John Hubbard
---
drivers/plat
Convert fs/io_uring to use the new pin_user_pages() call, which sets
FOLL_PIN. Setting FOLL_PIN is now required for code that requires
tracking of pinned pages, and therefore for any code that calls
put_user_page().
In partial anticipation of this work, the io_uring code was already
calling put_us
Convert process_vm_access to use the new pin_user_pages_remote()
call, which sets FOLL_PIN. Setting FOLL_PIN is now required for
code that requires tracking of pinned pages.
Also, release the pages via put_user_page*().
Also, rename "pages" to "pinned_pages", as this makes for
easier reading of p
Add tracking of pages that were pinned via FOLL_PIN.
As mentioned in the FOLL_PIN documentation, callers who effectively set
FOLL_PIN are required to ultimately free such pages via unpin_user_page().
The effect is similar to FOLL_GET, and may be thought of as "FOLL_GET
for DIO and/or RDMA use".
P
An upcoming patch uses try_get_compound_head() more widely,
so move it to the top of gup.c.
Also fix a tiny spelling error and a checkpatch.pl warning.
Reviewed-by: Christoph Hellwig
Reviewed-by: Jan Kara
Reviewed-by: Ira Weiny
Signed-off-by: John Hubbard
---
mm/gup.c | 29 +++---
Update VFIO to take advantage of the recently loosened restriction on
FOLL_LONGTERM with get_user_pages_remote(). Also, now it is possible to
fix a bug: the VFIO caller is logically a FOLL_LONGTERM user, but it
wasn't setting FOLL_LONGTERM.
Also, remove an unnessary pair of calls that were releasi
It's good to have basic unit test coverage of the new FOLL_PIN
behavior. Fortunately, the gup_benchmark unit test is extremely
fast (a few milliseconds), so adding it the the run_vmtests suite
is going to cause no noticeable change in running time.
So, add two new invocations to run_vmtests:
1) R
Up until now, gup_benchmark supported testing of the
following kernel functions:
* get_user_pages(): via the '-U' command line option
* get_user_pages_longterm(): via the '-L' command line option
* get_user_pages_fast(): as the default (no options required)
Add test coverage for the new correspon
In order to provide a clearer, more symmetric API for pinning
and unpinning DMA pages. This way, pin_user_pages*() calls
match up with unpin_user_pages*() calls, and the API is a lot
closer to being self-explanatory.
Reviewed-by: Jan Kara
Signed-off-by: John Hubbard
---
Documentation/core-api/p
1. Change vfio from get_user_pages_remote(), to
pin_user_pages_remote().
2. Because all FOLL_PIN-acquired pages must be released via
put_user_page(), also convert the put_page() call over to
put_user_pages_dirty_lock().
Note that this effectively changes the code's behavior in
vfio_iommu_type1.c:
As it says in the updated comment in gup.c: current FOLL_LONGTERM
behavior is incompatible with FAULT_FLAG_ALLOW_RETRY because of the
FS DAX check requirement on vmas.
However, the corresponding restriction in get_user_pages_remote() was
slightly stricter than is actually required: it forbade all
And get rid of the mmap_sem calls, as part of that. Note
that get_user_pages_fast() will, if necessary, fall back to
__gup_longterm_unlocked(), which takes the mmap_sem as needed.
Reviewed-by: Leon Romanovsky
Reviewed-by: Christoph Hellwig
Reviewed-by: Jan Kara
Reviewed-by: Jason Gunthorpe
Rev
Commit 817be129e6f2 ("mm: validate get_user_pages_fast flags") allowed
only FOLL_WRITE and FOLL_LONGTERM to be passed to get_user_pages_fast().
This, combined with the fact that get_user_pages_fast() falls back to
"slow gup", which *does* accept FOLL_FORCE, leads to an odd situation:
if you need FO
Introduce pin_user_pages*() variations of get_user_pages*() calls,
and also pin_longterm_pages*() variations.
For now, these are placeholder calls, until the various call sites
are converted to use the correct get_user_pages*() or
pin_user_pages*() API.
These variants will eventually all set FOLL
On Thu, 12 Dec 2019, "james qian wang (Arm Technology China)"
wrote:
> On Tue, Dec 10, 2019 at 02:30:48PM +0200, Jani Nikula wrote:
>> Prefer drm_dbg_atomic().
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/drm_agpsupport.c | 4 +-
>> drivers/gpu/drm/drm_atomic.c | 187 ++
On Wed, 11 Dec 2019, Hans de Goede wrote:
> Hi Lee,
>
> On 10-12-2019 09:51, Lee Jones wrote:
> > On Tue, 19 Nov 2019, Hans de Goede wrote:
> >
> > > At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
> > > different PWM controllers for controlling the LCD's backlight brightn
From: Thomas Hellstrom
TTM graphics buffer objects may, transparently to user-space, move
between IO and system memory. When that happens, all PTEs pointing to the
old location are zapped before the move and then faulted in again if
needed. When that happens, the page protection caching mode- an
From: Thomas Hellstrom
The drm/ttm module is using a modified on-stack copy of the
struct vm_area_struct to be able to set a page protection with customized
caching. Fix that by adding a vmf_insert_mixed_prot() function similar
to the existing vmf_insert_pfn_prot() for use with drm/ttm.
I'd like
From: Thomas Hellstrom
The TTM module today uses a hack to be able to set a different page
protection than struct vm_area_struct::vm_page_prot. To be able to do
this properly, add the needed vm functionality as vmf_insert_mixed_prot().
Cc: Andrew Morton
Cc: Michal Hocko
Cc: "Matthew Wilcox (Or
On 12/12/19 9:48 AM, Thomas Hellström (VMware) wrote:
> From: Thomas Hellstrom
>
> The TTM module today uses a hack to be able to set a different page
> protection than struct vm_area_struct::vm_page_prot. To be able to do
> this properly, add the needed vm functionality as vmf_insert_mixed_prot()
From: Nickey Yang
Fix edid reading error when edid's block > 2.
Signed-off-by: Nickey Yang
Signed-off-by: Johan Jonker
---
drivers/gpu/drm/rockchip/rk3066_hdmi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c
b/drivers/gpu/drm/rockchip/rk3066_hd
On Thu 21 Nov 17:26 PST 2019, Brian Masney wrote:
> Set the two interconnect paths for the GPU to maximum speed for now to
> work towards getting the GPU working upstream. We can revisit a later
> time to optimize this for battery life.
>
> Signed-off-by: Brian Masney
Reviewed-by: Bjorn Anderss
Make komeda driver can recongise D77, D77 is arm latest display
product, compare with D71, D77 support some new features:
1. Crossbar: adjust every plane's zorder
2. ATU: Asynchronous Timewarp Unit, which is used to support VR/AR
Signed-off-by: Tiannan Zhu (Arm Technology China)
---
.../gpu/drm/
On Thu 21 Nov 17:26 PST 2019, Brian Masney wrote:
> Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core
> and must use the On Chip MEMory (OCMEM) in order to be functional.
> There's a separate interconnect path that needs to be setup to OCMEM.
> Let's document this second inte
On Thu 21 Nov 17:26 PST 2019, Brian Masney wrote:
> Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core
> and must use the On Chip MEMory (OCMEM) in order to be functional.
> There's a separate interconnect path that needs to be setup to OCMEM.
> Add support for this second pat
On Thu 21 Nov 17:26 PST 2019, Brian Masney wrote:
> Set the two interconnect paths for the GPU to maximum speed for now to
> work towards getting the GPU working upstream. We can revisit a later
> time to optimize this for battery life.
>
> Signed-off-by: Brian Masney
Reviewed-by: Bjorn Anderss
This series of patches works well on a new platform which has a panel
only controls by DPCD aux brightness.
Tested-by: AceLan Kao
--
Chia-Lin Kao(AceLan)
http://blog.acelan.idv.tw/
E-Mail: acelan.kaoATcanonical.com (s/AT/@/)
___
dri-devel mailing list
I don't have this panel, but adding the first 3 OUI bytes to the
quirk, another platform which has DPCD aux brightness control works
well.
Tested-by: AceLan Kao
--
Chia-Lin Kao(AceLan)
http://blog.acelan.idv.tw/
E-Mail: acelan.kaoATcanonical.com (s/AT/@/)
___
On 2019-12-11 12:45, claudiu.bez...@microchip.com wrote:
>
>
> On 10.12.2019 19:22, Peter Rosin wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is safe
>>
>> On 2019-12-10 15:59, claudiu.bez...@microchip.com wrote:
>>>
>>>
>>> On 10.12.2019 16:11,
* Laurent Pinchart [191202 13:05]:
> Hi Tomi,
>
> Thank you for the patch.
>
> On Thu, Nov 14, 2019 at 11:39:49AM +0200, Tomi Valkeinen wrote:
> > panel-simple now handled panel osd070t1718-19ts, and we no longer need
> > the panel timings in the DT file. So remove them.
>
> Should you in that
drm_sched_entity_init() takes drm gpu scheduler list instead of
drm_sched_rq list. This makes conversion of drm_sched_rq list
to drm gpu scheduler list unnecessary
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/amd/
drm/mediatek: return if plane pending state is disabled.
If the plane pending state is disabled, call mtk_ovl_layer_off then
return.
This guarantees that that the state is valid for all operations when the
pending state is enabled.
Suggested-by: Sean Paul
To: CK Hu
To: dri-devel@lists.freedeskt
Use the backlight support in drm_panel to simplify the driver
Signed-off-by: Jerry Han
Reviewed-by: Sam Ravnborg
---
drivers/gpu/drm/panel/panel-boe-himax8279d.c | 17 +++--
1 file changed, 3 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-boe-himax8279d.c
On 10.12.2019 19:22, Peter Rosin wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 2019-12-10 15:59, claudiu.bez...@microchip.com wrote:
>>
>>
>> On 10.12.2019 16:11, Peter Rosin wrote:
>>> On 2019-12-10 14:24, Claudiu Beznea wrote:
>>
Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a
On Thu, Dec 05, 2019 at 11:03:24AM -0500, Jerome Glisse wrote:
> > struct mmu_notifier_mm (ie the mm->mmu_notifier_mm)
> >-> mmn_mm
> > struct mm_struct
> >-> mm
> > struct mmu_notifier (ie the user subscription to the mm_struct)
> >-> mn
> > struct mmu_interval_notifier (the other ki
On 10.12.2019 22:34, Sam Ravnborg wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Cladiu
>
> On Tue, Dec 10, 2019 at 03:24:47PM +0200, Claudiu Beznea wrote:
>> This reverts commit d2c755e66617620b729041c625a6396c81d1231c.
>> ("drm:
According to VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA STANDARD
(Defines EDID Structure Version 1, Revision 4) page: 39
How to determine whether the monitor support RB timing or not?
EDID 1.4
First: read detailed timing descriptor and make sure byte 0 = 0x00,
byte 1 = 0x00, byte 2
Hi,
> -Original Message-
> From: Kishon Vijay Abraham I
> Sent: Monday, December 9, 2019 14:21
> To: Yuti Suresh Amonkar ; dri-
> de...@lists.freedesktop.org; Rob Herring
> Cc: jsa...@ti.com; tomi.valkei...@ti.com; prane...@ti.com; Milind Parab
> ; Dhananjay Vilasrao Kangude
> ; Swapnil
Yes. This is DSI command to panel.
I saw same problem in 96boards.org discuss. On Android its all ok, but on
Linux flickering.
Yes, panel in video mode. Where is pageflip event in driver? Or where add
sleep/delay between update buffer? I think buffer copy by DMA (module) to
panel. But for this ne
This series of patches works well on a new platform which has a panel
only controls by DPCD aux brightness.
Tested-by: AceLan Kao
--
Chia-Lin Kao(AceLan)
http://blog.acelan.idv.tw/
E-Mail: acelan.kaoATcanonical.com (s/AT/@/)
___
dri-devel mailing list
D77 is the next generation of D71, compared with D71, it add some new
features(components) like ATU, Crossbar, PerfCounter etc.
Crossbar is used to control every plane's zorder.
ATU (Asyncronise Timewarp Unit) is used to support and optimize VR/AR
PerfCounter is used to log device performance data
This series of patches works well on a new platform which has a panel
only controls by DPCD aux brightness.
Tested-by: AceLan Kao
--
Chia-Lin Kao(AceLan)
http://blog.acelan.idv.tw/
E-Mail: acelan.kaoATcanonical.com (s/AT/@/)
___
dri-devel mailing list
This series of patches works well on a new platform which has a panel
only controls by DPCD aux brightness.
Tested-by: AceLan Kao
--
Chia-Lin Kao(AceLan)
http://blog.acelan.idv.tw/
E-Mail: acelan.kaoATcanonical.com (s/AT/@/)
___
dri-devel mailing list
Hi Laurentiu,
thanks for the updated patch! I can confirm after intensive testing that the
hangs on boot are fixed in this version (I’m using DCSS->MIPI DSI->TI eDP
Bridge).
Best
Lukas
--
Lukas F. Hartmann, CEO
MNT Research GmbH
https://mntre.com
--
Did you know? Our Open Laptop MNT Reform
On Thu, Dec 05, 2019 at 03:03:56PM -0800, John Hubbard wrote:
> No advice, just a naming idea similar in spirit to Jerome's suggestion
> (use a longer descriptive word, and don't try to capture the entire phrase):
> use "notif" in place of the unloved "mmn". So partially, approximately like
> thi
entity should not keep copy and maintain sched list for
itself.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
>
> Hi Jerry.
>
>
> > Support Boe Himax8279d 8.0" 1200x1920 TFT LCD panel, it is a MIPI DSI
> > panel.
>
> Thanks for your persistence with this driver.
>
>
> Unfortunately the driver no longer builds after the drm_panel
> work we committed earlier this week to drm-misc-next.
>
> >
> > V9:
> > - Ad
Hi Sam,
On 10.12.2019 22:37, Sam Ravnborg wrote:
> Hi Claudiu.
>
> On Tue, Dec 10, 2019 at 03:24:45PM +0200, Claudiu Beznea wrote:
>> For HLCDC timing engine configurations bit ATMEL_HLCDC_SIP of
>> ATMEL_HLCDC_SR needs to checked if it is equal with zero before applying
>> new configuration to t
* Laurent Pinchart [191202 13:02]:
> Hi Tomi,
>
> Thank you for the patch.
>
> On Thu, Nov 14, 2019 at 11:39:48AM +0200, Tomi Valkeinen wrote:
> > The LCD panel on AM4 GP EVMs and ePOS boards seems to be
> > osd070t1718-19ts. The current dts files say osd057T0559-34ts. Possibly
> > the panel has
This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113 +
drivers/gpu/drm/amd/amdgpu/amd
Active D77's Crossbar
Crossbar(CBU) is a new component added in D77, which is used for zorder
control.
At a time (per display frame) up to 5 inputs of the CBU can be enabled
Signed-off-by: Tiannan Zhu (Arm Technology China)
---
.../arm/display/komeda/d71/d71_component.c| 61
Hi,
On Thu, Dec 12, 2019 at 01:42:12AM +0200, Laurent Pinchart wrote:
> On Wed, Dec 11, 2019 at 10:13:18PM +0100, Sam Ravnborg wrote:
> > On Wed, Dec 11, 2019 at 12:57:06AM +0200, Laurent Pinchart wrote:
> > > The dumb-vga-dac driver is a simple DRM bridge driver for simple VGA
> > > DACs that don
On 12/3/19 5:38 PM, Jani Nikula wrote:
> Now that the fbops member of struct fb_info is const, we can start
> making the ops const as well.
>
> Remove the redundant fbops assignments while at it.
>
> v2:
> - actually add const in vivid
> - fix typo (Christophe de Dinechin)
>
> Cc: Hans Verkuil
On 11/12/2019 18:53, Tony Lindgren wrote:
* Laurent Pinchart [191202 13:05]:
Hi Tomi,
Thank you for the patch.
On Thu, Nov 14, 2019 at 11:39:49AM +0200, Tomi Valkeinen wrote:
panel-simple now handled panel osd070t1718-19ts, and we no longer need
the panel timings in the DT file. So remove th
Hi Thomas.
On Thu, Dec 12, 2019 at 08:41:14AM +0100, Thomas Zimmermann wrote:
> A number of cleanups that I wanted to apply for some time. The first
> two patches simplify the public interface. The third patch adds support
> for struct drm_driver.gem_create_object. All tested by running fbdev,
> X
Hi Jerry.
On Thu, Dec 12, 2019 at 10:26:14AM +0800, Jerry Han wrote:
> Use the backlight support in drm_panel to simplify the driver
>
> Signed-off-by: Jerry Han
> Reviewed-by: Sam Ravnborg
> ---
> drivers/gpu/drm/panel/panel-boe-himax8279d.c | 17 +++--
> 1 file changed, 3 inserti
Hi Dave & Daniel,
Two important user visible fixes; GPU hang on BDW/SKL when idling
and top of screen corruption on GLK+ when FBC enabled.
Fix to Tigerlake perf/OA, HDCP commit computation touching global
state.
Then two CI spotted corner cases, race condition about context
retirement and lockde
On Thu 12-12-19 00:19:15, John Hubbard wrote:
> Add tracking of pages that were pinned via FOLL_PIN.
>
> As mentioned in the FOLL_PIN documentation, callers who effectively set
> FOLL_PIN are required to ultimately free such pages via unpin_user_page().
> The effect is similar to FOLL_GET, and may
Am 12.12.19 um 10:49 schrieb Sam Ravnborg:
> Hi Thomas.
>
> On Thu, Dec 12, 2019 at 08:41:14AM +0100, Thomas Zimmermann wrote:
>> A number of cleanups that I wanted to apply for some time. The first
>> two patches simplify the public interface. The third patch adds support
>> for struct drm_driv
On Wed, Dec 11, 2019 at 04:22:50PM -0800, Lucas De Marchi wrote:
> On Wed, Dec 11, 2019 at 12:10:41PM +0530, Bharadiya,Pankaj wrote:
> >On Tue, Dec 10, 2019 at 09:57:39PM -0800, Lucas De Marchi wrote:
> >>On Mon, Dec 09, 2019 at 08:09:02PM +0530, Pankaj Bharadiya wrote:
> >>>intel_bw_state allocate
The "num_dtd" variable is the number of elements in the
generic_dtd->dtd[] array so the > needs to be >= to prevent reading one
element beyond the end of the array.
Fixes: 33ef6d4fd8df ("drm/i915/vbt: Handle generic DTD block")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/i915/display/intel_
Hi all,
n commit
64d17f25dcad ("drm/nouveau: Fix drm-core using atomic code-paths on pre-nv50
hardware")
Fixes tag
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1706557
has these problem(s):
- No SHA1 recognised
I haven't seen a Fixes tag with a bug URL before, they usually refer
On 12/11/19 5:08 PM, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 10:48:42AM +0100, Johan Korsnes wrote:
>> When logging the AVI InfoFrame, clearly indicate whether or not
>> attributes are active/"in effect". The specification is given in
>> CTA-861-G Section 6.4: Format of Version 2, 3 & 4 AVI
On Thu, Dec 12, 2019 at 09:52:22AM +0100, Ulf Hansson wrote:
> On Mon, 9 Dec 2019 at 14:03, Thierry Reding wrote:
> >
> > From: Thierry Reding
> >
> > The Tegra DRM driver heavily relies on the implementations for runtime
> > suspend/resume to be called at specific times. Unfortunately, there are
Hi,
On 12-12-2019 12:52, Stephen Rothwell wrote:
Hi all,
n commit
64d17f25dcad ("drm/nouveau: Fix drm-core using atomic code-paths on pre-nv50
hardware")
Fixes tag
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1706557
has these problem(s):
- No SHA1 recognised
I haven't see
v2: also check src rect (Chia-I Wu).
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/virtio/virtgpu_plane.c | 35 +++---
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_plane.c
b/drivers/gpu/drm/virtio/virtgpu_plane.c
index bc4
v2: fix src rect handling (Chia-I Wu).
Gerd Hoffmann (3):
drm/virtio: skip set_scanout if framebuffer didn't change
virtio-gpu: batch display update commands.
virtio-gpu: use damage info for display updates.
drivers/gpu/drm/virtio/virtgpu_drv.h | 6 ++
drivers/gpu/drm/virtio/virtgpu_pla
When the driver submits multiple commands in a row it makes sense to
notify the host only after submitting the last one, so the host can
process them all at once, with a single vmexit.
Add functions to enable/disable notifications to allow that. Use the
new functions for primary plane updates.
S
v2: remove shift by src_{x,y}, drm_atomic_helper_damage_merged()
handles that for us (Chia-I Wu).
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/virtio/virtgpu_plane.c | 41 +++---
1 file changed, 24 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/virtio/vi
Hi
Please can amdgpu/raven_ta.bin be published somewhere
Thanks
Mike
On Wed, 11 Dec 2019 at 22:30, Alex Deucher wrote:
>
> Hi Dave, Daniel,
>
> Kicking off 5.6 with new stuff from AMD. There is a UAPI addition. We
> added a new firmware for display, and this just adds the version query
> to
Hi,
Missatge de CK Hu del dia dj., 26 de set. 2019 a les 10:51:
>
> Hi, Jitao:
>
> On Thu, 2019-09-19 at 14:58 +0800, Jitao Shi wrote:
> > Change the method of frame rate calc which can get more accurate
> > frame rate.
> >
> > data rate = pixel_clock * bit_per_pixel / lanes
> > Adjust hfp_wc to
Hi Dave and Daniel,
I realized there were a few leftovers from -next-fixes which should find
their way to drm-fixes.
Sean
drm-misc-next-fixes-2019-12-12:
-mgag200: more startadd mitigation (Thomas)
-panfrost: devfreq fix + several memory fixes (Steven, Boris)
Cc: Boris Brezillon
Cc: Steven P
On 03/12/2019 12:16, Yuti Amonkar wrote:
> Document the bindings used for the Cadence MHDP DPI/DP bridge in
> yaml format.
>
> Signed-off-by: Yuti Amonkar
Couple of comments bellow.
> ---
> .../bindings/display/bridge/cdns,mhdp.yaml | 101
> +
> 1 file changed, 101
On Wed, Dec 11, 2019 at 11:45 PM CK Hu wrote:
>
> Hi, Mark:
>
> On Wed, 2019-12-11 at 10:49 -0500, Mark Yacoub wrote:
> > drm/mediatek: return if plane pending state is disabled.
> >
> > If the plane pending state is disabled, call mtk_ovl_layer_off then
> > return.
> > This guarantees that that t
Hi,
On 12-12-2019 09:45, Lee Jones wrote:
On Wed, 11 Dec 2019, Hans de Goede wrote:
Hi Lee,
On 10-12-2019 09:51, Lee Jones wrote:
On Tue, 19 Nov 2019, Hans de Goede wrote:
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the L
https://bugzilla.kernel.org/show_bug.cgi?id=204241
--- Comment #46 from Alex Deucher (alexdeuc...@gmail.com) ---
Can you bisect? It sounds like you may be experiencing a different issue.
--
You are receiving this mail because:
You are watching the assignee of the bug.
__
>-Original Message-
>From: dri-devel On Behalf Of
>Gerd Hoffmann
>Sent: Tuesday, December 10, 2019 3:58 AM
>To: dri-devel@lists.freedesktop.org
>Cc: David Airlie ; open list ;
>open list:VIRTIO GPU DRIVER ;
>Gerd Hoffmann ; gurchetansi...@chromium.org
>Subject: [PATCH] drm/virtio: fix mmap
On 12/11/19 11:04 PM, Ma, Le wrote:
[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: Andrey Grodzovsky
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-devel@lists.freedesktop.org; amd-...@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le
; Zhang, Ha
On 12/11/19 11:05 PM, Ma, Le wrote:
[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: Andrey Grodzovsky
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-devel@lists.freedesktop.org; amd-...@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le
; Zhang, Ha
On Thu, 12 Dec 2019, Hans de Goede wrote:
> Hi,
>
> On 12-12-2019 09:45, Lee Jones wrote:
> > On Wed, 11 Dec 2019, Hans de Goede wrote:
> >
> > > Hi Lee,
> > >
> > > On 10-12-2019 09:51, Lee Jones wrote:
> > > > On Tue, 19 Nov 2019, Hans de Goede wrote:
> > > >
> > > > > At least Bay Trail (BY
This patch adds a new DRM driver for Texas Instruments DSS IPs used on
Texas Instruments Keystone K2G, AM65x, and J721e SoCs. The new DSS IP is
a major change to the older DSS IP versions, which are supported by
the omapdrm driver. While on higher level the Keystone DSS resembles
the older DSS vers
Changes since v2:
- Add version history to commit messages
- Fix yaml bindings now that got dt_binding_check dtbs_check working propery
- Move tidss entry in MAINTAINERS after omapdrm and add "T: git
git://anongit.freedesktop.org/drm/drm-misc"
Changes since the first version of the patch series
Add dt-schema yaml bindig for K2G DSS, an ultra-light version of TI
Keystone Display SubSystem.
Version history:
v2: no change
v3: - Add ports node
- Add includes to dts example
- reindent dts example
Signed-off-by: Jyri Sarha
---
.../bindings/display/ti/ti,k2g-dss.yaml | 118 ++
On 12/3/19 12:26 PM, John Stultz wrote:
> This patch adds system heap to the dma-buf heaps framework.
>
> This allows applications to get a page-allocator backed dma-buf
> for non-contiguous memory.
>
> This code is an evolution of the Android ION implementation, so
> thanks to its original autho
On Thu, Dec 12, 2019 at 2:32 PM Ulf Hansson wrote:
>
> On Thu, 12 Dec 2019 at 13:33, Thierry Reding wrote:
> >
> > On Thu, Dec 12, 2019 at 09:52:22AM +0100, Ulf Hansson wrote:
> > > On Mon, 9 Dec 2019 at 14:03, Thierry Reding
> > > wrote:
> > > >
> > > > From: Thierry Reding
> > > >
> > > > Th
1 - 100 of 156 matches
Mail list logo
