Hi Laurent,
On Sat, May 11, 2019 at 11:07 PM Laurent Pinchart
wrote:
> On the receiving side, the THC63LVD1024 LVDS-to-parallel bridge has two
> LVDS inputs and two parallel outputs. It can operate in four different
> modes:
>
> - Single-in, single-out: The first LVDS input receives the video str
Hi Laurent,
On Sat, May 11, 2019 at 11:07 PM Laurent Pinchart
wrote:
> The THC63LVD1024 LVDS decoder can operate in two modes, single-link or
> dual-link. In dual-link mode both input ports are used to carry even-
> and odd-numbered pixels separately. Document this in the DT bindings,
> along wit
https://bugs.freedesktop.org/show_bug.cgi?id=102646
--- Comment #87 from tempel.jul...@gmail.com ---
Applying the patch to 5.0, 5.1 and drm-next-5.2-wip fails with
patching file drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
Hunk #5 FAILED at 3943.
Hunk #6 succeeded at 3951 (offset -7 lines).
H
Hi Geert,
On Sun, May 12, 2019 at 10:55:20AM +0200, Geert Uytterhoeven wrote:
> On Sat, May 11, 2019 at 11:07 PM Laurent Pinchart wrote:
> > On the receiving side, the THC63LVD1024 LVDS-to-parallel bridge has two
> > LVDS inputs and two parallel outputs. It can operate in four different
> > modes:
Hi Geert,
On Sun, May 12, 2019 at 10:58:54AM +0200, Geert Uytterhoeven wrote:
> On Sat, May 11, 2019 at 11:07 PM Laurent Pinchart wrote:
> > The THC63LVD1024 LVDS decoder can operate in two modes, single-link or
> > dual-link. In dual-link mode both input ports are used to carry even-
> > and odd-
Add support for the MIXEL DPHY IP as found on NXP's i.MX8MQ SoCs.
Signed-off-by: Guido Günther
Reviewed-by: Sam Ravnborg
Reviewed-by: Rob Herring
Reviewed-by: Fabio Estevam
---
.../bindings/phy/mixel,mipi-dsi-phy.txt | 29 +++
1 file changed, 29 insertions(+)
create mod
This adds initial support for the Mixel IP based mipi dphy as found on i.MX8
processors. It has support for the i.MX8MQ, support for other variants can be
added - once the platform specific parts are in - via the provided devdata.
The driver is somewhat based on what's found in NXPs BSP.
Public d
This adds support for the Mixel DPHY as found on i.MX8 CPUs but since
this is an IP core it will likely be found on others in the future. So
instead of adding this to the nwl host driver make it a generic PHY
driver.
The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be
added on
On Wed, 01 May 2019 10:12:42 -0700
Eric Anholt wrote:
> Boris Brezillon writes:
>
> > +Rob, Eric, Mark and more
> >
> > Hi,
> >
> > On Fri, 5 Apr 2019 16:20:45 +0100
> > Steven Price wrote:
> >
> >> On 04/04/2019 16:20, Boris Brezillon wrote:
> >> > Hello,
> >> >
> >> > This patch adds ne
Hi Kieran,
Thank you for the patch.
On Fri, Mar 15, 2019 at 05:01:06PM +, Kieran Bingham wrote:
> Provide helpers to manage the power state, and initial configuration of
> the CRTC.
I would add a sentence here to mention that these helpers operate from
the atomic commit tail handler, and res
Hi Kieran,
Thank you for the patch.
On Fri, Mar 15, 2019 at 05:01:07PM +, Kieran Bingham wrote:
> Provide helpers to allow CRTC configuration to be separated from the power
> state handling. rcar_du_crtc_atomic_post_commit() is a no-op, but maintained
> for API symmetry.
Do you think we will
On Sat, 11 May 2019 15:32:20 -0700
Alyssa Rosenzweig wrote:
> Hi all,
>
> As Steven Price explained, the "GPU top" kbase approach is often more
> useful and accurate than per-draw timing.
>
> For a 3D game inside a GPU-accelerated desktop, the games' counters
> *should* include desktop overhea
On Tue, 30 Apr 2019 09:49:51 -0600
Jordan Crouse wrote:
> On Tue, Apr 30, 2019 at 06:10:53AM -0700, Rob Clark wrote:
> > On Tue, Apr 30, 2019 at 5:42 AM Boris Brezillon
> > wrote:
> > >
> > > +Rob, Eric, Mark and more
> > >
> > > Hi,
> > >
> > > On Fri, 5 Apr 2019 16:20:45 +0100
> > > Steven P
Hi Kieran,
Thank you for the patch?
On Fri, Mar 15, 2019 at 05:01:08PM +, Kieran Bingham wrote:
> Refactoring of the group control code will soon require more iteration
> over the available groups. Simplify this process by introducing a group
> iteration helper.
>
> Signed-off-by: Kieran Bin
Hi Kieran,
Thank you for the patch.
On Fri, Mar 15, 2019 at 05:01:09PM +, Kieran Bingham wrote:
> Create a new private state object for the DU groups, and move the
> initialisation of a group object to a new function rcar_du_group_init().
>
> Signed-off-by: Kieran Bingham
> ---
> v2:
> - N
Hi Kieran,
Thank you for the patch.
On Fri, Mar 15, 2019 at 05:01:10PM +, Kieran Bingham wrote:
> The group can now be handled independently from the CRTC tracking its
> own state.
>
> Introduce an rcar_du_group_atomic_check() call which will iterate the
> CRTCs to determine the per-state us
Hi Sean,
In the subject line, s/-/)/
On Wed, May 08, 2019 at 06:33:27PM +0200, Daniel Vetter wrote:
> On Wed, May 08, 2019 at 12:09:07PM -0400, Sean Paul wrote:
> > From: Laurent Pinchart
> >
> > Add functions to the atomic core to retrieve the old and new connectors
> > associated with an enco
Unlike Linux the OpenBSD primary "drm" device name is substring of the
"drmR" render node device name and strncmp() tests resulted in render
nodes being flagged as primary nodes.
Signed-off-by: Jonathan Gray
---
xf86drm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
drm render nodes have the same major as drm primary devices but offset
the minor by a base of 128.
I expected the name of the device to have numbering starting at 0 when
these non-linux codepaths were added (before OpenBSD had render nodes).
Signed-off-by: Jonathan Gray
---
xf86drm.c | 24 +
Hi Ville,
On Fri, May 10, 2019 at 07:00:31PM +0300, Ville Syrjälä wrote:
> On Fri, May 10, 2019 at 01:08:49PM +0200, Maxime Ripard wrote:
> > So far, the drm_format_plane_cpp function was operating on the format's
> > fourcc and was doing a lookup to retrieve the drm_format_info structure and
> >
From: Clément Péron
Enable and add supply to the Mali GPU node on the
Orange Pi 3 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
b/ar
From: Clément Péron
Add the mali gpu node to the H6 device-tree.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50
From: Neil Armstrong
The Amlogic ARM Mali Midgard requires reset controls to power on and
software reset the GPU, adds these as optional in the bindings.
Signed-off-by: Neil Armstrong
Reviewed-by: Rob Herring
Signed-off-by: Kevin Hilman
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt
From: Clément Péron
Enable and add supply to the Mali GPU node on the
Beelink GS1 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
b/
From: Clément Péron
This add the H6 mali compatible in the dt-bindings to later support
specific implementation.
Signed-off-by: Clément Péron
Reviewed-by: Rob Herring
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
di
From: Icenowy Zheng
Some SoCs adds a bus clock gate to the Mali Midgard GPU.
Add the binding for the bus clock.
Signed-off-by: Icenowy Zheng
Signed-off-by: Clément Péron
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++
1 file changed, 6 ins
From: Clément Péron
Hi,
The Allwinner H6 has a Mali-T720 MP2. The drivers are
out-of-tree so this series only introduce the dt-bindings.
The first patch is from Neil Amstrong and has been already
merged in linux-amlogic. It is required for this series.
The second patch is from Icenowy Zheng wh
From: Clément Péron
Enable and add supply to the Mali GPU node on the
Pine H64 board.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm6
From: Clément Péron
Enable and add supply to the Mali GPU node on the
Orange Pi One Plus and Lite2 boards.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-ora
On Sun, May 12, 2019 at 11:16 PM wrote:
>
> From: Clément Péron
>
> Enable and add supply to the Mali GPU node on the
> Pine H64 board.
>
> Signed-off-by: Clément Péron
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arc
Loop N1 instruction delay for burst mode devices are computed
based on horizontal sync and porch timing values.
The current driver is using u16 type for computing this hsync_porch
value, which would failed to fit within the u16 type for large sync
and porch timings devices. This would result in hs
Some DSI panels do use GENERIC_SHORT_WRITE_2 transfer protocol to host
DSI driver and which is similar to GENERIC_SHORT_WRITE.
Add support for the same transfer, so-that so-that the panels which are
requesting similar transfer type will process properly.
Signed-off-by: Jagan Teki
Tested-by: Merl
This is v10 for the previous series[1] and few pathes are dropped
as part of this series since it would require separate rework same
will send in separately or another series.
Changes for v10:
- rebased on linux-next
- dropped few patches
- add 150 multiplication on hsync_porch
Changes for v9:
- r
Vertical front and back porch values on existing driver are swapped.
The existing timings are still working as expected, but to make sure
it can compatible with techstar ts8550b bsp timings this patch swap
the same values.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/panel/panel-sitronix-st770
On 2019-05-08 20:38, Uma Shankar wrote:
> This patch series enables HDR support in drm. It basically defines
> HDR metadata structures, property to pass content (after blending)
> metadata from user space compositors to driver.
>
> Dynamic Range and Mastering infoframe creation and sending.
>
> ToD
https://bugs.freedesktop.org/show_bug.cgi?id=109692
--- Comment #42 from mikhail.v.gavri...@gmail.com ---
Andrey, could you look on another GPU reset issue?
[18735.255511] sony 0003:054C:09CC.0008: input,hidraw4: USB HID v81.11 Gamepad
[Sony Interactive Entertainment Wireless Controller] on
usb-0
https://bugs.freedesktop.org/show_bug.cgi?id=109692
--- Comment #43 from mikhail.v.gavri...@gmail.com ---
Created attachment 144242
--> https://bugs.freedesktop.org/attachment.cgi?id=144242&action=edit
dmesg of another GPU reset issue
--
You are receiving this mail because:
You are the assigne
https://bugs.freedesktop.org/show_bug.cgi?id=102646
--- Comment #88 from bmil...@gmail.com ---
(In reply to tempel.julian from comment #87)
> Applying the patch to 5.0, 5.1 and drm-next-5.2-wip fails with
>
> patching file drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> Hunk #5 FAILED at 3943.
https://bugs.freedesktop.org/show_bug.cgi?id=108487
--- Comment #18 from Alex Villacís Lasso ---
Created attachment 144243
--> https://bugs.freedesktop.org/attachment.cgi?id=144243&action=edit
gbm: gbm_bo_get_handle_for_plane fallback to nonplanar handle
Here is a patch for Mesa 19.0.3 that fi
Acked-by: Prike Liang
-Original Message-
From: Chunming Zhou
Sent: Tuesday, May 07, 2019 7:46 PM
To: Koenig, Christian ; Liang, Prike
; dri-devel@lists.freedesktop.org
Cc: Zhou, David(ChunMing)
Subject: [PATCH 2/2] drm/amd/display: use ttm_eu_reserve_buffers instead of
amdgpu_bo_res
I have verified this solution again and the Abaqus case finished after about 27
hours running .
But not sure whether retrieve the first busy BO and then retry evict the LRU
BOs result in
Abaqus poor performance .
Anyway this can fix the age-old issue .Does any other concern before push the
foll
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