This is a patch set from Christoph Hellwig. Patch 2 has been updated by
me to not remove checks for TTM coherent pool presence. Ideally, we
should query TTM for this instead and I'll have a patch set intended for
5.1 so that we can do that. But I don't want to introduce cross-module API
additions o
From: Christoph Hellwig
Just use a simple if/else chain to select the DMA mode.
Signed-off-by: Christoph Hellwig
---
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 25 ++---
1 file changed, 6 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
b/drivers
From: Christoph Hellwig
Since Linux 4.21 we merged the swiotlb ops into the DMA direct ops,
so they would always have a the sync_single methods. But late in
the cicle we also removed the direct ops entirely, so we'd see NULL
DMA ops. Switch vmw_dma_select_mode to only detect swiotlb presence
us
From: Christoph Hellwig
intel_iommu_enabled is defined as always false for !CONFIG_INTEL_IOMMU,
so remove the ifdefs around it.
Signed-off-by: Christoph Hellwig
Reviewed-by: Thomas Hellstrom
---
v2: Retain the check for TTM dma page pool presence.
---
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 21
From: Christoph Hellwig
The driver depends on CONFIG_X86 so these are dead code.
Signed-off-by: Christoph Hellwig
---
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 25
https://bugs.freedesktop.org/show_bug.cgi?id=105733
--- Comment #62 from l...@protonmail.ch ---
What changes happened in 5.0rc3 that could have fixed this? I will try to see
if I still experience problems with 5.0rc3 when I can check.
Also, can you elaborate on what you mean by draining the built
On Thu, Jan 24, 2019 at 06:45:52PM +0100, Sam Ravnborg wrote:
> Hi Daniel.
>
> On Thu, Jan 24, 2019 at 05:58:11PM +0100, Daniel Vetter wrote:
> > The fbdev emulation helpers pretty much assume that this is set.
> > Let's do it for everyone.
>
> I do not know this code at all.
> But I failed to fo
On Thu, Jan 24, 2019 at 06:40:52PM +0100, Noralf Trønnes wrote:
>
>
> Den 24.01.2019 17.58, skrev Daniel Vetter:
> > The fbdev split between fix and var information is kinda
> > pointless for drm drivers since everything is fixed: The fbdev
> > emulation doesn't support changing modes at all.
> >
On Thu, Jan 24, 2019 at 05:58:29PM +0100, Daniel Vetter wrote:
> This should not result in any changes.
>
> v2: Rebase over vbox changes - vbox gained it's own line to fill
> fix.id.
>
> Signed-off-by: Daniel Vetter
> Cc: Greg Kroah-Hartman
> Cc: Hans de Goede
> Cc: Daniel Vetter
> Cc: Alexan
On Thu, Jan 24, 2019 at 07:00:11PM +0100, Sam Ravnborg wrote:
> Hi Daniel.
>
> On Thu, Jan 24, 2019 at 05:58:14PM +0100, Daniel Vetter wrote:
> > Should not result in any changes.
> >
> > Signed-off-by: Daniel Vetter
> > Cc: Dave Airlie
> > Cc: Junwei Zhang
> > Cc: Alex Deucher
> > Cc: "Chris
On Fri, Jan 25, 2019 at 07:39:26AM +0100, Gerd Hoffmann wrote:
> On Thu, Jan 24, 2019 at 05:58:24PM +0100, Daniel Vetter wrote:
> > This should not result in any changes.
>
> I'd love to merge https://patchwork.freedesktop.org/series/53951/
> instead (which will -- among other things -- switch qxl
On 24.1.2019 23.53, Dmitry Osipenko wrote:
24.01.2019 21:02, Thierry Reding пишет:
From: Thierry Reding
Tegra186 and later are different from earlier generations in that they
use an ARM SMMU rather than the Tegra SMMU. The ARM SMMU driver behaves
slightly differently in that the geometry for I
On 24.1.2019 20.02, Thierry Reding wrote:
From: Thierry Reding
Tegra186 and later support 40 bits of address space. Additional
registers need to be programmed to store the full 40 bits of push
buffer addresses.
Since command stream gathers can also reside in buffers in a 40-bit
address space,
instead of relying on intel_iommu_enabled, use the fact that the
dma_map:ops::map_page != dma_direct_map_page.
Signed-off-by: Thomas Hellstrom
---
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vmwgfx/
On Fri, Jan 25, 2019 at 11:13:41AM +0200, Mikko Perttunen wrote:
> On 24.1.2019 20.02, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Tegra186 and later support 40 bits of address space. Additional
> > registers need to be programmed to store the full 40 bits of push
> > buffer addresses.
On Fri, Jan 25, 2019 at 12:38:01AM +0300, Dmitry Osipenko wrote:
> 24.01.2019 21:02, Thierry Reding пишет:
> > From: Thierry Reding
> >
> > Tegra186 and later are different from earlier generations in that they
> > use an ARM SMMU rather than the Tegra SMMU. The ARM SMMU driver behaves
> > slight
On 25.1.2019 11.32, Mikko Perttunen wrote:
On 25.1.2019 11.20, Thierry Reding wrote:
On Fri, Jan 25, 2019 at 11:13:41AM +0200, Mikko Perttunen wrote:
On 24.1.2019 20.02, Thierry Reding wrote:
From: Thierry Reding
Tegra186 and later support 40 bits of address space. Additional
registers nee
On 25.1.2019 11.20, Thierry Reding wrote:
On Fri, Jan 25, 2019 at 11:13:41AM +0200, Mikko Perttunen wrote:
On 24.1.2019 20.02, Thierry Reding wrote:
From: Thierry Reding
Tegra186 and later support 40 bits of address space. Additional
registers need to be programmed to store the full 40 bits
On Thu, Jan 24, 2019 at 06:38:33PM +0100, Sam Ravnborg wrote:
> Hi Daniel.
>
> > +
> > + /**
> > +* @DRIVER_HAVE_DMA:
> > +*
> > +* Driver supports DMA, the userspace DMA API will be supported. Only
> > +* for legacy drivers. Do not use.
> > +*/
> > + DRIVER_HAVE_DMA
Hi,
This series adds support for programming the SPD and vendor infoframes.
It also adds support for pixel repeated modes - we were not rejecting
these modes, but we also didn't have the implementation to support
them. As their implementation is simple, add it rather than rejecting
the modes.
S
On Fri, Jan 25, 2019 at 11:23:03AM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This series enables the display pipeline on the Allwinner A23 SoC.
> A few fixes are included for corner cases when the frontend isn't
> enabled.
>
> The A23 display pipeline is very much the same as the A33, except
Den 25.01.2019 09.48, skrev Daniel Vetter:
> On Thu, Jan 24, 2019 at 06:40:52PM +0100, Noralf Trønnes wrote:
>>
>>
>> Den 24.01.2019 17.58, skrev Daniel Vetter:
>>> The fbdev split between fix and var information is kinda
>>> pointless for drm drivers since everything is fixed: The fbdev
>>> emul
From: Thierry Reding
The SOR has a crossbar that can map each lane of the SOR to each of the
SOR pads. The mapping is usually the same across designs for a specific
SoC generation, but every now and then there's a design that doesn't.
Allow the crossbar configuration to be specified in device tr
From: Thierry Reding
The crossbar configuration is usually the same across all designs for a
given SoC generation. But sometimes there are designs that require some
other configuration.
Implement support for parsing the crossbar configuration from a device
tree. If the crossbar configuration is
On Wednesday, January 23, 2019 6:04 AM, Kees Cook wrote
>
> Variables declared in a switch statement before any case statements
> cannot be initialized, so move all instances out of the switches.
> After this, future always-initialized stack variables will work
> and not throw warnings like this:
The DRM driver stack is designed to work with cache coherent devices
only, but permits an optimization to be enabled in some cases, where
for some buffers, both the CPU and the GPU use uncached mappings,
removing the need for DMA snooping and allocation in the CPU caches.
The use of uncached GPU m
On Thu, 24 Jan 2019 at 13:31, Koenig, Christian
wrote:
>
> Am 24.01.19 um 13:06 schrieb Ard Biesheuvel:
> > The DRM driver stack is designed to work with cache coherent devices
> > only, but permits an optimization to be enabled in some cases, where
> > for some buffers, both the CPU and the GPU u
On Thu, 24 Jan 2019 at 15:01, Alex Deucher wrote:
>
> On Thu, Jan 24, 2019 at 9:00 AM Ard Biesheuvel
> wrote:
> >
> > On Thu, 24 Jan 2019 at 13:31, Koenig, Christian
> > wrote:
> > >
> > > Am 24.01.19 um 13:06 schrieb Ard Biesheuvel:
> > > > The DRM driver stack is designed to work with cache co
On Thu, 24 Jan 2019 at 10:45, Koenig, Christian
wrote:
>
> Am 24.01.19 um 10:28 schrieb Ard Biesheuvel:
> > On Thu, 24 Jan 2019 at 10:25, Koenig, Christian
> > wrote:
> >> Am 24.01.19 um 10:13 schrieb Christoph Hellwig:
> >>> On Wed, Jan 23, 2019 at 05:52:50PM +0100, Ard Biesheuvel wrote:
>
On Thu, 24 Jan 2019 at 12:37, Koenig, Christian
wrote:
>
> Am 24.01.19 um 12:26 schrieb Ard Biesheuvel:
> > On Thu, 24 Jan 2019 at 12:23, Koenig, Christian
> > wrote:
> >> Am 24.01.19 um 10:59 schrieb Ard Biesheuvel:
> >>> [SNIP]
> >>> This is *exactly* my point the whole time.
> >>>
> >>> The cu
24.01.2019 21:02, Thierry Reding пишет:
> From: Thierry Reding
>
> Tegra186 and later are different from earlier generations in that they
> use an ARM SMMU rather than the Tegra SMMU. The ARM SMMU driver behaves
> slightly differently in that the geometry for IOMMU domains is set only
> after a d
This adds initial support for the Mixel IP based mipi dphy as found on i.MX8
processors. It has support for the i.MX8MQ, support for other variants can be
added - once the necessary parts are in - via the provided hooks.
The driver is somewhat based on what's found in NXPs BSP.
Documentation on t
commit d6abe6df706c (drm/bridge: sil_sii8620: do not have a dependency
of RC_CORE) changed the driver to select both RC_CORE and INPUT.
However, this causes problems with other drivers, in particular an input
driver that depends on MFD_INTEL_LPSS_PCI (to be added in a separate
commit):
drivers/c
On Thu, 24 Jan 2019 at 10:31, Michel Dänzer wrote:
>
> On 2019-01-23 5:52 p.m., Ard Biesheuvel wrote:
> > On Wed, 23 Jan 2019 at 17:44, Christoph Hellwig wrote:
> >>
> >> I think we just want a driver-local check for those combinations
> >> where we know this hack actually works, which really jus
Dear CK,
OK,I will modify according your comments in V3.
Best Regards
Wangyan Wang
On Thu, 2019-01-24 at 14:17 +0800, CK Hu wrote:
> On Fri, 2019-01-18 at 20:59 +0800, Wangyan Wang wrote:
> > From: chunhui dai
>
> Describe something here.
>
> >
> > Fixes: 0fc721b2968e ("drm/mediatek:
Signed-off-by: Guido Günther
---
.../bindings/phy/mixel,mipi-dsi-phy.txt | 29 +++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
b/
Hello, Julien!
Sorry for the late reply - it took quite some time to collect the data
requested.
On 1/22/19 1:44 PM, Julien Grall wrote:
>
>
> On 1/22/19 10:28 AM, Oleksandr Andrushchenko wrote:
>> Hello, Julien!
>
> Hi,
>
>> On 1/21/19 7:09 PM, Julien Grall wrote:
>> Well, I didn't get the attri
24.01.2019 21:02, Thierry Reding пишет:
> From: Thierry Reding
>
> Tegra186 and later are different from earlier generations in that they
> use an ARM SMMU rather than the Tegra SMMU. The ARM SMMU driver behaves
> slightly differently in that the geometry for IOMMU domains is set only
> after a d
On 24/01/2019 14:34, Oleksandr Andrushchenko wrote:
Hello, Julien!
Hi,
On 1/22/19 1:44 PM, Julien Grall wrote:
On 1/22/19 10:28 AM, Oleksandr Andrushchenko wrote:
Hello, Julien!
Hi,
On 1/21/19 7:09 PM, Julien Grall wrote:
Well, I didn't get the attributes of pages at the backend sid
On Thu, Jan 24, 2019 at 04:52:59PM -0800, ndesaulni...@google.com wrote:
> arch/x86/Makefile disables SSE and SSE2 for the whole kernel. The
> AMDGPU drivers modified in this patch re-enable SSE but not SSE2. Turn
> on SSE2 to support emitting double precision floating point instructions
> rather
This adds support for the Mixel DPHY as found on i.MX8 CPUs but since
this is an IP core it will likely be found on others in the future. So
instead of adding this to the nwl host driver make it a generic PHY
driver.
The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be
added on
On Fri, Jan 25, 2019 at 12:13:13AM +0530, Jagan Teki wrote:
> Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
>
> Add panel driver for it.
>
> Signed-off-by: Jagan Teki
Tested-by: Bhushan Shah
--
Bhushan Shah
http://blog.bshah.in
IRC Nick : bshah on Freenode
GPG key fingerpr
On Thu, 24 Jan 2019 at 12:23, Koenig, Christian
wrote:
>
> Am 24.01.19 um 10:59 schrieb Ard Biesheuvel:
> > [SNIP]
> > This is *exactly* my point the whole time.
> >
> > The current code has
> >
> > static inline bool drm_arch_can_wc_memory(void)
> > {
> > #if defined(CONFIG_PPC) && !defined(CONFI
arch/x86/Makefile disables SSE and SSE2 for the whole kernel. The
AMDGPU drivers modified in this patch re-enable SSE but not SSE2. Turn
on SSE2 to support emitting double precision floating point instructions
rather than calls to non-existent (usually available from gcc_s or
compiler_rt) floatin
On Thu, 24 Jan 2019 at 10:25, Koenig, Christian
wrote:
>
> Am 24.01.19 um 10:13 schrieb Christoph Hellwig:
> > On Wed, Jan 23, 2019 at 05:52:50PM +0100, Ard Biesheuvel wrote:
> >> But my concern is that it seems likely that non-cache coherent
> >> implementations are relying on this hack as well.
On Fri, Jan 25, 2019 at 10:46 AM Noralf Trønnes wrote:
>
>
>
> Den 25.01.2019 09.48, skrev Daniel Vetter:
> > On Thu, Jan 24, 2019 at 06:40:52PM +0100, Noralf Trønnes wrote:
> >>
> >>
> >> Den 24.01.2019 17.58, skrev Daniel Vetter:
> >>> The fbdev split between fix and var information is kinda
> >
24.01.2019 13:24, Mikko Perttunen пишет:
> On 23.1.2019 21.42, Dmitry Osipenko wrote:
>> 23.01.2019 18:55, Dmitry Osipenko пишет:
>>> 23.01.2019 17:04, Thierry Reding пишет:
On Wed, Jan 23, 2019 at 04:41:44PM +0300, Dmitry Osipenko wrote:
> 23.01.2019 12:39, Thierry Reding пишет:
>> Fr
24.01.2019 16:27, Mikko Perttunen пишет:
> On 24.1.2019 15.15, Dmitry Osipenko wrote:
>> 24.01.2019 13:24, Mikko Perttunen пишет:
>>> On 23.1.2019 21.42, Dmitry Osipenko wrote:
23.01.2019 18:55, Dmitry Osipenko пишет:
> 23.01.2019 17:04, Thierry Reding пишет:
>> On Wed, Jan 23, 2019 at
On Thu, 24 Jan 2019 at 14:54, Alex Deucher wrote:
>
> On Thu, Jan 24, 2019 at 6:45 AM Ard Biesheuvel
> wrote:
> >
> > On Thu, 24 Jan 2019 at 12:37, Koenig, Christian
> > wrote:
> > >
> > > Am 24.01.19 um 12:26 schrieb Ard Biesheuvel:
> > > > On Thu, 24 Jan 2019 at 12:23, Koenig, Christian
> > >
Hi Daniel.
On Thu, Jan 24, 2019 at 05:58:06PM +0100, Daniel Vetter wrote:
> If a non-legacy driver calls these it's valid to assume there is
> interrupt support. The flag is really only needed for legacy drivers.
>
> Also remove all the flag usage from non-legacy drivers.
>
> Signed-off-by: Dani
The function ttm_bo_put releases a reference to a TTM buffer object. The
function's name is more aligned to the Linux kernel convention of naming
ref-counting function _get and _put.
A call to ttm_bo_unref takes the address of the TTM BO object's pointer and
clears the pointer's value to NULL. Thi
This patchset cleans up the last remaining callers of ttm_bo_reference
and ttm_bo_unref. Calls are replaced with ttm_bo_get and ttm_bo_put,
which follow Linux' get/put semantics more closely.
The most notable difference is that ttm_bo_get does not clear the supplied
pointer's value. This behaviou
The function ttm_bo_put releases a reference to a TTM buffer object. The
function's name is more aligned to the Linux kernel convention of naming
ref-counting function _get and _put.
A call to ttm_bo_unref takes the address of the TTM BO object's pointer and
clears the pointer's value to NULL. Thi
The function ttm_bo_put releases a reference to a TTM buffer object. The
function's name is more aligned to the Linux kernel convention of naming
ref-counting function _get and _put.
A call to ttm_bo_unref takes the address of the TTM BO object's pointer and
clears the pointer's value to NULL. Thi
Both functions are obsolete and all calls have been replaced by
ttm_bo_get and ttm_bo_put.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ttm/ttm_bo.c | 9 -
include/drm/ttm/ttm_bo_api.h | 28
2 files changed, 37 deletions(-)
diff --git a/drivers/gpu/
The function ttm_bo_put releases a reference to a TTM buffer object. The
function's name is more aligned to the Linux kernel convention of naming
ref-counting function _get and _put.
A call to ttm_bo_unref takes the address of the TTM BO object's pointer and
clears the pointer's value to NULL. Thi
The function ttm_bo_get acquires a reference on a TTM buffer object. The
function's name is more aligned to the Linux kernel convention of naming
ref-counting function _get and _put.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 5 +++--
drivers/gpu/drm/vmwgfx/v
The function ttm_bo_get acquires a reference on a TTM buffer object. The
function's name is more aligned to the Linux kernel convention of naming
ref-counting function _get and _put.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/nouveau/nouveau_bo.h | 7 ++-
1 file changed, 6 insertio
https://bugs.freedesktop.org/show_bug.cgi?id=109456
Bug ID: 109456
Summary: KVM VFIO guest X hang with guest kernel > 4.15
Product: DRI
Version: XOrg git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
On Mon, 2018-11-12 at 18:41 +0100, Lucas Stach wrote:
> The horizontal blanking periods are too short, as the values are
> specified for a single LVDS channel. Since this panel is dual LVDS
> they need to be doubled. With this change the panel reaches its
> nominal vrefresh rate of 60Fps, instead o
Reviewed-by: Christian König
If there are no objections over the weekend I'm going to push that into
upstream direction on monday.
Thanks for the work,
Christian.
Am 25.01.19 um 12:02 schrieb Thomas Zimmermann:
> This patchset cleans up the last remaining callers of ttm_bo_reference
> and ttm_
Am 25.01.19 um 09:43 schrieb Ard Biesheuvel:
On Thu, 24 Jan 2019 at 15:01, Alex Deucher wrote:
On Thu, Jan 24, 2019 at 9:00 AM Ard Biesheuvel
wrote:
On Thu, 24 Jan 2019 at 13:31, Koenig, Christian
wrote:
Am 24.01.19 um 13:06 schrieb Ard Biesheuvel:
The DRM driver stack is designed to work
Hi Russell,
On Fri, Jan 25, 2019 at 09:40:38AM +, Russell King - ARM Linux admin wrote:
> Hi,
>
> This series adds support for programming the SPD and vendor infoframes.
>
> It also adds support for pixel repeated modes - we were not rejecting
> these modes, but we also didn't have the imple
(Removed what I assume is a typo on the Cc line - n...@arm.com)
On Fri, Jan 25, 2019 at 11:45:10AM +, Brian Starkey wrote:
> Hi Russell,
>
> On Fri, Jan 25, 2019 at 09:40:38AM +, Russell King - ARM Linux admin
> wrote:
> > Hi,
> >
> > This series adds support for programming the SPD and
Hi,
On Fri, Jan 25, 2019 at 11:56:09AM +, Russell King - ARM Linux admin wrote:
> (Removed what I assume is a typo on the Cc line - n...@arm.com)
Sadly not. I have to Cc (not Bcc!) n...@arm.com to remove the
confidentiality disclaimer which would otherwise be added.
Ugly, but my only option.
Den 24.01.2019 15.53, skrev Hans de Goede:
> Hi,
>
> On 24-01-19 15:38, Noralf Trønnes wrote:
>> [cc:Hans]
>>
>> Den 21.01.2019 10.22, skrev Daniel Vetter:
>>> On Sun, Jan 20, 2019 at 12:43:10PM +0100, Noralf Trønnes wrote:
This adds a function that creates a simple connector that has only
Instead of guessing whether TTM has the dma page allocator enabled,
ask TTM.
Signed-off-by: Thomas Hellstrom
---
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
The vmwgfx driver needs to know whether the dma page pool is enabled
to determine whether to refuse loading if the dma mode logic
requests coherent memory from the dma page pool.
Cc: "Koenig, Christian"
Signed-off-by: Thomas Hellstrom
---
drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 11 ++
From: Thierry Reding
If an I2C adapter doesn't match the provided device tree node, also try
matching the parent's device tree node. This allows finding an adapter
based on the device node of the parent device that was used to register
it.
This fixes a regression on Tegra124-based Chromebooks (N
On Wednesday, 2019-01-23 10:45:18 +, Emil Velikov wrote:
> From: Emil Velikov
>
> The functions are virtually identical, fold them up.
>
> Signed-off-by: Emil Velikov
Assuming patch 1 is OK, and `foo` gets renamed to something better:
Reviewed-by: Eric Engestrom
I don't know enough to re
Am Mittwoch, 23. Januar 2019, 11:14:39 CET schrieb Sandy Huang:
> update SPDX License Identifier from GPL-2.0+ to GPL-2.0
> and drop some GPL text.
>
> Signed-off-by: Sandy Huang
I've added Fixes, Cc-stable and Reported-by (for Thomas) tags
and applied it to drm-misc-fixes
Thanks
Heiko
_
Hi Eric,
On Wed, 2019-01-23 at 10:47 -0800, Eric Anholt wrote:
> Paul Kocialkowski writes:
>
> > From: Boris Brezillon
> >
> > The DRM framework provides a generic way to report underrun errors.
> > Let's implement the necessary hooks to support it in the VC4 driver.
> >
> > Signed-off-by: Bo
On Sat, Jan 19, 2019 at 01:43:43AM +0900, Tetsuo Handa wrote:
> syzbot is hitting a lockdep warning [1] because flush_work() is called
> without INIT_WORK() after kzalloc() at vkms_atomic_crtc_reset().
>
> Commit 6c234fe37c57627a ("drm/vkms: Implement CRC debugfs API") added
> INIT_WORK() to only
Hi,
On Wed, 2019-01-23 at 10:34 -0800, Eric Anholt wrote:
> Paul Kocialkowski writes:
>
> > During an atomic commit, the HVS is configured with a display list
> > for the channel matching the associated CRTC. The Pixel Valve (CRTC)
> > and encoder are also configured for the new setup at that ti
On Thu, 24 Jan 2019 at 16:58, Daniel Vetter wrote:
>
> This is only used by drm_irq_install(), which is an optional helper.
> And the right choice is to set it for all pci devices, and not for
> everything else.
>
Can you please add some information (or reference) why it's the right choice?
Thank
If fbdev setup has failed, lastclose will give a NULL pointer deref:
[ 77.794295] [drm:drm_lastclose]
[ 77.794414] [drm:drm_lastclose] driver lastclose completed
[ 77.794660] Unable to handle kernel NULL pointer dereference at virtual
address 0014
[ 77.809460] pgd = b376b71b
[ 77.81
On Thu, 24 Jan 2019 at 17:00, Daniel Vetter wrote:
>
> It's 0.
>
I'd add a bit more information here. Feel free to reuse as much/little
of the following:
Both macros evaluate to 0. At the same time flag is already set to
zero since the struct is kzalloc'd in framebuffer_alloc().
As called by drm_
On Thu, 24 Jan 2019 at 16:58, Daniel Vetter wrote:
>
> If a non-legacy driver calls these it's valid to assume there is
> interrupt support. The flag is really only needed for legacy drivers.
... legacy drivers which issue the IRQ via the DRM_IOCTL_CONTROL legacy IOCTL.
At a later stage, we migh
On Thu, Jan 24, 2019 at 05:58:27PM +0100, Daniel Vetter wrote:
> Another driver that didn't set fbinfo->fix.id before.
>
> Signed-off-by: Daniel Vetter
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Cc: linux-te...@vger.kernel.org
> ---
> drivers/gpu/drm/tegra/fb.c | 4 +---
> 1 file changed, 1
On Thu, Jan 24, 2019 at 05:58:31PM +0100, Daniel Vetter wrote:
> It's 0.
>
> Signed-off-by: Daniel Vetter
> Cc: Inki Dae
> Cc: Joonyoung Shim
> Cc: Seung-Woo Kim
> Cc: Kyungmin Park
> Cc: Kukjin Kim
> Cc: Krzysztof Kozlowski
> Cc: Patrik Jakobsson
> Cc: Ben Skeggs
> Cc: Sandy Huang
> Cc:
On 2019-01-24 7:52 p.m., ndesaulni...@google.com wrote:
> arch/x86/Makefile disables SSE and SSE2 for the whole kernel. The
> AMDGPU drivers modified in this patch re-enable SSE but not SSE2. Turn
> on SSE2 to support emitting double precision floating point instructions
> rather than calls to no
https://bugs.freedesktop.org/show_bug.cgi?id=109456
--- Comment #1 from Alex Deucher ---
Can you bisect? Please attach your dmesg output and xorg log.
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Den 18.01.2019 13.19, skrev Gerd Hoffmann:
> Not used, is always NULL.
>
> Signed-off-by: Gerd Hoffmann
> ---
Acked-by: Noralf Trønnes
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Den 18.01.2019 13.19, skrev Gerd Hoffmann:
> Signed-off-by: Gerd Hoffmann
> ---
Acked-by: Noralf Trønnes
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On Fri, Jan 25, 2019 at 01:28:50AM +0530, Jagan Teki wrote:
> Most of the Allwinner MIPI DSI controllers are supply with
> VCC-DSI pin. which need to supply for some of the boards to
> trigger the power.
>
> So, document the supply property so-that the required board
> can eable it via device tree
Den 18.01.2019 13.20, skrev Gerd Hoffmann:
> Drop pointless indirection, remove the mem_slots array and index
> variables, drop dynamic allocation. Store memslots in qxl_device
> instead.
>
> Signed-off-by: Gerd Hoffmann
> ---
Looks sane:
Acked-by: Noralf Trønnes
___
Den 18.01.2019 13.20, skrev Gerd Hoffmann:
> From: Frediano Ziglio
>
> Instead of relaying on surface type use the actual placement.
> This allow to have different placement for a single type of
> surface.
>
> Signed-off-by: Frediano Ziglio
>
> [ kraxel: rebased, adapted to upstream changes
On Fri, Jan 25, 2019 at 01:28:52AM +0530, Jagan Teki wrote:
> The MIPI DSI controller in Allwinner A64 is similar to A33.
>
> But unlike A33, A64 doesn't have DSI_SCLK gating which eventually
> set the mod clock rate for the controller.
>
> So, use the DSI_DPHY gating for the similar purpose of m
On Fri, Jan 25, 2019 at 01:28:53AM +0530, Jagan Teki wrote:
> The MIPI DSI PHY controller on Allwinner A64 is similar
> on the one on A31.
>
> Add A64 compatible and append A31 compatible as fallback.
>
> Signed-off-by: Jagan Teki
> Reviewed-by: Rob Herring
> ---
> Documentation/devicetree/bin
Den 18.01.2019 13.20, skrev Gerd Hoffmann:
> slot_id_bits and slot_gen_bits can be read directly from qxlrom instead.
> va_slot_mask is never used anywhere.
>
> Signed-off-by: Gerd Hoffmann
> ---
Acked-by: Noralf Trønnes
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d
Den 18.01.2019 13.20, skrev Gerd Hoffmann:
> Without that ttm offsets are not unique, they can refer to objects
> in both VRAM and PRIV memory (aka main and surfaces slot).
>
> One of those "why things didn't blow up without this" moments.
> Probably offset conflicts are rare enough by pure luck
Den 18.01.2019 13.20, skrev Gerd Hoffmann:
> qxl surfaces (used for framebuffers and gem objects) can live in both
> VRAM and PRIV ttm domains. Update placement setup to include both.
> Put PRIV first in the list so it is preferred, so VRAM will have more
> room for objects which must be allocat
Den 18.01.2019 13.20, skrev Gerd Hoffmann:
> The shadow bo is used as qxl surface, so allocate it as
> QXL_GEM_DOMAIN_SURFACE. Should usually be allocated in
> PRIV ttm domain then, so this reduces VRAM memory pressure.
>
> Signed-off-by: Gerd Hoffmann
> ---
Acked-by: Noralf Trønnes
Den 18.01.2019 13.20, skrev Gerd Hoffmann:
> dumb buffers are used as qxl surfaces, so allocate them as
> QXL_GEM_DOMAIN_SURFACE. Should usually be allocated in
> PRIV ttm domain then, so this reduces VRAM memory pressure.
>
> Signed-off-by: Gerd Hoffmann
> ---
Acked-by: Noralf Trønnes
_
On Fri, Jan 25, 2019 at 09:46:15AM -0500, Sean Paul wrote:
> On Sat, Jan 19, 2019 at 01:43:43AM +0900, Tetsuo Handa wrote:
> > syzbot is hitting a lockdep warning [1] because flush_work() is called
> > without INIT_WORK() after kzalloc() at vkms_atomic_crtc_reset().
> >
> > Commit 6c234fe37c57627a
Den 18.01.2019 13.20, skrev Gerd Hoffmann:
> The cursor must be set again after creating the primary surface.
> Also drop the error message.
>
> Signed-off-by: Gerd Hoffmann
> ---
> drivers/gpu/drm/qxl/qxl_display.c | 10 +++---
> 1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff -
Den 18.01.2019 13.20, skrev Gerd Hoffmann:
> Signed-off-by: Gerd Hoffmann
> ---
Acked-by: Noralf Trønnes
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Den 18.01.2019 13.20, skrev Gerd Hoffmann:
> Track which bo is used as primary surface. With that in place we don't
> need the primary_created flag any more, we can just check the primary bo
> pointer instead.
>
> Also verify we don't already have a primary surface in
> qxl_io_create_primary().
https://bugs.freedesktop.org/show_bug.cgi?id=107978
--- Comment #47 from Jerry Zuo ---
You observed the monitor goes to sleep right after reboot, did you? Hotplug
will have the display back on. Is that what you observed?
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On Fri, Jan 25, 2019 at 02:46:55PM +, Emil Velikov wrote:
> On Thu, 24 Jan 2019 at 16:58, Daniel Vetter wrote:
> >
> > This is only used by drm_irq_install(), which is an optional helper.
> > And the right choice is to set it for all pci devices, and not for
> > everything else.
> >
> Can you
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