18. 12. 11. 오후 4:49에 Andrzej Hajda 이(가) 쓴 글:
> On 11.12.2018 00:45, Inki Dae wrote:
>> Hi Andrzej,
>>
>> 18. 12. 10. 오후 4:35에 Andrzej Hajda 이(가) 쓴 글:
>>> Hi Inki,
>>>
>>> On 10.12.2018 03:25, Inki Dae wrote:
Hi Andrzej,
18. 12. 6. 오후 6:38에 Andrzej Hajda 이(가) 쓴 글:
> Hi Inki,
>>>
Hi Sebastian,
(CC'ing Daniel)
On Tuesday, 11 December 2018 03:07:45 EET Sebastian Reichel wrote:
> On Mon, Dec 10, 2018 at 02:14:01PM +0100, Sebastian Reichel wrote:
> > On Mon, Dec 10, 2018 at 09:50:08AM +0200, Laurent Pinchart wrote:
> >> On Monday, 10 December 2018 00:07:55 EET Sebastian Reich
On Mon, Dec 10, 2018 at 11:30:01AM +0100, Daniel Vetter wrote:
> lkml and Linus gained a CoC, and it's serious this time. Which means
> my no 1 reason for declining to officially step up as drm maintainer
> is gone, and I didn't find any new good excuse.
>
> I chatted with a few people in private
On 11.12.2018 09:01, Inki Dae wrote:
>
> 18. 12. 11. 오후 4:49에 Andrzej Hajda 이(가) 쓴 글:
>> On 11.12.2018 00:45, Inki Dae wrote:
>>> Hi Andrzej,
>>>
>>> 18. 12. 10. 오후 4:35에 Andrzej Hajda 이(가) 쓴 글:
Hi Inki,
On 10.12.2018 03:25, Inki Dae wrote:
> Hi Andrzej,
>
> 18. 12. 6. 오후
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
So, alter has_mod_clk bool via driver data for respective
SoC's compatible.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 +++
1 file changed, 7 ins
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetre
DRM driver fails to load if VIC firmware is missing, let's defer the
firmware loading until it is really needed. This eliminates the need
to have initrd with the firmware if DRM driver is compiled as built-in.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/vic.c | 43 ++
Hi Thierry
On Mon, 2018-12-10 at 11:21 +0100, Thierry Reding wrote:
> On Sat, Dec 08, 2018 at 02:54:45PM +, Marcel Ziswiler wrote:
> > Hi Thierry et al.
> >
> > I noticed that since commit 3dde5a2342cd ("ARM: tegra: Add VIC on
> > Tegra124") graphics on Apalis TK1 is broken. During boot it fa
Commit '88ba95bedb79 ("backlight: pwm_bl: Compute brightness of LED
linearly to human eye")' allows the possibility to compute a default
brightness table when there isn't the brightness-levels property in the
DT. Unfortunately the changes made broke the pwm backlight for the
non-DT boards.
Usually
Hi,
On Mon, Dec 10, 2018 at 02:28:43PM +0200, Laurent Pinchart wrote:
> The omap_dss_device type and output_type fields differ mostly for
> historical reasons. The output_type field is required for all devices
> but the display at the end of the pipeline, and must be set to
> OMAP_DISPLAY_TYPE_NON
This series fixed the issues related to work DSI on 2-lane panel
which is reported on previous version[1][2][3]
This supposed to be a clean series, where it support Allwinner A64 MIPI-DSI
support for 4-lane, 2-lane DSI panels.
This series fixed all previous series comments along with checkpatch
w
On Mon, Dec 10, 2018 at 10:05 AM Maxime Jourdan wrote:
>
> In case we are using simplefb or another conflicting framebuffer, make
> the call to drm_fb_helper_remove_conflicting_framebuffers()
>
> Signed-off-by: Maxime Jourdan
> ---
> drivers/gpu/drm/meson/meson_drv.c | 19 +++
>
In case we are using simplefb or another conflicting framebuffer, make
the call to drm_fb_helper_remove_conflicting_framebuffers()
Signed-off-by: Maxime Jourdan
---
drivers/gpu/drm/meson/meson_drv.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/meson/m
On 08/12/2018 18:12, Martin Blumenstingl wrote:
> The Meson8 SoC is slightly different compared to Meson8b and Meson8m2
> because it does not have the glitch-free Mali GPU clock mux. For Meson8b
> and Meson8m2 there are currently no known differences.
>
> Add a separate clk_hw_onecell_data table f
Some NKM PLLs doesn't work well when their output clock rate is set below
certain rate.
So, add support for minimal rate for relevant PLLs.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu_nkm.c | 5 +
drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
2 files changed, 6 in
Minimum PLL used for MIPI is 500MHz, as per manual, but
lowering the min rate by 300MHz can result proper working
nkms divider with the help of desired dclock rate from
panel driver.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 1 +
1 file changed
On Fri, 2018-11-23 at 13:11 +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> As part of commit cfea88a4d866 ("drm/nouveau: Start using new drm_dev
> initialization helpers"), the initialization of the Nouveau DRM
> device
> was reworked and along the way the platform driver initialization
TCON DRQ set bits for non-burst DSI mode can computed via
horizontal front porch instead of front porch + sync timings.
BSP code form BPI-M64-bsp is computing TCON DRQ set bits
for non-burts as (from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
=> panel->lcd_ht -
Hi Laurent,
On Mon, Dec 10, 2018 at 10:27:05AM +0200, Laurent Pinchart wrote:
> On Monday, 10 December 2018 00:19:22 EET Sebastian Reichel wrote:
> > On Wed, Dec 05, 2018 at 05:00:17PM +0200, Laurent Pinchart wrote:
> > > The encoder .atomic_check() and connector .mode_valid() operations both
> >
Hi Thierry
On Mon, 2018-12-10 at 17:23 +0100, Thierry Reding wrote:
Snip.
> > Looks like with pci_disable_device() it may take a rather strange
> > path...
>
> Yikes... it has no business at all calling pci_disable_device() on
> Tegra. Unless if you happen to have a GPU plugged into the PCIe sl
Short transfer write support for DCS and Generic transfer types
share similar way to process command sequence in DSI block so
add generic write 2 param transfer type macro so-that the panels
which are requesting similar transfer type may process properly.
Signed-off-by: Jagan Teki
---
drivers/gp
Quoting Matthias Kaehlcke (2018-12-04 14:42:29)
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate.
>
> Signed-off-by: Matthias Kaehlcke
> ---
Reviewed-by: Stephen Boyd
___
dri-devel mailing list
dri-devel@l
hblk is adding line with all porch timing values, or timings
values from htotal without sync time.
Current driver is subtracting htotal with hsa, but the hsa
is bounded with packet overhead. For real hblk calculation
needed by subtracting htotal with back and front porch values
and BSP code BPI-M6
Hi,
On Mon, Dec 10, 2018 at 09:50:08AM +0200, Laurent Pinchart wrote:
> Hi Sebastian,
>
> On Monday, 10 December 2018 00:07:55 EET Sebastian Reichel wrote:
> > On Wed, Dec 05, 2018 at 05:00:15PM +0200, Laurent Pinchart wrote:
> > > The DISPC timings checks relate to the CRTC, but they're performe
On Fri, Dec 7, 2018 at 6:51 PM Maxime Ripard wrote:
>
> On Tue, Nov 27, 2018 at 04:34:35PM +0530, Jagan Teki wrote:
> > On Tue, Nov 27, 2018 at 3:55 PM Maxime Ripard
> > wrote:
> > >
> > > On Tue, Nov 20, 2018 at 09:55:42PM +0530, Jagan Teki wrote:
> > > > On Tue, Nov 20, 2018 at 9:27 PM Maxime
Hi Thierry and David,
On Fri, Nov 16, 2018 at 10:10 PM Jagan Teki wrote:
>
> Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
>
> Add panel driver for it.
>
> Signed-off-by: Jagan Teki
> ---
> MAINTAINERS | 6 +
> drivers/gpu/drm/panel/Kconfig
Unlike hblk, the vblk timings should follow an equation to compute
the desired value for lane 4 devices and rest of devices it would be 0.
BSP code from BPI-M64-bsp is computing vblk as for 4-lane devices
(from linux-sunxi
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
tmp = (ht*ds
Some boards have VCC-DSI pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
MIPI DSI driver.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 14 ++
drivers/gpu/drm/
Quoting Matthias Kaehlcke (2018-12-04 14:42:28)
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate.
>
> Signed-off-by: Matthias Kaehlcke
> ---
Reviewed-by: Stephen Boyd
___
dri-devel mailing list
dri-devel@l
On 12/10/18 5:36 PM, Hans Verkuil wrote:
> On 12/10/18 5:34 PM, Thierry Reding wrote:
>> From: Thierry Reding
>>
>> Most of the CEC support code already lives in the "output" library code.
>> Move registration and unregistration to the library code as well to make
>> use of the same code with HDMI
Quoting Matthias Kaehlcke (2018-12-04 14:42:31)
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate.
>
> Note: This change could break old out-of-tree DTS files that
> use the 10nm PHY
>
> Signed-off-by: Matthias Kaehlcke
> Reviewed-by: Douglas Anderson
The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
on the one on A31.
Add A64 compatible and append A31 compatible as fallback.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion(+)
Current driver is calculating hfp maximum value by subtracting
htotal with hsync_end which is front back value, but the
hpp refers to front porch.
Front porch value is calculating by subtracting hsync_start with
hdisplay as per drm_mode timings, and BSP code from BPI-M64-bsp
is eventually followin
Current driver is calculating hbp maximum value by subtracting
hsync_start with hdisplay which is front porch value, but the
hbp refers to back porch.
Back porch value is calculating by subtracting htotal with
hsync_end as per drm_mode timings, and BSP code from BPI-M64-bsp
is eventually following
Most of the Allwinner MIPI DSI controllers are supply with
VCC-DSI pin. which need to supply for some of the boards to
trigger the power.
So, document the supply property so-that the required board
can eable it via device tree.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentati
On 12/10/18 5:34 PM, Thierry Reding wrote:
> From: Thierry Reding
>
> Most of the CEC support code already lives in the "output" library code.
> Move registration and unregistration to the library code as well to make
> use of the same code with HDMI on Tegra210 and later via the SOR.
>
> Signed
The A64 has a MIPI-DSI block which is similar to A31
without mod clock.
So, add dsi node with A64 compatible, dphy node with
A31 compatible and finally connect dsi to tcon0 to
make proper DSI pipeline.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45
Mod clock is not mandatory for all Allwinner MIPI DSI
controllers, it is connected as CLK_DSI_SCLK for A31
and not available in A64.
So add has_mod_clk quirk and process the clk accordingly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 39 ++
dr
Hi Thierry
On Mon, 2018-12-10 at 12:00 +0100, Thierry Reding wrote:
> On Mon, Dec 10, 2018 at 11:21:47AM +0100, Thierry Reding wrote:
> > On Sat, Dec 08, 2018 at 02:54:45PM +, Marcel Ziswiler wrote:
> > > Hi Thierry et al.
> > >
> > > I noticed that since commit 3dde5a2342cd ("ARM: tegra: Add
On 12/10/18 3:47 AM, james qian wang (Arm Technology China) wrote:
> On Wed, Dec 05, 2018 at 06:08:38PM -0800, Randy Dunlap wrote:
>> On 12/5/18 2:25 AM, james qian wang (Arm Technology China) wrote:
>>> Signed-off-by: James (Qian) Wang
>>> ---
>>> Documentation/gpu/drivers.rst| 1 +
>>> Do
Hi,
On Mon, Dec 10, 2018 at 10:01:19AM +0200, Laurent Pinchart wrote:
> Instead of rolling out custom suspend/resume implementations based on
> state information stored in the driver's data structures, use the atomic
> suspend/resume helpers that rely on a DRM atomic state object.
>
> Signed-off-
On 10.12.2018 13:21, Thierry Reding wrote:
> On Sat, Dec 08, 2018 at 02:54:45PM +, Marcel Ziswiler wrote:
>> Hi Thierry et al.
>>
>> I noticed that since commit 3dde5a2342cd ("ARM: tegra: Add VIC on
>> Tegra124") graphics on Apalis TK1 is broken. During boot it fails
>> loading the vic firmware
Quoting Matthias Kaehlcke (2018-12-04 14:42:30)
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> index 71fe60e5f01f1..032bf3e8614bd 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
Add 10 bytes packet overhead for hblk where blank is set using
a blanking packet like (4 bytes + 4 bytes + payload + 2 bytes)
This is according to BSP code from BPI-M64-bsp (from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
dsi_hblk = (ht-hspw)*dsi_pixel_bits[format]
Hi,
On Mon, Dec 10, 2018 at 02:14:01PM +0100, Sebastian Reichel wrote:
> On Mon, Dec 10, 2018 at 09:50:08AM +0200, Laurent Pinchart wrote:
> > Hi Sebastian,
> >
> > On Monday, 10 December 2018 00:07:55 EET Sebastian Reichel wrote:
> > > On Wed, Dec 05, 2018 at 05:00:15PM +0200, Laurent Pinchart w
Video start delay can be computed by subtracting total vertical
timing with front porch timing and with adding 1 delay line for TCON.
BSP code form BPI-M64-bsp is computing video start delay as
(from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
u32 vfp = panel->lcd_v
Clang warns when an expression that equals zero is used as a null
pointer constant (in lieu of NULL):
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4435:3:
warning: expression which evaluates to zero treated as a null pointer
constant of type 'const enum color_transfer_func *'
[-Wnon
In case we are using simplefb or another conflicting framebuffer, make
the call to drm_fb_helper_remove_conflicting_framebuffers()
Signed-off-by: Maxime Jourdan
---
drivers/gpu/drm/meson/meson_drv.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/meson/me
On 08/12/2018 18:12, Martin Blumenstingl wrote:
> Add the GPU clock tree on Meson8, Meson8b and Meson8m2.
>
> The GPU clock tree on Meson8b and Meson8m2 is almost identical to the
> one one GXBB:
> - there's a glitch-free mux at HHI_MALI_CLK_CNTL[31]
> - there are two identical parents for this mu
On Mon, Dec 10, 2018 at 10:51:04PM +0100, Arnd Bergmann wrote:
> In this usage, the two are completely equivalent, but the
> completion documents better what is going on, and we generally
> try to avoid semaphores these days.
>
> Signed-off-by: Arnd Bergmann
> ---
> drivers/gpu/host1x/cdma.c | 6
On Tue, Dec 11, 2018 at 11:08 AM Thierry Reding
wrote:
>
> On Mon, Dec 10, 2018 at 10:51:04PM +0100, Arnd Bergmann wrote:
> > In this usage, the two are completely equivalent, but the
> > completion documents better what is going on, and we generally
> > try to avoid semaphores these days.
> >
> >
The gpu crashstate's base objects registers pointer can be NULL if the
target implementation decides to capture the register dump on its own.
This patch simply checks for NULL before dereferencing.
Signed-off-by: Sharat Masetty
---
Changes from v1:
Addressed comments from Jordan Crouse
We are not really checking the state of the adreno_gpu_state_get()
function at the callers and in addition the state capture is mostly a
best effort service, so make the function return void.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 +---
drivers/gpu/drm/msm/
On Tue, Dec 11, 2018 at 11:11:38AM +0100, Arnd Bergmann wrote:
> On Tue, Dec 11, 2018 at 11:08 AM Thierry Reding
> wrote:
> >
> > On Mon, Dec 10, 2018 at 10:51:04PM +0100, Arnd Bergmann wrote:
> > > In this usage, the two are completely equivalent, but the
> > > completion documents better what is
From: Christian König
This completes "drm/syncobj: Drop add/remove_callback from driver
interface" and cleans up the implementation a bit.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 91 ---
include/drm/drm_syncobj.h | 21
2 f
From: Christian König
Lockless container implementation similar to a dma_fence_array, but with
only two elements per node and automatic garbage collection.
v2: properly document dma_fence_chain_for_each, add dma_fence_chain_find_seqno,
drop prev reference during garbage collection if it's no
points array is one-to-one match with syncobjs array.
v2:
add seperate ioctl for timeline point wait, otherwise break uapi.
v3:
userspace can specify two kinds waits::
a. Wait for time point to be completed.
b. and wait for time point to become available
v4:
rebase
v5:
add comment for xxx_WAIT_AVAI
user mode can query timeline payload.
v2: check return value of copy_to_user
v3: handle querying entry by entry
v4: rebase on new chain container, simplify interface
Signed-off-by: Chunming Zhou
Cc: Daniel Rakos
Cc: Jason Ekstrand
Cc: Bas Nieuwenhuizen
Cc: Dave Airlie
Cc: Christian König
Cc:
From: Christian König
Use the dma_fence_chain object to create a timeline of fence objects
instead of just replacing the existing fence.
v2: rebase and cleanup
v3: fix garbage collection parameters
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 37 +
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8de55f7f1a3a..cafafdb1d03f 100644
--- a/drivers/gpu/drm/amd/amdgp
syncobj wait/signal operation is appending in command submission.
v2: separate to two kinds in/out_deps functions
Signed-off-by: Chunming Zhou
Cc: Daniel Rakos
Cc: Jason Ekstrand
Cc: Bas Nieuwenhuizen
Cc: Dave Airlie
Cc: Christian König
Cc: Chris Wilson
---
drivers/gpu/drm/amd/amdgpu/amdgp
From: Christian König
Implement finding the right timeline point in drm_syncobj_find_fence.
v2: return -EINVAL when the point is not submitted yet.
v3: fix reference counting bug, add flags handling as well
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 43
v2: individually allocate chain array, since chain node is free independently.
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/drm_internal.h | 2 +
drivers/gpu/drm/drm_ioctl.c| 2 +
drivers/gpu/drm/drm_syncobj.c | 81 ++
include/uapi/drm/drm.h |
we need to import/export timeline point.
v2: unify to one transfer ioctl
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/drm_internal.h | 2 +
drivers/gpu/drm/drm_ioctl.c| 2 +
drivers/gpu/drm/drm_syncobj.c | 74 ++
include/uapi/drm/drm.h | 10 +++
v2: drop not implemented IOCTLs and flags
v3: add transfer/signal ioctls
Signed-off-by: Chunming Zhou
Signed-off-by: Christian König
---
include/drm/drm.h | 35 +++
1 file changed, 35 insertions(+)
diff --git a/include/drm/drm.h b/include/drm/drm.h
index 85c685a
v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
fix some warnings
v3: add export/import and cpu signal testing cases
Signed-off-by: Chunming Zhou
Signed-off-by: Christian König
---
tests/amdgpu/Makefile.am | 3 +-
tests/amdgpu/amdgpu_test.c | 12 ++
tests/amdgpu
Signed-off-by: Chunming Zhou
---
include/drm/amdgpu_drm.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 1ceec56d..a3c067dd 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -517,6 +517,8 @@ struct drm_a
v2: symbos are stored in lexical order.
v3: drop export/import and extra query indirection
Signed-off-by: Chunming Zhou
Signed-off-by: Christian König
---
amdgpu/amdgpu-symbol-check | 2 ++
amdgpu/amdgpu.h| 39 ++
amdgpu/amdgpu_cs.c | 23
v2: drop export/import
Signed-off-by: Chunming Zhou
---
xf86drm.c | 44
xf86drm.h | 6 ++
2 files changed, 50 insertions(+)
diff --git a/xf86drm.c b/xf86drm.c
index 71ad54ba..9816b3b2 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4277,3 +4277,47 @@
v2: use one transfer ioctl
Signed-off-by: Chunming Zhou
---
xf86drm.c | 33 +
xf86drm.h | 6 ++
2 files changed, 39 insertions(+)
diff --git a/xf86drm.c b/xf86drm.c
index 9816b3b2..2a089616 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4278,6 +4278,21 @@ drm_pu
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu.h| 22 ++
amdgpu/amdgpu_cs.c | 16
2 files changed, 38 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 5536d2d5..48e28aef 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1638,6 +1638
v2: adapt to new one transfer ioctl
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu-symbol-check | 3 ++
amdgpu/amdgpu.h| 51
amdgpu/amdgpu_cs.c | 68 ++
3 files changed, 122 insertions(+)
diff --git a/amdgpu/a
v2: adapt to new transfer ioctl
Signed-off-by: Chunming Zhou
---
include/drm-uapi/drm.h | 33 ++
lib/igt_syncobj.c| 206
lib/igt_syncobj.h| 19 +
tests/meson.build|1 +
tests/syncobj_timeline.c | 1032 ++
5 files cha
Hi Giulio,
On Thu, 6 Dec 2018 at 22:00, Giulio Benetti
wrote:
>
> Hi Jonathan,
>
> Il 06/12/2018 08:29, Jonathan Liu ha scritto:
> > Hi Giulio,
> >
> > On Thu, 15 Feb 2018 at 17:54, Giulio Benetti
> > wrote:
> >>
> >> Differently from other Lcd signals, HSYNC and VSYNC signals
> >> result invert
https://bugs.freedesktop.org/show_bug.cgi?id=108919
--- Comment #9 from Alexander Walker ---
Created attachment 142775
--> https://bugs.freedesktop.org/attachment.cgi?id=142775&action=edit
renderdoc capture
--
You are receiving this mail because:
You are the assignee for the bug._
Hi Daniel,
On Mon, Dec 10, 2018 at 11:30:01AM +0100, Daniel Vetter wrote:
> lkml and Linus gained a CoC, and it's serious this time. Which means
> my no 1 reason for declining to officially step up as drm maintainer
> is gone, and I didn't find any new good excuse.
I wish you best of luck in the
https://bugs.freedesktop.org/show_bug.cgi?id=108919
--- Comment #10 from Alexander Walker ---
(In reply to Timothy Arceri from comment #8)
> Do you think you could try grabbing a capture in renderdoc [1]? Once you
> unzip it somewhere you can add the following to the launch options for the
> game
https://bugs.freedesktop.org/show_bug.cgi?id=102646
--- Comment #58 from tempel.jul...@gmail.com ---
I've written a small script to only write into pp_dpm_mclk when it's not forced
into pstate 2:
#!/bin/bash
if ! cat /sys/class/drm/card0/device/pp_dpm_mclk |
grep -xqFe "2: 2250Mhz *"
then
ec
Build the GPU crashstate capture functions only if either of
CONFIG_DEBUG_FS, CONFIG_DEV_COREDUMP is defined.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
https://bugs.freedesktop.org/show_bug.cgi?id=108919
--- Comment #11 from Alexander Walker ---
Created attachment 142776
--> https://bugs.freedesktop.org/attachment.cgi?id=142776&action=edit
renderdoc black screen from toggling vsync
--
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On 06/12/2018 22:26, Laurent Pinchart wrote:
> The TI TFP410 is a DVI encoder, not a full HDMI encoder. Its output can
> be routed to a DVI-D connector, even if in many cases embedded systems
> will use an HDMI connector to carry the DVI signals.
>
> Instead of hardcoding the connector type to HDM
On 06/12/2018 22:26, Laurent Pinchart wrote:
> The TFP410 has a powerdown pin that can be connected to a GPIO to
> control power saving. The DT bindings define a corresponding property,
> but the driver doesn't implement support for it. Fix that.
>
> Signed-off-by: Laurent Pinchart
> ---
I find
On Fri, 7 Dec 2018 14:47:57 +0100
Paul Kocialkowski wrote:
> diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
> index f3fd34faa812..e80b1ad5c938 100644
> --- a/drivers/gpu/drm/vc4/vc4_kms.c
> +++ b/drivers/gpu/drm/vc4/vc4_kms.c
> @@ -479,6 +479,7 @@ static const struct
Hi again,
It seems I have missed two questions:
On 11.12.2018 09:36, Andrzej Hajda wrote:
> On 11.12.2018 09:01, Inki Dae wrote:
>> 18. 12. 11. 오후 4:49에 Andrzej Hajda 이(가) 쓴 글:
>>> On 11.12.2018 00:45, Inki Dae wrote:
Hi Andrzej,
18. 12. 10. 오후 4:35에 Andrzej Hajda 이(가) 쓴 글:
> H
On Mon, Dec 10, 2018 at 02:15:11PM -0800, Dhinakaran Pandiyan wrote:
> On Mon, 2018-12-10 at 23:29 +0200, Ville Syrjälä wrote:
> > On Mon, Dec 10, 2018 at 01:07:49PM -0800, Dhinakaran Pandiyan wrote:
> > > The Write_Status_Update_Request I2C transaction requires the MOT
> > > bit to
> > > be set, C
I've pulled this into the dma-mapping for-next tree now.
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Hi Jyri,
On Tuesday, 11 December 2018 15:01:52 EET Jyri Sarha wrote:
> On 06/12/2018 22:26, Laurent Pinchart wrote:
> > The TFP410 has a powerdown pin that can be connected to a GPIO to
> > control power saving. The DT bindings define a corresponding property,
> > but the driver doesn't implement
On Tue, 11 Dec 2018 15:09:26 +0100
Petr Mladek wrote:
> > We have liburcu already, which is good. The main sticking points are:
> >
> > - printk has started adding a lot of %pX enhancements which printf
> >obviously doesn't know about.
>
> I wonder how big problem it is and if it is wor
On Mon, 22 Oct 2018 14:31:22 +0200
Boris Brezillon wrote:
> From: Rob Clark
>
> Follow the same pattern of locking as with other state objects. This
> avoids boilerplate in the driver.
>
> Signed-off-by: Rob Clark
> Signed-off-by: Boris Brezillon
> Reviewed-by: Daniel Vetter
Queued to drm-
On 06/12/2018 22:26, Laurent Pinchart wrote:
> The TFP410 supports configurable pixel clock sampling edge and data
> de-skew adjustments. The configuration can be set through I2C or
> dedicated chip pins.
>
> Report the configuration through the drm_bridge timings. As the
> ti-tftp410 driver doesn
https://bugzilla.kernel.org/show_bug.cgi?id=201957
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC||alexdeuc...@gmail.c
Hi Laurent,
On 04/12/2018 16:36, Laurent Pinchart wrote:
> Implement a .mode_valid() handler in the R-Car glue layer to reject
> modes with an unsupported clock frequency.
Thank you, I believe my concerns were addressed;
(and my misunderstandings are now understandings)
> Signed-off-by: Laurent
On 11/12/18 16:48, Jyri Sarha wrote:
>> +/* Get the setup and hold time from vendor-specific properties. */
>> +of_property_read_u32(dvi->dev->of_node, "ti,deskew", (u32 *)&deskew);
>> +if (deskew < -4 || deskew > 3)
>> +return -EINVAL;
>
> Is "ti,deskew" property document
Am Mittwoch, 5. Dezember 2018, 19:16:57 CET schrieb Brian Norris:
> This reverts commit 7f3ef5dedb146e3d5063b6845781ad1bb59b92b5.
>
> It causes new warnings [1] on shutdown when running the Google Kevin or
> Scarlet (RK3399) boards under Chrome OS. Presumably our usage of DRM is
> different than w
On 11/12/2018 17:19, Tomi Valkeinen wrote:
> On 11/12/18 16:48, Jyri Sarha wrote:
>
>>> + /* Get the setup and hold time from vendor-specific properties. */
>>> + of_property_read_u32(dvi->dev->of_node, "ti,deskew", (u32 *)&deskew);
>>> + if (deskew < -4 || deskew > 3)
>>> + return
Hi Jyri,
On Tuesday, 11 December 2018 16:48:16 EET Jyri Sarha wrote:
> On 06/12/2018 22:26, Laurent Pinchart wrote:
> > The TFP410 supports configurable pixel clock sampling edge and data
> > de-skew adjustments. The configuration can be set through I2C or
> > dedicated chip pins.
> >
> > Report
On Mon, Dec 10, 2018 at 10:58:20AM -0500, Alex Deucher wrote:
> On Mon, Dec 10, 2018 at 5:04 AM Daniel Vetter wrote:
> >
> > It's not a core function, and the matching atomic functions are also
> > not in the core. Plus the suspend/resume helper is also already there.
> >
> > Needs a tiny bit of o
On Tue, Dec 11, 2018 at 10:53 AM Sean Paul wrote:
>
> On Mon, Dec 10, 2018 at 10:58:20AM -0500, Alex Deucher wrote:
> > On Mon, Dec 10, 2018 at 5:04 AM Daniel Vetter
> > wrote:
> > >
> > > It's not a core function, and the matching atomic functions are also
> > > not in the core. Plus the suspen
A I understand you say that by the time the fence callback runs the job
might have already been released,
but how so if the job gets released from drm_sched_job_finish work
handler in the normal flow - so, after the HW
fence (s_fence->parent) cb is executed. Other 2 flows are error use
cases w
Yeah, completely correct explained.
I was unfortunately really busy today, but going to give that a look as
soon as I have time.
Christian.
Am 11.12.18 um 17:01 schrieb Grodzovsky, Andrey:
A I understand you say that by the time the fence callback runs the job
might have already been release
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