Hi Stefan,
On Monday, 24 September 2018 14:54:36 EET Stefan Agner wrote:
> On 22.09.2018 14:15, Laurent Pinchart wrote:
> > Hello,
> >
> > This patch series attemps at clarifying usage of the
> > DRM_BUS_FLAG_PIXDATA_(POS|NEG)EDGE flags. It results from a discussion
> > on the mailing list availa
Hello, Daniel!
Could you please ack/nack the patch, so either we can merge the
series or I can address your comments if any
Thank you,
Oleksandr
On 11/30/18 9:42 AM, Oleksandr Andrushchenko wrote:
From: Oleksandr Andrushchenko
Use page directory based shared buffer implementation
now avail
Hello,
On Monday, 24 September 2018 15:34:54 EET Stefan Agner wrote:
> On 24.09.2018 14:13, Thierry Reding wrote:
> > On Mon, Sep 24, 2018 at 01:59:25PM +0200, Stefan Agner wrote:
> >> On 24.09.2018 13:48, Thierry Reding wrote:
> >>> On Sat, Sep 22, 2018 at 03:15:04PM +0300, Laurent Pinchart wrote
Display engine drivers often need to distinguish between different types of
YUV sub-sampling. This introduces helpers to check for common sub-sampling
ratios in their commonly-used denomination from the DRM format info.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Maxime Ripard
---
include/drm
It is often useful to check whether the DRM format info retrieved from
the DRM framebuffer matches a specific YUV planes disposition.
This introduces helpers to quickly check that a provided format info
matches a YUV format with a specific disposition, in commonly-used
terminology.
The intent of
The helper returning the input mode needs to know the number of planes
for the provided format. Passing the fourcc requires iterating through
the format info list in order to return the number of planes.
Pass the DRM format info structure directly instead to all helpers
related to configuring the
This series implements support for YUV formats using the display engine
frontend in the sun4i DRM driver, with various fixes along the way.
Scaling is supported for every format handled by the frontend.
The tiling mode used by the VPU on Allwinner platforms is also supported
by this series and a d
Checking for the number of planes is not sufficient to en ensure that
the format is a packed YUV422.
Use explicit fourcc helpers for the check instead.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 3 ++-
1 file changed, 2 insertions(+), 1
Semi-planar YUV formats use two distinct planes, one for luminance and
one for chrominance. To add support for them, we need to configure the
second line stride and buffer address registers to setup the second YUV
plane.
New definitions are introduced to configure the input format register
for the
Planar YUV formats come with 3 distinct planes, which requires
configuring the frontend line stride and address registers for the
third plane.
Our hardware only supports the YUV planes order and in order to support
formats with a YVU plane order, a helper is introduced to indicate
whether to inver
This introduces specific definitions for vendor Allwinner and its
associated tiled format modifier. This modifier is used for the output
format of the VPU, that can be imported directly with the display
engine hardware supported by the sun4i-drm driver.
Signed-off-by: Paul Kocialkowski
Reviewed-b
Since all the RGB input formats have the same value for the DATA_FMT
field of the INPUT_FMT register, we can group them when the format is
known to be RGB. Here, we assume that a non-YUV format is RGB, because
the hardware does not support any other colorspace than RGB and YUV.
Use the DRM format
In prevision of adding support for YUV formats, set the YUV to RGB
colorspace conversion coefficients if required and don't bypass the
CSC engine when converting.
The BT601 coefficients from the A33 BSP are copied over from the backend
code. Because of module inter-dependency, we can't have the fr
This introduces a list of supported modifiers for the driver, that
includes the Allwinner tiled modifier, as well as a format_mod_supported
callback.
The callback uses both the backend and frontend helpers to indicate
per-format modifier support (including for the linear modifier).
Signed-off-by:
This introduces support for packed YUV formats with 4:2:2 sampling using
the frontend. Definitions are introduced for the data format and pixel
sequence input format register values.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 22 +++
This introduces a helper to check whether a frontend input format
supports tiling mode. This helper is used when tiling is requested in
the frontend format support helper.
Only semiplanar and planar YUV formats are supported by the hardware.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripa
From: Maxime Ripard
The FIR filters phase depend on the SoC, so let's move it to our quirks
structure instead of removing them.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 28 --
drivers/gpu/drm/sun4i/sun4i
This introduces stride and offset configuration for the VPU tiling mode.
Stride is calculated differently than it is for linear formats and an
offset is calculated, for which new register definitions are introduced.
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 49
Make sure we reserve at least one slot for pipelined BO moves
during BO creation.
Fixes: 5786b66c9e3b drm/ttm: drop the extra reservation for pipelined BO
moves
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm
This adds the appropriate device-tree compatible and quirk data for
hooking frontend support for the A20. It supports the FIR coefficients
ready bit but not the access control bit. It also takes different phase
values than the A33 for these coefficients.
The compatible is already used in the A20 d
From: Maxime Ripard
Unlike what is currently being done, the ACCESS_CTRL bit documentation asks
that this bit should be set before modifying any register. The code in the
BSP also does this, so make sure we do this as well.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
dri
From: Maxime Ripard
The COEF_RDY bit isn't found in all the SoCs featuring some variant of the
frontend.
Add it to our quirks structure.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 9 +
drivers/gpu/drm/sun4i/sun4i_fronten
This introduces the data input mode definitions for the tiled YUV mode,
that are used in the input mode helper if tiling is requested.
The modifier is passed to the helper from the framebuffer to determine
if tiling is requested.
Only semiplanar and planar YUV formats are supported for tiling mod
From: Maxime Ripard
The ACCESS_CTRL bit is not found on all the variants of the frontend, so
let's introduce a structure that will hold whether or not we need to set
it, and associate it with the compatible.
This will be extended for further similar quirks later on.
Signed-off-by: Maxime Ripard
From: Maxime Ripard
The COEF_RDY bit is used to tell the hardware that new FIR filters
coefficients have been written to the registers and that the hardware
should take them into account starting next frame.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun
Both the backend and the frontend need the BT.601 CSC coefficients for
YUV to RGB conversion. Since the backend has a dependency on the
frontend (and not the other way round), move the coefficients there
so that both can access them without having to duplicate them.
Signed-off-by: Paul Kocialkowsk
This is the final step to indicate to the core that our driver
supports framebuffer modifiers.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/
https://bugs.freedesktop.org/show_bug.cgi?id=108937
--- Comment #7 from network...@rkmail.ru ---
(In reply to Christian König from comment #4)
> Alternatively update the applications.
>
> The problem is that the driver exposes 10bit RGB and the applications
> selects that for some reason but actu
On 05.12.2018 07:32, Laurent Pinchart wrote:
> Hi Ville,
>
> On Tuesday, 4 December 2018 21:13:20 EET Ville Syrjälä wrote:
>> On Tue, Dec 04, 2018 at 08:46:53AM +0100, Andrzej Hajda wrote:
>>> On 03.12.2018 22:38, Ville Syrjälä wrote:
On Thu, Nov 29, 2018 at 10:08:07AM +0100, Andrzej Hajda wro
Delete redundant CONFIG_DRM_ARM, and add a menu "ARM devices" to subclass
ARM device drivers.
Signed-off-by: James (Qian) Wang
---
drivers/gpu/drm/Makefile| 2 +-
drivers/gpu/drm/arm/Kconfig | 10 --
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/Make
On 11/30/18 2:42 AM, Oleksandr Andrushchenko wrote:
> From: Oleksandr Andrushchenko
>
> based frontends. Currently the frontends which implement
> similar code for sharing big buffers between frontend and
> backend are para-virtualized DRM and sound drivers.
> Both define the same way to share gra
Hi Brendan,
On 11/28/18 11:36 AM, Brendan Higgins wrote:
> Split out a couple of test cases that these features in base.c from the
> unittest.c monolith. The intention is that we will eventually split out
> all test cases and group them together based on what portion of device
> tree they test.
W
On Mon, 3 Dec 2018 at 22:24, Eric Anholt wrote:
>
> Right now, userspace doesn't do any L2T writes, but we should lay out
> our expectations for how it works.
>
> v2: Explicitly mention the VCD cache flushing requirements and that
> we'll flush the other caches before each of the CLs.
>
> Sign
On Mon, Dec 3, 2018 at 2:56 PM Sean Paul wrote:
>
> From: Sean Paul
>
> Since dpu_crtc subclasses crtc_state, we need a custom .reset hook in
> order to allocate the right amount of memory to accommodate the
> additional struct members in dpu_crtc_state. So bring it [partially]
> back.
>
> Releva
On Mon, 3 Dec 2018 at 22:24, Eric Anholt wrote:
>
> This cache was replaced with the slice accessing the L2T in the newer
> generations. Noted by Dave during review.
>
> Signed-off-by: Eric Anholt
Reviewed-by: Dave Emett
> ---
> drivers/gpu/drm/v3d/v3d_gem.c | 11 ---
> 1 file change
On 11/28/18 11:36 AM, Brendan Higgins wrote:
> This patch set proposes KUnit, a lightweight unit testing and mocking
> framework for the Linux kernel.
>
> Unlike Autotest and kselftest, KUnit is a true unit testing framework;
> it does not require installing the kernel on a test machine or in a VM
On 11/28/18 11:36 AM, Brendan Higgins wrote:
> Migrate tests without any cleanup, or modifying test logic in anyway to
> run under KUnit using the KUnit expectation and assertion API.
>
> Signed-off-by: Brendan Higgins
> ---
> drivers/of/Kconfig|1 +
> drivers/of/unittest.c | 1405 ++
On Tue, Dec 4, 2018 at 2:57 PM Fabio Estevam wrote:
>
> VXT Ltd is a manufacturer of projected capacitive touch panel
> and display solutions: http://www.vxt.com.tw/
>
> Signed-off-by: Fabio Estevam
Reviewed-by: Otavio Salvador
--
Otavio Salvador O.S. Systems
http:
Quoting Matthias Kaehlcke (2018-11-30 16:52:52)
> Add 'xo_board' as ref clock for the DSI PHYs, it was previously
> hardcoded in the PLL 'driver' for the 28nm PHY.
>
> Signed-off-by: Matthias Kaehlcke
> Reviewed-by: Douglas Anderson
> ---
Reviewed-by: Stephen Boyd
Quoting Matthias Kaehlcke (2018-12-04 09:35:49)
> On Tue, Dec 04, 2018 at 08:44:00AM -0800, Stephen Boyd wrote:
> > Quoting Matthias Kaehlcke (2018-11-30 16:52:48)
> > > +
> > > /* custom byte clock divider */
> > > struct clk_bytediv *bytediv;
> > >
> > > @@ -125,7 +127,10 @@ sta
Document the new amd,imageon compatible, used for non-qcom hardware that
uses the drm/msm driver (iMX5).
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/binding
On Mon, 3 Dec 2018 at 22:24, Eric Anholt wrote:
>
> This would be a fairly obscure race, but let's make sure we don't ever
> lose it.
>
> Signed-off-by: Eric Anholt
Reviewed-by: Dave Emett
> ---
> drivers/gpu/drm/v3d/v3d_gem.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Quoting Matthias Kaehlcke (2018-11-30 16:52:47)
> Allow the PHY drivers to get the ref clock from the DT.
>
> Signed-off-by: Matthias Kaehlcke
> ---
Reviewed-by: Stephen Boyd
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.fr
On Mon, 2018-11-26 at 17:56 +0530, Anshuman Khandual wrote:
> At present there are multiple places where invalid node number is encoded
> as -1. Even though implicitly understood it is always better to have macros
> in there. Replace these open encodings for an invalid node number with the
> global
Quoting Matthias Kaehlcke (2018-11-30 16:52:54)
> Add 'xo_board' as ref clock for the DSI PHY, it was previously
> hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Why is driver in quotes?
>
> Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
_
Quoting Matthias Kaehlcke (2018-11-30 16:52:48)
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate. Use default values if the ref
> clock is not specified.
>
> Signed-off-by: Matthias Kaehlcke
> ---
> Changes in v3:
> - use default name and rate if the r
This switches the fbtft driver to use GPIO descriptors
rather than numerical gpios:
Utilize the GPIO library's intrinsic handling of OF GPIOs
and polarity. If the line is flagged active low, gpiolib
will deal with this.
Remove gpios from platform device structure. Neither assign
statically number
A2XX has its own very simple MMU.
Added a msm_use_mmu() function because we can't rely on iommu_present to
decide to use MMU or not.
Signed-off-by: Jonathan Marek
---
v3: rebased on msm-next-staging and moved is_a2xx initialization earlier
drivers/gpu/drm/msm/Makefile | 3 +-
d
Hi Brendan, Rob,
On 11/28/18 11:36 AM, Brendan Higgins wrote:
> This patch set proposes KUnit, a lightweight unit testing and mocking
> framework for the Linux kernel.
>
> Unlike Autotest and kselftest, KUnit is a true unit testing framework;
> it does not require installing the kernel on a test
This allows controlling which of the 8 lanes are used for 6 bit color.
Signed-off-by: Jonathan Marek
---
v3: removed empty line and added documentation
.../devicetree/bindings/display/msm/mdp4.txt | 2 ++
.../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 21 ---
2 files changed,
From: Laurent Pinchart
The DRM_BUS_FLAG_PIXDATA_(POS|NEG)EDGE and
DRM_BUS_FLAG_SYNC_(POS|NEG)EDGE flags are deprecated in favour of the
new DRM_BUS_FLAG_PIXDATA_(DRIVE|SAMPLE)_(POS|NEG)EDGE and
new DRM_BUS_FLAG_SYNC_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags. Replace them
through the code.
This effectiv
On 03.12.2018 18:36, Thierry Reding wrote:
> From: Thierry Reding
>
> This code is very similar to the audio over HDMI support on older chips.
> Interoperation with the audio codec is done via a pair of codec scratch
> registers and an interrupt that is raised at the SOR when the codec has
> writ
On Mon, 3 Dec 2018 at 22:24, Eric Anholt wrote:
>
> According to Dave, once you've started an L2T flush, all L2T accesses
> will be blocked until the flush completes. This fixes a consistent
> 3-4ms stall between the ioctl and running the job, and 3DMMES Taiji
> goes from 27fps to 110fps.
>
> v2:
On 04.12.2018 16:08, Thierry Reding wrote:
> On Tue, Dec 04, 2018 at 02:09:07PM +0300, Dmitry Osipenko wrote:
>> On 03.12.2018 18:36, Thierry Reding wrote:
>>> From: Thierry Reding
>>>
>>> This code is very similar to the audio over HDMI support on older chips.
>>> Interoperation with the audio co
On Mon, Nov 26, 2018 at 01:13:08PM +0300, Dan Carpenter wrote:
> On Sun, Nov 25, 2018 at 04:56:29PM +0530, Nishad Kamdar wrote:
> > This switches the flexfb.c to use GPIO descriptors
> > rather than numerical gpios.
> >
> > Signed-off-by: Nishad Kamdar
> > ---
> > drivers/staging/fbtft/flexfb.c
Quoting Matthias Kaehlcke (2018-11-30 16:52:49)
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> index 26e3a01a99c2b..4a84c69ca0b2b 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
From: Laurent Pinchart
The DRM_BUS_FLAG_PIXDATA_POSEDGE and DRM_BUS_FLAG_PIXDATA_NEGEDGE macros
and their DRM_BUS_FLAG_SYNC_* counterparts define on which pixel clock
edge data and sync signals are driven. They are however used in some
drivers to define on which pixel clock edge data and sync sig
On Tue, Dec 4, 2018 at 2:57 PM Fabio Estevam wrote:
>
> Add support for the VXT VL050-8048NT-C01 800x480 panel to the
> panel-simple driver.
>
> This panel is used on some boards manufactured by TechNexion, such as
> imx7d-pico.
>
> Signed-off-by: Fabio Estevam
Reviewed-by: Otavio Salvador
Hello,
This patch series attemps at clarifying usage of the
DRM_BUS_FLAG_(PIXDATA|SYNC)_(POS|NEG)EDGE flags. It results from a
discussion on the mailing list available at [1].
The problem being discussed was confusion around how the
DRM_BUS_FLAG_(PIXDATA|SYNC)_POSEDGE and DRM_BUS_FLAG_(PIXDATA|SY
On Tue, Dec 4, 2018 at 2:57 PM Fabio Estevam wrote:
>
> The VXT VL050-8048NT-C01 is a TFT LCD panel with a 800x480 resolution
> connected via 24 width parallel interface.
>
> Signed-off-by: Fabio Estevam
Reviewed-by: Otavio Salvador
--
Otavio Salvador O.S. Systems
This patch allows using drm/msm without qcom display hardware. It adds a
amd,imageon compatible, which is used instead of qcom,adreno, but does
not require a top level msm node.
Signed-off-by: Jonathan Marek
---
v3: reworked to work with only a amd,imageon node
drivers/gpu/drm/msm/Kconfig
kfree(NULL) is safe, so removes NULL check before freeing the mem.
This patch also fix the ifnullfree.cocci warnings.
Signed-off-by: Wen Yang
CC: Alex Deucher
CC: christian.koe...@amd.com
CC: "David (ChunMing) Zhou"
CC: David Airlie (maintainer:DRM DRIVERS)
CC: Lyude Paul
CC: Rex Zhu
CC: Jim
Quoting Matthias Kaehlcke (2018-11-30 16:52:53)
> Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
> hardcoded in the PLL 'driver' for the 10nm PHY.
>
> Signed-off-by: Matthias Kaehlcke
> Reviewed-by: Douglas Anderson
> ---
Reviewed-by: Stephen Boyd
_
https://bugs.freedesktop.org/show_bug.cgi?id=108937
--- Comment #8 from Christian König ---
(In reply to network723 from comment #7)
> (In reply to Christian König from comment #4)
> > Alternatively update the applications.
> >
> > The problem is that the driver exposes 10bit RGB and the applica
Hi Andrzej,
On Wednesday, 5 December 2018 10:46:40 EET Andrzej Hajda wrote:
> On 05.12.2018 07:32, Laurent Pinchart wrote:
> > On Tuesday, 4 December 2018 21:13:20 EET Ville Syrjälä wrote:
> >> On Tue, Dec 04, 2018 at 08:46:53AM +0100, Andrzej Hajda wrote:
> >>> On 03.12.2018 22:38, Ville Syrjälä
From: Christian Hewitt
[ Upstream commit 31e1ab494559fb46de304cc6c2aed1528f94b298 ]
This essential mode for PAL users is missing, so add it.
Fixes: 335e3713afb87 ("drm/meson: Add support for HDMI venc modes and settings")
Signed-off-by: Christian Hewitt
Acked-by: Neil Armstrong
Signed-off-by:
Hi Dave,
Three patch series - code refactoring for simplifying DMA mapping,
enhancing plane alpha and blend mode support for Exynos5433 Decon device,
and fixing color format setting of Mixer driver.
Please kindly let me know if there is any problem.
Thanks,
Inki Dae
The following ch
From: shaoyunl
[ Upstream commit ad97d9de45835b6a0f71983b0ae0cffd7306730a ]
Driver shouldn't try to access any GFX registers until RLC is idle.
During the test, it took 12 seconds for RLC to clear the BUSY bit
in RLC_GPM_STAT register which is un-acceptable for driver.
As per RLC engineer, it wo
From: "Y.C. Chen"
[ Upstream commit 300625620314194d9e6d4f6dda71f2dc9cf62d9f ]
v1: over-sample data to increase the stability with some specific monitors
v2: refine to avoid infinite loop
v3: remove un-necessary "volatile" declaration
[airlied: fix two checkpatch warnings]
Signed-off-by: Y.C.
From: Christian Hewitt
[ Upstream commit 31e1ab494559fb46de304cc6c2aed1528f94b298 ]
This essential mode for PAL users is missing, so add it.
Fixes: 335e3713afb87 ("drm/meson: Add support for HDMI venc modes and settings")
Signed-off-by: Christian Hewitt
Acked-by: Neil Armstrong
Signed-off-by:
From: "Y.C. Chen"
[ Upstream commit 300625620314194d9e6d4f6dda71f2dc9cf62d9f ]
v1: over-sample data to increase the stability with some specific monitors
v2: refine to avoid infinite loop
v3: remove un-necessary "volatile" declaration
[airlied: fix two checkpatch warnings]
Signed-off-by: Y.C.
From: shaoyunl
[ Upstream commit ad97d9de45835b6a0f71983b0ae0cffd7306730a ]
Driver shouldn't try to access any GFX registers until RLC is idle.
During the test, it took 12 seconds for RLC to clear the BUSY bit
in RLC_GPM_STAT register which is un-acceptable for driver.
As per RLC engineer, it wo
From: "Y.C. Chen"
[ Upstream commit 300625620314194d9e6d4f6dda71f2dc9cf62d9f ]
v1: over-sample data to increase the stability with some specific monitors
v2: refine to avoid infinite loop
v3: remove un-necessary "volatile" declaration
[airlied: fix two checkpatch warnings]
Signed-off-by: Y.C.
From: "Y.C. Chen"
[ Upstream commit 300625620314194d9e6d4f6dda71f2dc9cf62d9f ]
v1: over-sample data to increase the stability with some specific monitors
v2: refine to avoid infinite loop
v3: remove un-necessary "volatile" declaration
[airlied: fix two checkpatch warnings]
Signed-off-by: Y.C.
From: "Y.C. Chen"
[ Upstream commit 300625620314194d9e6d4f6dda71f2dc9cf62d9f ]
v1: over-sample data to increase the stability with some specific monitors
v2: refine to avoid infinite loop
v3: remove un-necessary "volatile" declaration
[airlied: fix two checkpatch warnings]
Signed-off-by: Y.C.
Hi Daniel,
can I get a review for this one? It is essentially just a follow up
cleanup on one of your patches and shouldn't have any functional effect.
Thanks,
Christian.
Am 04.12.18 um 12:59 schrieb Christian König:
This completes "drm/syncobj: Drop add/remove_callback from driver
interface
Hi Stable team,
On 22/11/2018 17:01, Neil Armstrong wrote:
> Since Linux 4.17, calls to drm_crtc_vblank_on/off are mandatory, and we get
> a warning when ctrc is disabled :
> " driver forgot to call drm_crtc_vblank_off()"
>
> But, the vsync IRQ was not totally disabled due the transient hardware
On Tue, Nov 20, 2018 at 06:13:42PM +0200, Ville Syrjala wrote:
> diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c
> b/drivers/gpu/drm/i2c/tda998x_drv.c
> index a7c39f39793f..38c66fbc8276 100644
> --- a/drivers/gpu/drm/i2c/tda998x_drv.c
> +++ b/drivers/gpu/drm/i2c/tda998x_drv.c
> @@ -849,7 +849,8 @@
Em Thu, 18 Oct 2018 14:00:40 +0200
Benjamin Gaignard escreveu:
> Le mer. 17 oct. 2018 à 09:20, Christoph Hellwig a écrit :
> >
> > On Mon, Oct 15, 2018 at 11:12:55AM +0200, Benjamin Gaignard wrote:
> > > Le sam. 13 oct. 2018 à 17:18, Christoph Hellwig a écrit :
> > > >
> > > > The DMA API d
On 2018-12-04 21:21, Rob Clark wrote:
On Tue, Dec 4, 2018 at 11:56 AM Robert Foss wrote:
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
R
Hi Dave,
The vmwgfx -next changes for 4.21:
Page flip with damage by Deepak and others,
Various vmwgfx minor fixes anc cleanups.
The following changes since commit 818182dd1097fdc492aaef9b08755ea13274352d:
Merge tag 'imx-drm-next-2018-12-03' of git://git.pengutronix.de/git/pza/linux
into drm-
Hi,
On 05/12/18 10:49, Laurent Pinchart wrote:
> From: Laurent Pinchart
>
> The DRM_BUS_FLAG_PIXDATA_(POS|NEG)EDGE and
> DRM_BUS_FLAG_SYNC_(POS|NEG)EDGE flags are deprecated in favour of the
> new DRM_BUS_FLAG_PIXDATA_(DRIVE|SAMPLE)_(POS|NEG)EDGE and
> new DRM_BUS_FLAG_SYNC_(DRIVE|SAMPLE)_(POS|N
If we got an error response code from the host, print it to the log.
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/virtio/virtgpu_vq.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c
b/drivers/gpu/drm/virtio/virtgpu_vq.c
i
Sending the flush command only makes sense if we actually have
a framebuffer attached to the scanout (handle != 0).
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/virtio/virtgpu_plane.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtg
Just call drm_fence_put directly instead.
Also set vgfb->fence to NULL after dropping the reference.
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/virtio/virtgpu_drv.h | 1 -
drivers/gpu/drm/virtio/virtgpu_fence.c | 8
drivers/gpu/drm/virtio/virtgpu_ioctl.c | 2 +-
drivers/gpu/drm/
Gerd Hoffmann (3):
drm/virtio: log error responses
drm/virtio: fix pageflip flush
drm/virtio: drop virtio_gpu_fence_cleanup()
drivers/gpu/drm/virtio/virtgpu_drv.h | 1 -
drivers/gpu/drm/virtio/virtgpu_fence.c | 8
drivers/gpu/drm/virtio/virtgpu_ioctl.c | 2 +-
drivers/gpu/dr
Hi Jerome!
On Mon 03-12-18 15:18:16, jgli...@redhat.com wrote:
> From: Jérôme Glisse
>
> To avoid having to change many call sites everytime we want to add a
> parameter use a structure to group all parameters for the mmu_notifier
> invalidate_range_start/end cakks. No functional changes with th
Fixes the regression I noticed.
Tested-by: Tom St Denis
On 2018-12-05 3:38 a.m., Christian König wrote:
> Make sure we reserve at least one slot for pipelined BO moves
> during BO creation.
>
> Fixes: 5786b66c9e3b drm/ttm: drop the extra reservation for pipelined BO
> moves
>
> Signed-off-by:
Hi James,
On Wed, Dec 05, 2018 at 03:41:35AM +, james qian wang (Arm Technology
China) wrote:
> Delete redundant CONFIG_DRM_ARM, and add a menu "ARM devices" to subclass
> ARM device drivers.
>
> Signed-off-by: James (Qian) Wang
Reviewed-by: Alexandru Gheorghe
> ---
> drivers/gpu/drm/Ma
Adding a debug log when the DP_AUX_NATIVE_REPLY_ACK is missing
for aksv write. This helps to locate the possible non responding
DP HDCP sinks.
v2:
Rewritten for readability [Sean Paul]
Signed-off-by: Ramalingam C
Reviewed-by: Sean Paul
---
drivers/gpu/drm/i915/intel_dp.c | 7 ++-
1 file
Couple of more HDCP1.4 fixes on
- Key load process for CFL
- Encryption status change time
- debug log addition
- active platform coverage
v1 and v2 went into old series https://patchwork.freedesktop.org/series/38978/
as v8 and v9, due to the same series title. Now changed the title.
v3--
HDCP1.4 key load process varies between Intel platform to platform.
For Gen9 platforms except BXT and GLK, HDCP1.4 key is loaded using
the GT Driver Mailbox interface. So all GEN9_BC platforms will use
the GT Driver Mailbox interface for HDCP1.4 key load.
v2:
Using the IS_GEN9_BC for filtering
At enable/disable of the HDCP encryption, for encryption status change
we need minimum one frame duration. And we might program this bit any
point(start/End) in the previous frame.
With 20mSec, observed the timeout for change in encryption status.
Since this is not time critical operation and we n
HDCP1.4 is enabled and validated only on GEN9+ platforms.
v2:
Removed the unnecessary parens [Ville]
Signed-off-by: Ramalingam C
Reviewed-by: Sean Paul
---
drivers/gpu/drm/i915/intel_hdcp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.
On 12/5/2018 12:45 AM, Ville Syrjälä wrote:
On Tue, Dec 04, 2018 at 11:37:05PM +0530, Ramalingam C wrote:
HDCP1.4 is enabled and validated only on GEN9+ platforms.
Signed-off-by: Ramalingam C
Reviewed-by: Sean Paul
---
drivers/gpu/drm/i915/intel_hdcp.c | 3 +--
1 file changed, 1 insertion
Hi James,
On Wed, Dec 05, 2018 at 10:20:13AM +, james qian wang (Arm Technology
China) wrote:
> Signed-off-by: James (Qian) Wang
> ---
> MAINTAINERS | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 254b7b267731..9e44c2c2e234 100644
> --- a/
On 05.12.2018 11:42, Tomi Valkeinen wrote:
> Hi,
>
> On 05/12/18 10:49, Laurent Pinchart wrote:
>> From: Laurent Pinchart
>>
>> The DRM_BUS_FLAG_PIXDATA_(POS|NEG)EDGE and
>> DRM_BUS_FLAG_SYNC_(POS|NEG)EDGE flags are deprecated in favour of the
>> new DRM_BUS_FLAG_PIXDATA_(DRIVE|SAMPLE)_(POS|NEG)E
Lockless container implementation similar to a dma_fence_array, but with
only two elements per node and automatic garbage collection.
v2: properly document dma_fence_chain_for_each, add dma_fence_chain_find_seqno,
drop prev reference during garbage collection if it's not a chain fence.
v3: use
From: Chunming Zhou
points array is one-to-one match with syncobjs array.
v2:
add seperate ioctl for timeline point wait, otherwise break uapi.
v3:
userspace can specify two kinds waits::
a. Wait for time point to be completed.
b. and wait for time point to become available
v4:
rebase
v5:
add com
Use the dma_fence_chain object to create a timeline of fence objects
instead of just replacing the existing fence.
v2: rebase and cleanup
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 37 +
include/drm/drm_syncobj.h | 5 +
2 file
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