Add 10 bytes packet overhead for hblk where blank is set using
a blanking packet like (4 bytes + 4 bytes + payload + 2 bytes)
This is according to BSP code from BPI-M64-bsp (from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
dsi_hblk = (ht-hspw)*dsi_pixel_bits[format]
Current driver is calculating hfp maximum value by subtracting
htotal with hsync_end which is front back value, but the
hpp refers to front porch.
Front porch value is calculating by subtracting hsync_start with
hdisplay as per drm_mode timings, and BSP code from BPI-M64-bsp
is eventually followin
Some boards have VCC-DSI pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
MIPI DSI driver.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 14 ++
drivers/gpu/drm/
This series adds two more EDIDs that I needed for a project some time ago,
and fixes some problems that I found along the way.
There isn't a listed maintainer for Documentation/EDID but it looks
like it falls under the DRM umbrella. Please let me know if this the
wrong place.
Ben.
Ben Hutchings
The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
on the one on A31.
Add A64 compatible and append A31 compatible as fallback.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion(+)
This patch add support for Bananapi S070WV20-CT16 DSI panel to
BPI-M64 board.
DSI panel connected via board DSI port with,
- DC1SW as AVDD supply
- DCDC1 as DVDD supply
- PD6 gpio for reset pin
- PD5 gpio for backlight enable pin
- PD7 gpio for backlight vdd supply
Signed-off-by: Jagan Teki
---
hblk is adding line with all porch timing values, or timings
values from htotal without sync time.
Current driver is subtracting htotal with hsa, but the hsa
is bounded with packet overhead. For real hblk calculation
needed by subtracting htotal with back and front porch values
and BSP code BPI-M6
This should match standard HDTV 720p 60 Hz timings.
Signed-off-by: Ben Hutchings
---
Documentation/EDID/1280x720.S | 45 +++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/EDID/1280x720.S
diff --git a/Documentation/EDID/1280x720.S b/Do
Add support for Allwinner A64 has Mali-400MP2.
All interrupt lines are mentioned in the manual so used the same.
Used 408MHz as assigned clock rate used by BSP, so used the same as
well.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Drop assigned clock properties
- Separate dt-bindings as sepa
Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB
bridge panel, which is available on same PCB with 24-bit RGB interface.
So, this patch adds DSI specific binding details on existing
dt-bindings file.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
.../display/panel/bana
On 2018-11-13 18:24, Russell King - ARM Linux wrote:
> On Tue, Nov 13, 2018 at 01:28:40PM +, Peter Rosin wrote:
>> Hi!
>>
>> I'm wondering about some programming details regarding the TDA998x
>> driver...
>>
>> The bindings documentation [1] state that one should fill in the
>> desired register
Mod clock is not mandatory for all Allwinner MIPI DSI
controllers, it is connected as CLK_DSI_SCLK for A31
and not available in A64.
So add has_mod_clk quirk and process the clk accordingly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 39 ++
dr
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
LCD panel. Add dt-bingings for it.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
.../display/panel/techstar,ts8550b.txt| 22 +++
1 file changed, 22 insertions(+)
create mode 100644
Documentation/devic
Manual noted to use PLL_MIPI rate 500MHz to 1.4GHz,
but lowering the min rate by 300MHz can result proper
working nkms divider with the help of desired dclock
rate from panel driver.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
1 file change
Most of the Allwinner MIPI DSI controllers are supply with
VCC-DSI pin. which need to supply for some of the boards to
trigger the power.
So, document the supply property so-that the required board
can eable it via device tree.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/dis
Current driver is calculating hbp maximum value by subtracting
hsync_start with hdisplay which is front porch value, but the
hbp refers to back porch.
Back porch value is calculating by subtracting htotal with
hsync_end as per drm_mode timings, and BSP code from BPI-M64-bsp
is eventually following
Currently we fail to encode any of these fields correctly if they
are large enough to require the top 2 bits. Thankfully none of
the EDID sources here are affected.
The masking and shifting of the top 2 bits (out of 10 for X, 6 for Y)
is only needed in one place so remove the msbs4() macro.
Sign
Some NKM PLLs doesn't work well when their output clock rate is set below
certain rate.
So, add support for minimal rate for relevant PLLs.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu_nkm.c | 3 +++
drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
2 files changed, 4 inse
Allwinner PWM support need for ARM64 Allwinner SoC's
which used pwms, builds it as module.
Signed-off-by: Jagan Teki
---
Changes for v6:
- none
Changes for v5:
- new patch
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/
Hiding all commands is unhelpful unless there's some way to override
it (e.g. Kbuild's V=1). The -s option is available for those who like
it.
Signed-off-by: Ben Hutchings
---
Documentation/EDID/Makefile | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentat
Allwinner SoC like SUN8I and SUN50I has DE2 CCU so enable them
as default.
Signed-off-by: Jagan Teki
---
Changes for v6:
- droped "depends on" since the CCU select based on MACH defined.
Changes for v5:
- remove DRM dependency
Changes for v4, v3:
- none
Changes for v2:
- Enable for MACH_SUN8I
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
LCD panel. Add panel driver for it.
Signed-off-by: Jagan Teki
---
MAINTAINERS | 6 +
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile| 1 +
.../g
The A64 has a MIPI-DSI block which is similar to A31
without mod clock.
So, add dsi node with A64 compatible, dphy node with
A31 compatible and finally connect dsi to tcon0 to
make proper DSI pipeline.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45
Amarula A64-Relic board by default bound with Techstar TS8550B
MIPI-DSI panel, add support for it.
DSI panel connected via board DSI port with,
- DC1SW as AVDD supply
- DCDC2 as DVDD supply
- DCDC1 as VCC-DSI supply
- PD24 gpio for reset pin
- PD23 gpio for backlight enable pin
Signed-off-by: Jag
Some NKM PLLs, frequency can be set above PLL working range.
Add a constraint for maximum supported rate. This way, drivers can
specify which is maximum allowed rate for PLL.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu_nkm.c | 3 +++
drivers/clk/sunxi-ng/ccu_n
Unlike hblk, the vblk timings should follow an equation to compute
the desired value for lane 4 devices and rest of devices it would be 0.
BSP code from BPI-M64-bsp is computing vblk as for 4-lane devices
(from linux-sunxi
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
tmp = (ht*ds
The horizontal and vertical back porch calculation in BSP
code is simply following the Linux drm comment diagram, in
include/drm/drm_modes.h which is
[hv]back porch = [hv]total - [hv]sync_end
BSP code form BPI-M64-bsp is calculating vertical back porch as
(from linux-sunxi/drivers/video/sunxi/dis
Hi Thomas,
On Tue, 13 Nov 2018 10:23:45 +0100, Thomas Zimmermann wrote:
> ast doesn't remove the vesafb's framebuffer before attaching to the
> device. I have a patch at [1]. If you have a way of testing it, I'd
> appreciate.
>
> [1] https://bugzilla.suse.com/show_bug.cgi?id=1112963
Thank you ve
Allwinner A64 has Mali-400MP2, so document the relevant compatible
as "allwinner,sun50i-a64-mali"
Signed-off-by: Jagan Teki
---
Changes for v2:
- New patch, separated from previous version patch.
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 1 +
1 file changed, 1 insertion(+)
di
On 2018-11-13 20:09, Russell King - ARM Linux wrote:
> On Tue, Nov 13, 2018 at 06:12:37PM +, Peter Rosin wrote:
>> On 2018-11-13 18:24, Russell King - ARM Linux wrote:
>>> On Tue, Nov 13, 2018 at 01:28:40PM +, Peter Rosin wrote:
Hi!
I'm wondering about some programming detail
Short transfer write support for DCS and Generic transfer types
share similar way to process command sequence in DSI block so
add generic write 2 param transfer type macro so-that the panels
which are requesting similar transfer type may process properly.
Signed-off-by: Jagan Teki
---
drivers/gp
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetre
TCON DRQ set bits for non-burst DSI mode can computed via
horizontal front porch instead of front porch + sync timings.
BSP code form BPI-M64-bsp is computing TCON DRQ set bits
for non-burts as (from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
=> panel->lcd_ht -
From: Kuninori Morimoto
This patch updates license to use SPDX-License-Identifier
instead of verbose license text.
Signed-off-by: Kuninori Morimoto
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/b
On Tue, Nov 13, 2018 at 5:52 PM Andre Przywara wrote:
>
> On Tue, 13 Nov 2018 16:46:32 +0530
> Jagan Teki wrote:
>
> Hi,
>
> > This patch add support for Bananapi S070WV20-CT16 DSI panel to
> > BPI-M64 board.
> >
> > DSI panel connected via board DSI port with,
> > - DC1SW as AVDD supply
>
> Are
Video start delay can be computed by subtracting total vertical
timing with front porch timing and with adding 1 delay line for TCON.
BSP code form BPI-M64-bsp is computing video start delay as
(from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
u32 vfp = panel->lcd_v
DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu-sun
This is one of several modes sometimes called WXGA.
Signed-off-by: Ben Hutchings
---
Documentation/EDID/1280x768.S | 45 +++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/EDID/1280x768.S
diff --git a/Documentation/EDID/1280x768.S b/Do
Allwinner DesignWare HDMI is needed for HDMI support
in ARM64 Allwinner SoC's, build it as module.
Signed-off-by: Jagan Teki
---
Changes for v6:
- none
Changes for v5:
- Enable it on defconfig
Changes for v4:
- none
Changes for v3:
- skip SUN8I enablement, since it built statically for arm32
Chan
It appears that the range of the vertical sync offset and pulse (0-63)
was typo'd as '-63)' and this led to writing code that subtracts 63
from each of the field values. This is not the case, and all the EDID
sources counteract it by adding 63 to YOFFSET and YPULSE. Remove the
additions and subtr
Allwinner A64 has Mali-400MP2, so document the relevant compatible
as "allwinner,sun50i-a64-mali" along with reset line.
Signed-off-by: Jagan Teki
---
Changes for v3:
- document reset line
Changes for v2:
- New patch, separated from previous version patch.
Documentation/devicetree/bindings/gpu/
Allwinner Display Engine 2.0 Mixer is need for ARM64
Allwinner SoC's, build it as module.
Signed-off-by: Jagan Teki
---
Changes for v6:
- none
Changes for v5:
- Enable it on defconfig
Changes for v4, v3:
- none
Changes for v2:
- Enable for SUN8I
arch/arm64/configs/defconfig | 1 +
1 file change
This series fixed the issues related to work DSI on 2-lane panel
which is reported on previous version[1].
This supposed to be a clean series, where it support Allwinner A64 MIPI-DSI
support for 4-lane, 2-lane DSI panels.
This series fixed all previous series comments along with checkpatch
warnin
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
So, alter has_mod_clk bool via driver data for respective
SoC's compatible.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 +++
1 file changed, 7 ins
Hi!
I'm wondering about some programming details regarding the TDA998x
driver...
The bindings documentation [1] state that one should fill in the
desired register content of the AP_ENA register. However, I cannot
find any details anywhere about how one determines what is desired.
When I look for
Add support for Allwinner A64 has Mali-400MP2.
All interrupt lines are mentioned in the manual so used the same.
Signed-off-by: Jagan Teki
---
Changes for v3:
- Clean commit message
Changes for v2:
- Drop assigned clock properties
- Separate dt-bindings as separate patch.
arch/arm64/boot/dts/
Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB bridge
panel which can be used to connect via DSI port on BPI-M64 board,
so add a driver for it.
The same panel PCB comes with parallel RBG which is supported via
panel-simple driver with "bananapi,s070wv20-ct16" compatible.
BSP dc
On Wed, Nov 7, 2018 at 9:46 AM Frank Rowand wrote:
>
> On 11/6/18 5:17 PM, Brendan Higgins wrote:
> > On Fri, Nov 2, 2018 at 11:23 AM Shuah Khan wrote:
> >>
> >> Hi Brendan,
> >
> >> Framework looks good. I think it would be helpful to include a real test
> >
> > Great to hear!
> >
> >> in the p
On Tue, 2018-11-13 at 16:40 +, Chris Wilson wrote:
> Quoting Stanislav Lisovskiy (2018-11-13 14:31:38)
> > Currently whenever we attempt to recalculate
> > watermarks, we assign dirty_pipes to zero,
> > then compare current wm results to the recalculated
> > one and if they changed we set corre
struct drm_plane_state *new_state)
> +{
> + struct vop *vop = to_vop(plane->state->crtc);
> +
> + plane->state->crtc_x = new_state->crtc_x;
> + plane->state->crtc_y = new_state->crtc_y;
> + plane->state->crtc_h
Hello Heiko,
On Fri, Nov 09, 2018 at 10:48:57AM +0100, Heiko Stuebner wrote:
> Commit e6bcca0890b9 ("backlight: pwm_bl: Switch to using "atomic" PWM API")
> removed the driver internal enabled tracking in favor of simply checking
> the pwm state.
>
> This can lead to issues as all of gpio-, regul
On Wed, Nov 14, 2018 at 2:58 PM Chen-Yu Tsai wrote:
>
> On Wed, Nov 14, 2018 at 2:31 PM Jagan Teki wrote:
> >
> > On Tue, Nov 13, 2018 at 5:52 PM Andre Przywara
> > wrote:
> > >
> > > On Tue, 13 Nov 2018 16:46:32 +0530
> > > Jagan Teki wrote:
> > >
> > > Hi,
> > >
> > > > This patch add suppor
https://bugs.freedesktop.org/show_bug.cgi?id=102909
--- Comment #2 from Pander ---
>From https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1707695 , what would
be an workaround until this bug is fixed for Ubuntu 18.10 / kernel
4.18.0-10-generic ?
Perhaps also link related bugs from
https://bu
https://bugs.freedesktop.org/show_bug.cgi?id=99195
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--- Comment #7 from Pander ---
Same issue with Radeon HD 5970 for mesa 18.2.2
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--- Comment #1 from Pander ---
Same issue with Radeon HD 5970 for mesa 18.2.2
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Chí-Thanh Christopher Nguyễn changed:
What|Removed |Added
Status|RESOLVED|REOPENED
Resolut
On Tue, 13 Nov 2018, Ben Hutchings wrote:
> This series adds two more EDIDs that I needed for a project some time ago,
> and fixes some problems that I found along the way.
See also [1]. The patches there have been applied via the linux-doc
tree.
> There isn't a listed maintainer for Documentati
Hi Kishon
On Mon, Nov 12, 2018 at 03:32:25PM +0530, Kishon Vijay Abraham I wrote:
> On 06/11/18 8:24 PM, Maxime Ripard wrote:
> > The phy framework is only allowing to configure the power state of the PHY
> > using the init and power_on hooks, and their power_off and exit
> > counterparts.
> >
>
On Wed, 14 Nov 2018, pr-tracker-...@kernel.org wrote:
> The pull request you sent on Sun, 11 Nov 2018 04:43:57 +1000:
>
>> git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2018-11-11
>
> has been merged into torvalds/linux.git:
> https://git.kernel.org/torvalds/c/20ef6d06ef9a31a33516637a80521b9
On Wed, Nov 14, 2018 at 08:19:26AM +, Lisovskiy, Stanislav wrote:
> On Tue, 2018-11-13 at 16:40 +, Chris Wilson wrote:
> > Quoting Stanislav Lisovskiy (2018-11-13 14:31:38)
> > > Currently whenever we attempt to recalculate
> > > watermarks, we assign dirty_pipes to zero,
> > > then compare
After adding the hs_rate and lp_rate fields to the DSI device
we need to populate these accordingly so display drivers can
respect them.
This figure for HS rate comes from the ILI9881C manual, the
calculation is explained in the comment.
Cc: Daniel Vetter
Cc: Andrzej Hajda
Cc: Maxime Ripard
Si
https://bugs.freedesktop.org/show_bug.cgi?id=108704
--- Comment #3 from adamcart...@gmail.com ---
FYI the patch did fix the same issue for me with an R9 380
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After adding the hs_rate and lp_rate fields to the DSI device
we need to populate these accordingly so display drivers can
respect them.
Cc: Andrzej Hajda
Cc: Chris Zhong
Cc: Lin Huang
Cc: Heiko Stuebner
Signed-off-by: Linus Walleij
---
drivers/gpu/drm/panel/panel-innolux-p079zca.c | 3 +++
https://bugs.freedesktop.org/show_bug.cgi?id=108671
--- Comment #4 from coolo...@gmail.com ---
This occurs on the latest official arch linux kernel update.
4.19.1-arch1-1-ARCH
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https://bugs.freedesktop.org/show_bug.cgi?id=108671
--- Comment #6 from coolo...@gmail.com ---
Created attachment 142463
--> https://bugs.freedesktop.org/attachment.cgi?id=142463&action=edit
xorg log
the whole drm driver completely crashed and the system refused to even poweroff
a few seconds b
https://bugs.freedesktop.org/show_bug.cgi?id=108671
--- Comment #5 from coolo...@gmail.com ---
Created attachment 142462
--> https://bugs.freedesktop.org/attachment.cgi?id=142462&action=edit
dmesg
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On Mon, Nov 12, 2018 at 05:51:53PM +0100, Robert Foss wrote:
>
> This series implements fence support for drm/virtio and
> has been tested using qemu, kmscube and the below branches.
>
> Rob Herring solved a reference counting issue and
> suggested a context check for the execbuf ioctl, his
> cha
On Wed, Nov 14, 2018 at 12:17:11PM +0100, Linus Walleij wrote:
> After adding the hs_rate and lp_rate fields to the DSI device
> we need to populate these accordingly so display drivers can
> respect them.
>
> This figure for HS rate comes from the ILI9881C manual, the
> calculation is explained i
On Wed, Nov 07, 2018 at 08:31:22PM +, Colin King wrote:
> From: Colin Ian King
>
> The allocation for vfpriv is being leaked on an error return path,
> fix this by kfree'ing it before returning.
>
> Detected by CoverityScan, CID#1475380 ("Resource Leak")
Patches added to qemu queue, should
On Sat, Nov 10, 2018 at 03:44:46AM +, YueHaibing wrote:
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/qxl/qxl_object.c: In function 'qxl_bo_kunmap_atomic_page':
> drivers/gpu/drm/qxl/qxl_object.c:189:21: warning:
> variable 'map' set but not used [-Wunused-but-set-varia
Otherwise, mmap fails when done with PROT_WRITE.
Suggested-by: Gurchetan Singh
Signed-off-by: Gerd Hoffmann
---
drivers/dma-buf/udmabuf.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma-buf/udmabuf.c b/drivers/dma-buf/udmabuf.c
index e70328ab7e..d9ff246093 100644
--- a/drivers/d
On Fri, Nov 09, 2018 at 10:48:57AM +0100, Heiko Stuebner wrote:
> Commit e6bcca0890b9 ("backlight: pwm_bl: Switch to using "atomic" PWM API")
> removed the driver internal enabled tracking in favor of simply checking
> the pwm state.
>
> This can lead to issues as all of gpio-, regulator- and pwm-
This reverts commit 9a09a42369a4a37a959c051d8e1a1f948c1529a4.
The whole interface isn't thought through. Since this function can't
fail we actually can't allocate an object to store the sync point.
Sorry, I should have taken the lead on this from the very beginning and
reviewed it more thoughtful
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