On Thu, Oct 25, 2018 at 05:09:29PM +0200, Alex Gonzalez wrote:
> Alex Gonzalez (4):
> drm/panel: simple: Add AUO G101EVN010 panel support
> ARM: dts: ccimx6ulsbcpro: Enable AUO G101EVN010 lcdif panel
> ARM: imx_v6_v7_defconfig: Select TOUCHSCREEN_GOODIX
> ARM: dts: ccimx6ulsbcpro: Add suppo
https://bugs.freedesktop.org/show_bug.cgi?id=108649
Bug ID: 108649
Summary: On Vega GPU Project CARS 2 Demo cause broke fonts in
gnome-shell
Product: DRI
Version: XOrg git
Hardware: Other
OS: All
https://bugs.freedesktop.org/show_bug.cgi?id=108649
--- Comment #1 from mikhail.v.gavri...@gmail.com ---
Created attachment 142361
--> https://bugs.freedesktop.org/attachment.cgi?id=142361&action=edit
screenshot 2
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https://bugs.freedesktop.org/show_bug.cgi?id=108649
--- Comment #2 from mikhail.v.gavri...@gmail.com ---
Link to game: https://store.steampowered.com/app/737770/
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dri-devel mai
https://bugs.freedesktop.org/show_bug.cgi?id=108641
--- Comment #1 from steelwin...@gmail.com ---
If it's of any help, I have managed to narrow down the first output appearance
of these interlacing lines between events glDispatchCompute(80, 45, 1) and
second call of glDrawElementsBaseVertex(48).
https://bugs.freedesktop.org/show_bug.cgi?id=108625
--- Comment #8 from Carsten Haitzler ---
Actually no ogl client has even started. this is just the xserver being started
by slim (login manager) and that doesn't use OGL. it's really basic xlib stuff.
so it is basically a raw xserver... perhaps
https://bugs.freedesktop.org/show_bug.cgi?id=108514
--- Comment #8 from Werner Lueckel ---
more tests with flickering screen:
- check modelines "xvidtune -show -display :0"
14.04 trusty (NO flickering)
"1680x1050" 122.00 1680 1712 1776 1904 1050 1051 1054 1066 -hsync -vsync
18.04.1 LTS (Fl
https://bugs.freedesktop.org/show_bug.cgi?id=108514
--- Comment #9 from Werner Lueckel ---
(In reply to Alex Deucher from comment #1)
> Any chance you can narrow down when the regression occurred and bisect it
> using git? Please attach your dmesg output and xorg log (if using X).
I tried to na
https://bugs.freedesktop.org/show_bug.cgi?id=108514
--- Comment #10 from Werner Lueckel ---
(In reply to Alex Deucher from comment #1)
> Any chance you can narrow down when the regression occurred and bisect it
> using git? Please attach your dmesg output and xorg log (if using X).
... sorry, b
https://bugs.freedesktop.org/show_bug.cgi?id=108625
--- Comment #9 from Alex Deucher ---
(In reply to Carsten Haitzler from comment #8)
> Actually no ogl client has even started. this is just the xserver being
> started by slim (login manager) and that doesn't use OGL. it's really basic
> xlib st
https://bugzilla.kernel.org/show_bug.cgi?id=200645
--- Comment #9 from Duncan (1i5t5.dun...@cox.net) ---
Regression still alive on 4.19.0-12838-g71e560281 (which I believe is a day
before 4.20-rc1).
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Pine H64 board has HDMI type A connector.
Signed-off-by: Jernej Skrabec
---
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 25 +++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-
From: Icenowy Zheng
The Allwinner H6 SoC uses a v2.12a DesignWare HDMI controller, with
dedicated CEC and HDCP clocks added; the PHY connected is a standard
DesignWare HDMI PHY.
Add binding for it.
Reviewed-by: Rob Herring
Signed-off-by: Icenowy Zheng
[added HDCP clock and reset]
Signed-off-b
It turns out that TCON TOP registers in H6 SoC have non-zero reset
value. This may cause issues if bits are not changed during
configuration.
To prevent that, initialize registers to 0.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 7 +++
1 file changed, 7 inser
Mixer 0 has 1 VI and 3 UI planes, scaler on all planes and can output
4K image @60Hz. It also support 10 bit colors, which are not yet
implemented.
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 +
1 file changed, 13 insertions(+
This commit adds compatibles used in H6 display pipeline, namely for
display engine, mixer and TV TCON.
H6 display engine is somewhat similar to R40, just less TCONs and
mixer support more features.
Reviewed-by: Rob Herring
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Jernej Skrabec
---
.../devic
From: Icenowy Zheng
Some SoCs, such as H6, doesn't have a full-featured TCON TOP.
Add quirks support for TCON TOP.
Currently the presence of TCON_TV1 and DSI is controlled via the quirks
structure.
Acked-by: Maxime Ripard
Signed-off-by: Icenowy Zheng
[Fixed code style and removed unnecessary
H6 has Synopsys DWC HDMI 2.0 TX PHY.
There is no freely available documentation for it, only code found in
BSP kernel. However, judging by the code, PHY is very similar to older
Synopsys HDMI PHY described in i.MX6 documentation. Most registers seem
to be the same.
According to i.MX6 documentatio
Currently MP clocks don't consider adjusting parent rate even if they
are allowed to do so. Such behaviour considerably lowers amount of
possible rates, which is very inconvenient when such clock is used for
pixel clock, for example.
In order to improve the situation, adjusting parent rate is cons
Most, if not all, registers found in DE2 still exists in DE3. However,
units are on different base addresses.
To prepare for addition of DE3 support, registers macros are reworked so
they take base address as parameter.
Signed-off-by: Jernej Skrabec
[rebased]
Signed-off-by: Icenowy Zheng
---
d
Video PLL factors can be set in a way that final PLL rate is outside
stable range. H6 user manual specifically says that N factor should not
be below 12. While it doesn't says anything about maximum stable rate, it
is clear that PLL doesn't work at 6.096 GHz (254 * 24 MHz).
Set minimum allowed PLL
Hi, Jagan,
On 11/3/18 1:08 PM, Jagan Teki wrote:
Loop N1 instruction delay for burst mode lcd panel are
computed as per BSP code.
Reference code is available in BSP
(in drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
dsi_dev[sel]->dsi_inst_loop_num.bits.loop_n1=
(panel->lcd_ht-pan
Allwinner H6 SoC has multiplier N range between 1 and 254. Since parent
rate is 24MHz, intermediate result when calculating final rate easily
overflows 32 bit variable.
Because of that, introduce function for calculating clock rate which
uses 64 bit variable for intermediate result.
Fixes: 6174a1
This commit adds necessary description and dt includes for H6 DE3 clock.
It is very similar to others, but memory region has some additional
registers not found in DE2.
Reviewed-by: Rob Herring
Signed-off-by: Jernej Skrabec
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++--
in
Currently sun8i-hdmi-phy driver supports only custom PHYs connected to
DW HDMI controller. Since newest Allwinner SoCs have unmodified Synopsys
PHY, driver has to be reorganized to support them.
Variant structure is expanded to allow differentiation between custom
and Sysnopsys PHYs and to hold Sy
To be exact, the issue does not happen in case I use default kernel
config but only with the custom one.
On 10/2/18 2:14 PM, Noralf Trønnes wrote:
Den 01.10.2018 21.45, skrev Noralf Trønnes:
Sergey Suloev reported a crash happening in drm_client_dev_hotplug()
when fbdev had failed to registe
This doesn't seem to fix the initially reported issue. The problem still
exists with 4.19.
On 10/2/18 2:14 PM, Noralf Trønnes wrote:
Den 01.10.2018 21.45, skrev Noralf Trønnes:
Sergey Suloev reported a crash happening in drm_client_dev_hotplug()
when fbdev had failed to register.
[ 9.1245
Currently supported Allwinner SoCs with DW HDMI controller have
scrambled addresses and read lock. However, that is not true in general.
For example, A80 and H6 have normal addresses and normal read access.
Move code for unscrambling addresses and unlocking read access to it's
own function and cal
It turns out that even new DW HDMI controllers exhibits same magenta
line issues as older versions.
Enable workaround for v2.12a.
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gp
DE2 mixer is always 0x6000 bytes in size on all known SoCs.
While at it, introduce a macro for that.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 2 +-
drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gp
From: Icenowy Zheng
Allwinner H6 SoC has a cut down version of TCON TOP.
Add binding documentation for it.
Reviewed-by: Rob Herring
Signed-off-by: Icenowy Zheng
[expanded description]
Signed-off-by: Jernej Skrabec
---
.../bindings/display/sunxi/sun4i-drm.txt | 14 --
1
My Thinkpad X32 (r100, Mobility M6) can't suspend or hibernate
with KMS using the "radeon" driver. "radeonfb" and the VESA
fallback (no KMS) are both fine.
It seems to be the same bug as:
https://bugs.freedesktop.org/show_bug.cgi?id=38554
http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=583120
T
On Sat, Nov 3, 2018 at 8:53 PM Sergey Suloev wrote:
>
> Hi, Jagan,
>
> On 11/3/18 1:08 PM, Jagan Teki wrote:
> > Loop N1 instruction delay for burst mode lcd panel are
> > computed as per BSP code.
> >
> > Reference code is available in BSP
> > (in drivers/video/sunxi/disp2/disp/de/lowlevel_sun50i
This commit adds all entries needed for HDMI to function properly.
Signed-off-by: Jernej Skrabec
[added DE3 bus]
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 201 +++
1 file changed, 201 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner
From: Icenowy Zheng
The TCON TOP on Allwinner H6 SoC is a cut down version of the R40 TCON
TOP, which dropped TCON_TV1 and DSI (which do not exist on H6).
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 8
1 file changed, 8 insertions(+)
It turns out that H6 HDMI BSP kernel driver doesn't change TMDS rate at
all. At this point it is not clear whether it is just not necessary or
it would cause some kind of issues.
Add a quirk for it.
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Jernej Skrabec
---
drivers/gp
H6 is first Allwinner SoC which supports 10 bit colors, HDR and AFBC.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 1e41c3f5fd6d..1ca7b70cbbfa 10
Support for mixer0, mixer1, writeback and rotation units is added.
Signed-off-by: Jernej Skrabec
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 71 ++--
drivers/clk/sunxi-ng/ccu-sun8i-de2.h | 4 +-
2 files changed, 71 insertions(+), 4 deletions(
On Sat, Nov 03, 2018 at 03:38:51PM +0530, Jagan Teki wrote:
> Loop N1 instruction delay for burst mode lcd panel are
> computed as per BSP code.
>
> Reference code is available in BSP
> (in drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
> dsi_dev[sel]->dsi_inst_loop_num.bits.loop_n1
Display Engine 3 is an upgrade of DE2 with new features like support for
10 bit color formats and support for AFBC.
Most of DE2 code works with DE3, except some small details.
Implement basic support for DE3. Support for 10 bit colort formats and
AFBC, among others missing features, will be added
This series adds support for Display Engine 3.0 and HDMI 2.0a, which
can be found on H6 SoC.
Display Engine 3.0 in comparison to 2.0 mostly adds features needed for
displaying and processing 10-bit and AFBC formats, which are not yet
supported by this series.
H6 is also the first SoC which suppor
From: Icenowy Zheng
The Allwinner H6 DE3 bus is similar to the A64 DE2 one.
Add its compatible string with the A64 string as fallback to the
binding.
Some description of the binding is modified to make it more generic.
Reviewed-by: Rob Herring
Signed-off-by: Icenowy Zheng
[Fixed compatible n
Currently, quirks and compatibles are sorted alphabetically. However,
they should be sorted by family release date and then alphabetically.
Fix that by moving A64 quirks and compatible to bottom. No functional
change is made.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_hdmi_ph
Some sub-engines are unused. Disable them explicitly.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 8
drivers/gpu/drm/sun4i/sun8i_mixer.h | 4 ++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/g
H6 has DW HDMI 2.0b controller v2.12a.
It supports 4K at 60 Hz and HDCP 2.2.
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
b/drive
On 10/31/2018 5:06 PM, Lorenzo Pieralisi wrote:
> On Wed, Oct 31, 2018 at 12:17:50PM +, Leonard Crestez wrote:
>> On 10/31/2018 8:12 AM, Shawn Guo wrote:
>>> On Mon, Oct 08, 2018 at 06:06:23PM +, Leonard Crestez wrote:
This was implemented in the driver but not actually defined and
>>>
Since it is not possible to access sun8i-dw-hdmi driver private data
inside mode_valid function, make it configurable. That way different
versions of HDMI controllers can set different function, depending on
it's limitations.
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Jernej Skrabec
---
drivers/g
Hi Jagan.
Reading through the driver triggered a few comments.
Read and decide what is usefull.
Sam
> Add panel driver for it.
>
> Signed-off-by: Jagan Teki
> ---
> Note: init sequence is referenced from
> https://github.com/longsleep/linux-pine64/blob/pine64-hacks-1.2/drivers/video/s
https://bugzilla.kernel.org/show_bug.cgi?id=201273
--- Comment #8 from quirin.blae...@freenet.de ---
I have replaced HDMI-cable by displayport about 2 weeks ago. No bug visible.
(Firmware update about 1 week ago).
Maybe HDMI is broken or implementation in monitors/graphics board is bad or
cables a
> > On Thu, 25 Oct 2018 at 19:38, Robert Foss wrote:
> > >
> > > From: Gustavo Padovan
> > >
> > > Refactor fence creation to remove the potential allocation failure from
> > > the cmd_submit and atomic_commit paths. Now the fence should be allocated
> > > first and just after we should proceed
On 02.11.2018 19:25, Jordan Crouse wrote:
> Devices that are bound as components should not use devm since
> device managed memory is not freed when the component is
> unbound.
>
> In particular this is an issue if the compoent bind fails
> due to an -EPROBE_DEFER. In this case the bind would try a
https://bugzilla.kernel.org/show_bug.cgi?id=201439
fin4...@hotmail.com changed:
What|Removed |Added
Kernel Version|drm-next-4.21-wip |4.20-rc1,
|
https://bugs.freedesktop.org/show_bug.cgi?id=108652
Bug ID: 108652
Summary: I suspect that in kernel 4.19 power limit decreased in
4 times on Vega GPU
Product: DRI
Version: XOrg git
Hardware: Other
OS: All
On 11/2/2018 7:07 PM, Koenig, Christian wrote:
Am 02.11.18 um 14:25 schrieb Sharat Masetty:
On 11/2/2018 4:09 PM, Koenig, Christian wrote:
Am 02.11.18 um 11:31 schrieb Sharat Masetty:
Add an optional backend function op which will let the scheduler
clients
know when the timeout got schedul
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