Am 04.09.2018 um 06:04 schrieb zhoucm1:
On 2018年09月03日 19:19, Christian König wrote:
Am 03.09.2018 um 12:07 schrieb Chunming Zhou:
在 2018/9/3 16:50, Christian König 写道:
Am 03.09.2018 um 06:13 schrieb Chunming Zhou:
在 2018/8/30 19:32, Christian König 写道:
[SNIP]
+
+struct drm_syncobj_
From: Jagan Teki
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
Signed-off-by: Jagan Teki
Signed-off-by: Icenowy Zheng
Reviewed
vexpress_muxfpga_match needs NULL terminate, fix it.
Signed-off-by: Ding Xiang
---
drivers/gpu/drm/pl111/pl111_vexpress.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/pl111/pl111_vexpress.c
b/drivers/gpu/drm/pl111/pl111_vexpress.c
index a534b22..5fa0441
On Wed 15 Aug 22:23 PDT 2018, kgu...@codeaurora.org wrote:
> On 2018-08-07 10:53, Bjorn Andersson wrote:
> > On Mon 09 Jul 03:22 PDT 2018, Kiran Gunda wrote:
> > > diff --git
> > > a/Documentation/devicetree/bindings/leds/backlight/qcom-wled.txt
> > > b/Documentation/devicetree/bindings/leds/backl
Allwiner SoCs with DesignWare HDMI controller all come with a "HVCC"
pin, which is the VCC of HDMI part.
Add a supply property to specify HVCC's regulator in the device tree.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rename the supply name to "hvcc".
Changes in v3.1:
- New patch.
Docum
It is used to be believed that the A64 HDMI PHY has the PLL-VIDEO mux
which is introduced in R40, because A64 has two PLL-VIDEOs. However,
experiments show that the mux is not present in A64, so the compatible
string of dual-PLL-input HDMI PHY clock must be changed to use R40 in
it rather than A64.
We have introduce new return type vm_fault_t for
fault handler. Update the document for the same.
Signed-off-by: Souptick Joarder
---
v2: Revert spaces added in v1
Documentation/gpu/drm-mm.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/gpu/drm-mm.rst b/Doc
The Allwinner A64 SoC is proven to have no PLL-VIDEO mux in the HDMI PHY
clock, although it has two PLL-VIDEOs. The R40 SoC has this mux.
Change the binding compatible string from sun50i-a64 to sun8i-r40, and
let A64 to use H3 compatible string.
The compatible string is introduced in v4.19, and d
From: Jagan Teki
Enable all necessary device tree nodes and add connector node to device
trees for all supported A64 boards with HDMI.
Signed-off-by: Jagan Teki
[Icenowy: squash all board patches altogether and change supply name]
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rebase some d
Allwinner A64 has display engine pipeline like other Allwinner SOC's A83T/H3/H5.
A64 behaviour similar to Allwinner A83T where
Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
Mixer1 => TCON1 => HDMI
as per Display System Block Diagram from the A64 user manual.
This patchset adds support for the two display
By experiment, the A64 HDMi PHY doesn't support the PLL-VIDEO mux
introduced in R40, although it has two PLL-VIDEOs.
Change the A64 HDMI PHY binding to R40 one.
This binding is introduced in v4.19, which is still in RC stage, so we
have change to fix it.
Signed-off-by: Icenowy Zheng
---
.../de
On Mon, 2018-08-27 at 14:02 +0200, Philipp Zabel wrote:
> Hi Leonard,
>
> On Mon, 2018-08-27 at 14:10 +0300, Leonard Crestez wrote:
> > Adding lcdif nodes to a power domain currently doesn't work, it results
> > in black/corrupted screens or hangs. While the driver does enable
> > runtime pm it do
From: Jagan Teki
The HDMI controller on Allwinner A64 is similar on the one on
H3/H5/A83T (although the PHY is different with A83T).
Add A64 compatible and append A83T compatible as fallback.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
[Icenowy: refactor commit log]
Signed-off-by: Icen
This is a respin with a wider audience (all that get_maintainer returned)
and I know this spams a *lot* of people. Not sure what would be the correct
way, so my apologies for ruining your inbox.
The 00-INDEX files are supposed to give a summary of all files present
in a directory, but these files
Video PLLs on A64 can be set to higher rate that it is actually
supported by HW.
Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
clock driver. Interestengly, user manual specifies maximum frequency to
be 600 MHz. Historically, this data was wrong in some user manuals for
ot
From: Jagan Teki
Display Engine(DE2) in Allwinner A64 has two mixers and tcons.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
The routing for mixer1 is through tcon1 and connected to HDMI.
Signed-off-by: Jagan Teki
Signed-off-by: Icenowy Zheng
---
Cha
From: Jernej Skrabec
Some boards have HDMI VCC pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
HDMI driver.
Signed-off-by: Jernej Skrabec
[Icenowy: change supply name to "hvcc"]
Signed-off-by: Ic
On Tue 28 Aug 15:39 PDT 2018, Abhinav Kumar wrote:
> From: "abhin...@codeaurora.org"
>
> Add support for Truly NT35597 panel driver used
> in MSM reference platforms.
>
> This panel driver supports both single DSI and dual DSI
> modes.
>
> However, this patch series adds support only for
> dua
From: Jagan Teki
Allwinner A64 has a DE2 display pipeline. The TCONs are similar to the
ones in A83T, but the mixers are new (similar to the later R40 SoC).
This patch adds dt-binding documentation for A64 DE2 display pipeline.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
[Icenowy: Refa
From: Jagan Teki
Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first
TCON is connected to LCD and the second is to HDMI.
The HDMI controller/PHY pair is similar to the one on H3/H5.
Add all required device tree nodes of the display pipeline, including
the TCON0 LCD one and the
crtc_state is accessed by both vblank_handle() and the ordered
work_struct handle vkms_crc_work_handle() to retrieve and or update
the frame number for computed CRC.
Since work_struct can fail, add frame_end to account for missing frame
numbers.
Use (frame_[start/end]) for synchronization between
From: Jagan Teki
Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent.
Include the macro on dt-bindings so-that the same can be used
while defining CCU clock phandles.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- Dropped PLL_VIDEO1
The A64 HDMI PHY is proven to have no PLL-VIDEO mux, thus it's not
compatible with the R40 one.
Drop the A64 fallback compatible string in R40 device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arc
Replace "fall though" with a proper "fall through" annotation.
This fix is part of the ongoing efforts to enabling
-Wimplicit-fallthrough
Addresses-Coverity-ID: 402013 ("Missing break in switch")
Signed-off-by: Gustavo A. R. Silva
---
drivers/video/fbdev/stifb.c | 2 +-
1 file changed, 1 insert
From: Jagan Teki
Mixers in Allwinner have similar capabilities as others SoCs with DE2.
Add support for them.
Signed-off-by: Jagan Teki
[Icenowy: Add mixer1]
Signed-off-by: Icenowy Zheng
Reviewed-by: Jernej Skrabec
---
Changes for v4:
- none
Changes for v3.1:
- Add mixer0
Changes for v3:
- n
Am 04.09.2018 um 03:00 schrieb Bas Nieuwenhuizen:
This is an initial proposal for format modifiers for AMD hardware.
It uses 48 bits including a chip generation, leaving 8 bits for
a format version number.
I'm absolutely not an expert on this, but as far as I know the major
problem with this
https://bugs.freedesktop.org/show_bug.cgi?id=107819
Michel Dänzer changed:
What|Removed |Added
Resolution|--- |DUPLICATE
Status|NEW
On 2018年09月04日 15:00, Christian König wrote:
Am 04.09.2018 um 06:04 schrieb zhoucm1:
On 2018年09月03日 19:19, Christian König wrote:
Am 03.09.2018 um 12:07 schrieb Chunming Zhou:
在 2018/9/3 16:50, Christian König 写道:
Am 03.09.2018 um 06:13 schrieb Chunming Zhou:
在 2018/8/30 19:32, Chris
On 2018-09-03 7:07 p.m., Ilia Mirkin wrote:
> On Mon, Sep 3, 2018 at 12:45 PM, Daniel Vetter wrote:
>> On Mon, Sep 03, 2018 at 12:57:54PM +0200, Gerd Hoffmann wrote:
>>> Userspace on big endian machhines typically expects the ADDFB ioctl
>>> returns a big endian framebuffer. drm_mode_addfb() will
Am 04.09.2018 um 09:53 schrieb zhoucm1:
[SNIP]
How about this idea:
1. Each signaling point is a fence implementation with an rb node.
2. Each node keeps a reference to the last previously inserted node.
3. Each node is referenced by the sync object itself.
4. Before each signal/wait operation
On 2018年09月04日 16:05, Christian König wrote:
Am 04.09.2018 um 09:53 schrieb zhoucm1:
[SNIP]
How about this idea:
1. Each signaling point is a fence implementation with an rb node.
2. Each node keeps a reference to the last previously inserted node.
3. Each node is referenced by the sync obje
On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec wrote:
>
> From: Icenowy Zheng
>
> The Allwinner H6 SoC's DE3 needs the SRAM C section being claimed in the
> system controller to work, like A64 DE2.
>
> As H6 and A64 system controller are quite similar, code is reused now,
> and the A64 fallback co
On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec wrote:
>
> From: Icenowy Zheng
>
> As we have already binding for the H6 system controller, add its node
> to the device tree.
>
> Signed-off-by: Icenowy Zheng
> [fixed compatible string]
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
_
Am 04.09.2018 um 10:27 schrieb zhoucm1:
On 2018年09月04日 16:05, Christian König wrote:
Am 04.09.2018 um 09:53 schrieb zhoucm1:
[SNIP]
How about this idea:
1. Each signaling point is a fence implementation with an rb node.
2. Each node keeps a reference to the last previously inserted node.
3.
Hi,
On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec wrote:
>
> This commit adds necessary description and dt includes for H6 DE3 clock.
> It is very similar to others, but memory region has some additional
> registers not found in DE2.
>
> Signed-off-by: Jernej Skrabec
> ---
> Documentation/devic
On 2018年09月04日 16:42, Christian König wrote:
Am 04.09.2018 um 10:27 schrieb zhoucm1:
On 2018年09月04日 16:05, Christian König wrote:
Am 04.09.2018 um 09:53 schrieb zhoucm1:
[SNIP]
How about this idea:
1. Each signaling point is a fence implementation with an rb node.
2. Each node keeps a re
On Tuesday, 2018-09-04 16:24:44 +1000, Dave Airlie wrote:
> On Mon, 3 Sep 2018 at 18:47, Daniel Vetter wrote:
> >
> > I picked up a bunch of the pieces from wayland's version:
> >
> > https://gitlab.freedesktop.org/wayland/wayland/blob/master/CONTRIBUTING.md
> >
> > The weston one is fairly simila
On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec wrote:
>
> Support for mixer0, mixer1, writeback and rotation units is added.
>
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Icenowy Zheng
> ---
> drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 65
> drivers/clk/sunxi-ng/ccu
On Tue, Sep 4, 2018 at 4:59 PM Chen-Yu Tsai wrote:
>
> Hi,
>
> On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec wrote:
> >
> > This commit adds necessary description and dt includes for H6 DE3 clock.
> > It is very similar to others, but memory region has some additional
> > registers not found in D
https://bugs.freedesktop.org/show_bug.cgi?id=107213
--- Comment #8 from Pau Ruiz Safont ---
Same issue here, with the same error on dmesg:
GPU: R9 380 connected over Displayport
Monitor: DELL U2515H
CPU: AMD Ryzen 7 1700
Motherboard: ASRock AB350 Gaming-ITX/ac
OpenGL Renderer: AMD Radeon R9 380
On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec wrote:
>
> Allwinner H6 SoC has multiplier N range between 1 and 254. Since parent
> rate is 24MHz, intermediate result when calculating final rate easily
> overflows 32 bit variable.
>
> Because of that, introduce function for calculating clock rate w
https://bugs.freedesktop.org/show_bug.cgi?id=107213
--- Comment #9 from Pau Ruiz Safont ---
Created attachment 141438
--> https://bugs.freedesktop.org/attachment.cgi?id=141438&action=edit
dmesg crash output
--
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Am 04.09.2018 um 11:00 schrieb zhoucm1:
On 2018年09月04日 16:42, Christian König wrote:
Am 04.09.2018 um 10:27 schrieb zhoucm1:
On 2018年09月04日 16:05, Christian König wrote:
Am 04.09.2018 um 09:53 schrieb zhoucm1:
[SNIP]
How about this idea:
1. Each signaling point is a fence implementation
https://bugzilla.kernel.org/show_bug.cgi?id=199139
--- Comment #8 from Eduard (wirch.edu...@gmail.com) ---
Is there anything I could do to work around the problem?
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dr
On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
wrote:
> This is an initial proposal for format modifiers for AMD hardware.
>
> It uses 48 bits including a chip generation, leaving 8 bits for
> a format version number.
>
> On gfx6-gfx8 we have all the fields influencing sample locations
> in mem
Hi,
On Tue, 4 Sep 2018 at 11:05, Daniel Vetter wrote:
> On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
> wrote:
> > +/* The chip this is compatible with.
> > + *
> > + * If compression is disabled, use
> > + * - AMDGPU_CHIP_TAHITI for GFX6-GFX8
> > + * - AMDGPU_CHIP_VEGA10 for GFX9+
> >
https://bugs.freedesktop.org/show_bug.cgi?id=107781
--- Comment #7 from Michel Dänzer ---
(In reply to Alex Findler from comment #6)
> I'll use these instructions. Which remote and baseline should I choose?
The linux-4.17.y or linux-4.18.y branch from linux-stable.git .
--
You are receiving th
Am 04.09.2018 um 12:15 schrieb Daniel Stone:
Hi,
On Tue, 4 Sep 2018 at 11:05, Daniel Vetter wrote:
On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
wrote:
+/* The chip this is compatible with.
+ *
+ * If compression is disabled, use
+ * - AMDGPU_CHIP_TAHITI for GFX6-GFX8
+ * - AMDGPU_C
On Tue, Sep 04, 2018 at 12:15:23AM +0200, Henrik Austad wrote:
> This is a respin with a wider audience (all that get_maintainer returned)
> and I know this spams a *lot* of people. Not sure what would be the correct
> way, so my apologies for ruining your inbox.
Acked-by: Mark Brown
signature.
Op 30-08-18 om 14:41 schreef Juha-Pekka Heikkila:
> Preparations for enabling P010, P012 and P016 formats. These
> formats will extend NV12 for larger bit depths.
>
> (Sharma, Swati2): removed unnecessary checks, changed debug error message
> to be more generic.
>
> Signed-off-by: Juha-Pekka Heikki
Hi!
> The 00-INDEX files are supposed to give a summary of all files present
> in a directory, but these files are horribly out of date and their
> usefulness is brought into question. Often a simple "ls" would reveal
> the same information as the filenames are generally quite descriptive as
> a s
May be related to (if your kernel have the same faulty commit):
https://bugs.freedesktop.org/show_bug.cgi?id=107784
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
https://bugs.freedesktop.org/show_bug.cgi?id=107213
--- Comment #10 from Sylvain BERTRAND ---
May be related to (if your kernel have the same faulty commit):
https://bugs.freedesktop.org/show_bug.cgi?id=107784
--
You are receiving this mail because:
You are the assignee for the bug.
The ioctl arguments are under control of the user and as such we should
resist any temptation to flood the kernel logs with their errors.
Relegate the DRM_ERROR to a DRM_DEBUG so the user has to opt into
hearing of their own mistakes. (One day we will have a small ringbuffer
attached to the task, s
The E3 (r8a77990) supports two LVDS channels. Extend the binding to
support them.
Signed-off-by: Laurent Pinchart
---
Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,lvd
On the D3 and E3 SoCs, the LVDS encoder can derive its internal pixel
clock from an externally supplied clock, either through the EXTAL pin or
through one of the DU_DOTCLKINx pins. Add corresponding clocks to the DT
bindings.
To retain backward compatibility with DT that don't specify the
clock-na
On selected SoCs, the DU can use the clock output by the LVDS encoder
PLL as its input dot clock. This feature is optional, but on the D3 and
E3 SoC it is often the only way to obtain a precise dot clock frequency,
as the other available clocks (CPG-generated clock and external clock)
usually have
The R8A77990 (E3) platform has one RGB output and two LVDS outputs
connected to the DU. Add the DT nodes for the DU, LVDS encoders and
supporting VSP and FCP.
Signed-off-by: Laurent Pinchart
---
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 167 ++
1 file changed, 167 i
The THC63LVD1024 is restricted to a pixel clock frequency in the range
of 8 to 135 MHz. Implement the bridge .mode_valid() operation
accordingly.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/thc63lvd1024.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/driv
All Gen3 SoCs supported so far have a fixed association between DPAD0
and DU channels, which led to hardcoding that association when writing
the corresponding hardware register. The D3 and E3 will break that
mechanism as DPAD0 can be dynamically connected to either DU0 or DU1.
Make DPAD0 routing d
From: Kieran Bingham
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
Signed-off-by: Kieran Bingham
[uli: moved lvds* into the soc node, added PM domains, resets]
Signed-off-by: Ulrich Hecht
Reviewed-by: Laurent Pinchart
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 +++
The LVDS encoders in the D3 and E3 SoCs differ significantly from those
in the other R-Car Gen3 family members:
- The LVDS PLL architecture is more complex and requires computing PLL
parameters manually.
- The PLL uses external clocks as inputs, which need to be retrieved
from DT.
- In additio
Document the E3 (r8a77990) SoC in the R-Car DU bindings.
Signed-off-by: Laurent Pinchart
---
Documentation/devicetree/bindings/display/renesas,du.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt
b/Documentation/devicetree/binding
The rcar_du_crtc_get() function is always immediately followed by a call
to rcar_du_crtc_setup(). Call the later from the former to simplify the
code, and add a comment to explain how the get and put calls are
balanced.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c |
From: Ulrich Hecht
Adds LVDS decoder, HDMI encoder and connector for the Draak board.
The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
EXTAL externals clocks. Two of them are provided to the SoC on the Draak
board, hook them up in DT.
Signed-off-by: Ulrich Hecht
Signed-o
From: Takeshi Kihara
Add device nodes for I2C ch{0,1,2,3,4,5,6,7} to R-Car E3 R8A77990 device
tree.
Signed-off-by: Takeshi Kihara
Signed-off-by: Jacopo Mondi
---
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 123 ++
1 file changed, 123 insertions(+)
diff --git a/arc
Hello everybody,
This patch series adds display support for the D3 and E3 SoCs, and in
particular the Draak and Ebisu boards.
The code is based on Ulrich's "[PROTO][PATCH 00/10] R-Car D3 LVDS/HDMI support
(with PLL)" series previously posted to the dri-devel and linux-renesas-soc
mailing lists. I
Add the LVDS decoder, HDMI encoder, VGA encoder and HDMI and VGA
connectors, and wire up the display-related nodes with clocks, pinmux
and regulators.
The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
EXTAL externals clocks. Two of them are provided to the SoC on the Ebisu
bo
DSYSR is a DU channel register that also contains group fields. It is
thus written to by both the group and CRTC code, using read-update-write
sequences. As the register isn't initialized explicitly at startup time,
this can lead to invalid or otherwise unexpected values being written to
some of th
The official way to stop the display is to clear the display enable
(DEN) bit in the DSYSR register, but that operates at a group level and
affects the two channels in the group. To disable channels selectively,
the driver uses TV sync mode that stops display operation on the channel
and turns outp
From: Ulrich Hecht
Add support for the R-Car D3 (R8A77995) and E3 (R8A77990) SoCs to the
R-Car DU driver. The two SoCs instantiate compatible DUs, so a single
information structure is enough.
Signed-off-by: Ulrich Hecht
[Add support for R8A77990]
Signed-off-by: Laurent Pinchart
---
drivers/gp
On Mon, Sep 03, 2018 at 06:38:44PM +0100, Emil Velikov wrote:
> On 3 September 2018 at 17:54, Daniel Vetter wrote:
>
> > -Hide legacy cruft better
> > -
> > -
> > -Way back DRM supported only drivers which shadow-attached to PCI devices
> > with
> > -userspace or fbdev dr
On Tue, Sep 4, 2018 at 12:04 PM Daniel Vetter wrote:
>
> On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
> wrote:
> > This is an initial proposal for format modifiers for AMD hardware.
> >
> > It uses 48 bits including a chip generation, leaving 8 bits for
> > a format version number.
> >
> > O
Hi,
On Tue, 4 Sep 2018 at 11:44, Christian König
wrote:
> Am 04.09.2018 um 12:15 schrieb Daniel Stone:
> > Right. The conclusion, after people went through and started sorting
> > out the kinds of formats for which they would _actually_ export real
> > colour buffers for, that most vendors defini
On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
> Am 04.09.2018 um 12:15 schrieb Daniel Stone:
> > Hi,
> >
> > On Tue, 4 Sep 2018 at 11:05, Daniel Vetter wrote:
> > > On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
> > > wrote:
> > > > +/* The chip this is compatible with.
>
https://bugs.freedesktop.org/show_bug.cgi?id=107213
--- Comment #11 from Nicholas Kazlauskas ---
I'm inclined to believe that is a userspace issue.
I can observe the crash happening on the newest stable Ubuntu/Debian releases.
However, the crash does *not* occur for distributions that have newer
Den 04.09.2018 08.18, skrev Daniel Vetter:
On Tue, Sep 4, 2018 at 1:41 AM, Dave Airlie wrote:
I've seen that you dropped this patch:
https://patchwork.kernel.org/patch/10445393/
Is that patch correct or incorrect? In case it is incorrect, do you have
an idea how should fbdefio be used properl
Hey,
I like the new series. Looks good to me.
Reviewed-by: Maarten Lankhorst
Unfortunately, we probably shouldn't merge this until we've fixed IGT to
support the new floating point formats. :(
This requires a new pixman release and a new cairo release, but without
it we can't actually test.
O
On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
>
> On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
> > Am 04.09.2018 um 12:15 schrieb Daniel Stone:
> > > Hi,
> > >
> > > On Tue, 4 Sep 2018 at 11:05, Daniel Vetter wrote:
> > > > On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuiz
+everyone again
On Tue, Sep 4, 2018 at 2:39 PM Bas Nieuwenhuizen
wrote:
>
> On Tue, Sep 4, 2018 at 2:22 PM Daniel Stone wrote:
> >
> > Hi,
> >
> > On Tue, 4 Sep 2018 at 11:44, Christian König
> > wrote:
> > > Am 04.09.2018 um 12:15 schrieb Daniel Stone:
> > > > Right. The conclusion, after peopl
https://bugs.freedesktop.org/show_bug.cgi?id=107793
--- Comment #3 from Nicholas Kazlauskas ---
If you can provide a dmesg log for your black screen boot that would help.
--
You are receiving this mail because:
You are the assignee for the bug.___
dri
On Tue, Sep 04, 2018 at 10:02:40AM +0100, Eric Engestrom wrote:
> On Tuesday, 2018-09-04 16:24:44 +1000, Dave Airlie wrote:
> > On Mon, 3 Sep 2018 at 18:47, Daniel Vetter wrote:
> > >
> > > I picked up a bunch of the pieces from wayland's version:
> > >
> > > https://gitlab.freedesktop.org/wayland
Op 30-08-18 om 16:24 schreef Stanislav Lisovskiy:
> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> specification.
>
> v2: Edited commit message, removed redundant whitespaces.
>
> v3: Fixed fallthrough logic for the format switch cases.
>
> v4: Yet again fixed fallthrough logic
Looks much neater on the gitlab UI, e.g. on my personal libdrm fork:
https://gitlab.freedesktop.org/danvet/drm
Signed-off-by: Daniel Vetter
---
CONTRIBUTING => CONTRIBUTING.rst | 0
README => README.rst | 0
2 files changed, 0 insertions(+), 0 deletions(-)
rename CONTRIBUTING => CO
Am 04.09.2018 um 14:22 schrieb Daniel Stone:
Hi,
On Tue, 4 Sep 2018 at 11:44, Christian König
wrote:
Am 04.09.2018 um 12:15 schrieb Daniel Stone:
Right. The conclusion, after people went through and started sorting
out the kinds of formats for which they would _actually_ export real
colour bu
Am 04.09.2018 um 14:26 schrieb Daniel Vetter:
On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
Am 04.09.2018 um 12:15 schrieb Daniel Stone:
Hi,
On Tue, 4 Sep 2018 at 11:05, Daniel Vetter wrote:
On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
wrote:
+/* The chip this is c
On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
> On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
> >
> > On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
> > > Am 04.09.2018 um 12:15 schrieb Daniel Stone:
> > > > Hi,
> > > >
> > > > On Tue, 4 Sep 2018 at 11:
On Tue, Sep 4, 2018 at 4:00 AM, Michel Dänzer wrote:
> On 2018-09-03 7:07 p.m., Ilia Mirkin wrote:
>> On Mon, Sep 3, 2018 at 12:45 PM, Daniel Vetter wrote:
>>> On Mon, Sep 03, 2018 at 12:57:54PM +0200, Gerd Hoffmann wrote:
Userspace on big endian machhines typically expects the ADDFB ioctl
>
On Tue, Sep 04, 2018 at 09:45:05AM +0530, Souptick Joarder wrote:
> We have introduce new return type vm_fault_t for
> fault handler. Update the document for the same.
>
> Signed-off-by: Souptick Joarder
> ---
> v2: Revert spaces added in v1
Thanks, applied to drm-misc-next.
-Daniel
>
> Docum
On Tue, Sep 04, 2018 at 12:57:19PM +0100, Chris Wilson wrote:
> The ioctl arguments are under control of the user and as such we should
> resist any temptation to flood the kernel logs with their errors.
> Relegate the DRM_ERROR to a DRM_DEBUG so the user has to opt into
> hearing of their own mist
Am 04.09.2018 um 15:03 schrieb Daniel Vetter:
On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
Am 04.09.2018 um 12:15 schrieb Daniel Stone:
Hi,
On Tue, 4 Se
tree: git://people.freedesktop.org/~agd5f/linux.git drm-next-4.20-wip
head: 6abc0c8f8cf3e0c47707b01f027f9f9b9aa75646
commit: dd73043534515c1b8bf31f78f0e9945f5d95e0e6 [165/258] drm/amd/display:
implement DPMS DTN test v2
config: i386-randconfig-j3-201835 (attached as .config)
compiler: gcc-4.9
On Tue, Sep 4, 2018 at 3:12 PM, Christian König
wrote:
> Am 04.09.2018 um 15:03 schrieb Daniel Vetter:
>>
>> On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
>>>
>>> On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian
Am 04.09.2018 um 15:17 schrieb Daniel Vetter:
On Tue, Sep 4, 2018 at 3:12 PM, Christian König
wrote:
Am 04.09.2018 um 15:03 schrieb Daniel Vetter:
On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
On Tue, Sep 04, 2018 at 1
On Tuesday, 2018-09-04 14:49:07 +0200, Daniel Vetter wrote:
> Looks much neater on the gitlab UI, e.g. on my personal libdrm fork:
>
> https://gitlab.freedesktop.org/danvet/drm
>
> Signed-off-by: Daniel Vetter
Acked-by: Eric Engestrom
> ---
> CONTRIBUTING => CONTRIBUTING.rst | 0
> README =>
On Tue, Sep 4, 2018 at 3:04 PM Daniel Vetter wrote:
>
> On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
> > On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
> > >
> > > On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
> > > > Am 04.09.2018 um 12:15 schrieb Da
On Thu, Aug 30, 2018 at 01:09:37PM +0200, Heiko Stuebner wrote:
> The rk3188 has 2 vops not using iommus which only output directly
> to a rgb interface per vop. So all other output modes like hdmi
> are provided by external brige chips.
>
> Signed-off-by: Heiko Stuebner
> ---
> This depends on S
On 09/03/2018 06:54 PM, Daniel Vetter wrote:
The idea behind allowing drivers to override legacy ioctls (instead of
using the generic implementations unconditionally) is to handle bugs
in old driver-specific userspace. Like e.g. vmw_kms_set_config does,
to work around some vmwgfx userspace not cl
On Tue, Sep 04, 2018 at 02:47:51PM +0200, Maarten Lankhorst wrote:
> Op 30-08-18 om 16:24 schreef Stanislav Lisovskiy:
> > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> > specification.
> >
> > v2: Edited commit message, removed redundant whitespaces.
> >
> > v3: Fixed fallthr
Op 04-09-18 om 15:50 schreef Ville Syrjälä:
> On Tue, Sep 04, 2018 at 02:47:51PM +0200, Maarten Lankhorst wrote:
>> Op 30-08-18 om 16:24 schreef Stanislav Lisovskiy:
>>> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
>>> specification.
>>>
>>> v2: Edited commit message, removed r
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