On 05/17/2018 11:40 PM, Daniel Vetter wrote:
On Thu, May 17, 2018 at 11:18 PM, Thomas Hellstrom wrote:
On 05/17/2018 09:20 PM, Daniel Vetter wrote:
On Thu, May 17, 2018 at 8:23 PM, Thomas Hellstrom
wrote:
Hi!
I'm currently working on a remoting KMS backend, and now I thought it
would
be a g
On Mon, May 14, 2018 at 10:36:08PM +0200, Paul Kocialkowski wrote:
> > > + backlight: backlight {
> > > + compatible = "pwm-backlight";
> > > + pwms = <&pwm 0 5 PWM_POLARITY_INVERTED>;
> > > + brightness-levels = < 0 1 1 1 1 2 2 2
> > > +
On 2018-05-08 15:55, kgu...@codeaurora.org wrote:
On 2018-05-07 21:50, Bjorn Andersson wrote:
On Thu 03 May 02:57 PDT 2018, Kiran Gunda wrote:
WLED4 peripheral is present on some PMICs like pmi8998
and pm660l. It has a different register map and also
configurations are different. Add support f
On Wed, May 16, 2018 at 11:59:32AM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 5/16/2018 10:54 AM, Simon Horman wrote:
>
> > > Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
> > >
> > > Signed-off-by: Ulrich Hecht
> > > ---
> > > drivers/gpu/drm/rcar-du/rcar_lvds.c
A host bridge is allowed to remap BAR addresses using _TRA attribute in
_CRS windows.
pci_bus :00: root bus resource [mem 0x8010010-0x8011fff window]
(bus address [0x0010-0x1fff])
pci :02:00.0: reg 0x10: [mem 0x8011e00-0x8011eff]
When a VGA device is behind such a
From: Lima Project Developers
Signed-off-by: Qiang Yu
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/lima/lima_regs.h | 304 +++
1 file changed, 304 insertions(+)
create mode 100644 drivers/gpu/drm/lima/lima_regs.h
diff --git a/drivers/gpu/drm/lima/lima_regs.h
Hi,
As I already commented[1], I think that it is not proper in order to pass
the devfreq instance to power_domain driver by separate defined function
(rockchip_pm_register_dmcfreq_notifier()).
[1] https://patchwork.kernel.org/patch/10349571/
Maybe, you could check the 'OF graph[1]' or 'device co
On 23.04.2018 09:57, Thierry Reding wrote:
> From: Thierry Reding
>
> The IOVA API uses a memory cache to allocate IOVA nodes from. To make
> sure that this cache is available, obtain a reference to it and release
> the reference when the cache is no longer needed.
>
> On 64-bit ARM this is hidd
+ Kishon
On Thursday, May 17, 2018 09:51 PM, Sean Paul wrote:
On Thu, May 17, 2018 at 05:18:00PM +0800, Lin Huang wrote:
DP firmware uses fixed phy config values to do training, but some
boards need to adjust these values to fit for their unique hardware
design. So get phy config values from d
From: Lima Project Developers
Signed-off-by: Qiang Yu
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/lima/lima_pmu.c | 85 +
drivers/gpu/drm/lima/lima_pmu.h | 30
2 files changed, 115 insertions(+)
create mode 100644 drivers/gpu/drm/lima/lima_pm
On Thu, May 17, 2018 at 02:15:40PM +0100, Daniel Stone wrote:
> Hi Russell,
>
> On 30 March 2018 at 15:11, Daniel Stone wrote:
> > Since drm_framebuffer can now store GEM objects directly, place them
> > there rather than in our own subclass. As this makes the framebuffer
> > create_handle and de
Hi David,
I don't see this in what I presume is your tree yet - do you have some
concern about merging this series?
Thanks.
On Tue, Apr 24, 2018 at 10:54:56AM +0100, Russell King wrote:
> David,
>
> Please incorporate support for TDA998x I2C driver CEC, which can be
> found at:
>
> git://git
On 2018-05-17 18:01, Rob Herring wrote:
On Thu, May 17, 2018 at 4:47 AM, wrote:
On 2018-05-08 15:55, kgu...@codeaurora.org wrote:
On 2018-05-07 21:50, Bjorn Andersson wrote:
On Thu 03 May 02:57 PDT 2018, Kiran Gunda wrote:
WLED4 peripheral is present on some PMICs like pmi8998
and pm660l
Hi All,
Good day!
I’ve been doing some PTN3460 programming under Linux using C/C++ and I have
some questions regarding on setting the brightness level to my display device.
The display device with PTN3460 is connected in DP (display port) to my
computer. Only needs a DisplayPort native AUX comman
We report the crash:
"KASAN: use-after-free Read in vgacon_invert_region"
This crash was found in v4.17-rc3. Specifically, memory access (read
operation) is invalid, and it is detected by KASAN.
C repro code:
https://kiwi.cs.purdue.edu/static/alexkkid-fuzzer/repro-ba6c1.c
kernel config:
https:/
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v3:
- modify property description and add this property to Example
Change in v4:
- None
Change in v5:
- None
.../devicetree/bindings/phy/phy-
From: Lima Project Developers
Signed-off-by: Qiang Yu
Signed-off-by: Simon Shields
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/lima/lima_device.c | 407 +
drivers/gpu/drm/lima/lima_device.h | 136 ++
2 files changed, 543 insertions(+)
create mode 100
On 5/17/2018 6:17 AM, Robin Murphy wrote:
>> + }
>> +
>
> Is this not pretty much just pcibios_bus_to_resource()?
>
Agreed, let me convert the code to use pcibios_bus_to_resource() API.
I wasn't aware of its existence.
> Robin.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an af
On Wed, May 16, 2018 at 08:55:06PM -0300, Rodrigo Siqueira wrote:
> This series of patches add a centralized initialization mechanism, a
> single CRTC with a plane, an encoder, and extra module information.
>
> Changes in v2:
> - Remove unused definitions
> - Improve file names
> - Improve cod
From: Lima Project Developers
PP is a processor used for OpenGL fragment shader
processing.
Signed-off-by: Qiang Yu
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/lima/lima_pp.c | 418 +
drivers/gpu/drm/lima/lima_pp.h | 37 +++
2 files changed, 455 insertio
On 17 May 2018 at 16:55, Peter Jones wrote:
> On Thu, May 17, 2018 at 09:22:23AM -0400, Sinan Kaya wrote:
>> A host bridge is allowed to remap BAR addresses using _TRA attribute in
>> _CRS windows.
>>
>> pci_bus :00: root bus resource [mem 0x8010010-0x8011fff window]
>> (bus address [
From: Chris Zhong
We may support training outside firmware, so we need support
dpcd read/write to get the message or do some setting with
display.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
Reviewed-by: Sean Paul
Reviewed-by: Enric Balletbo
---
Changes in v2:
- update patch followin
From: Lima Project Developers
Signed-off-by: Qiang Yu
Signed-off-by: Heiko Stuebner
Signed-off-by: Erico Nunes
---
drivers/gpu/drm/lima/lima_drv.c | 466
drivers/gpu/drm/lima/lima_drv.h | 77 ++
2 files changed, 543 insertions(+)
create mode 100644 drive
Hi Linus,
On 17/05/18 10:04, Linus Walleij wrote:
> On Wed, May 9, 2018 at 6:44 PM, Sudeep Holla wrote:
>
>> Please copy me and Lorenzo also in future.
>> Applied now(with typo in hierarchy fixed), thanks.
>
> Sure thing, sorry I didn't realize you were working actively with
> the Versatile Exp
Sorry, I'm preparing RFC for lima driver, this mail is send by accident.
Will resend a formal one latter.
Regards,
Qiang
On Fri, May 18, 2018 at 11:16 AM, Qiang Yu wrote:
> From: Lima Project Developers
>
> Signed-off-by: Qiang Yu
> Signed-off-by: Heiko Stuebner
> ---
> drivers/gpu/drm/lima
On 2018-05-16 12:56, Andrzej Hajda wrote:
I suppose you wanted to respond on the list, so I have added back all
recipients.
On 16.05.2018 06:39, spa...@codeaurora.org wrote:
On 2018-05-15 19:23, Andrzej Hajda wrote:
On 15.05.2018 07:52, Sandeep Panda wrote:
Add support for TI's sn65dsi86 dsi2
DP firmware uses fixed phy config values to do training, but some
boards need to adjust these values to fit for their unique hardware
design. So get phy config values from dts and use software link training
instead of relying on firmware, if software training fail, keep firmware
training as a fallb
From: Lima Project Developers
Signed-off-by: Qiang Yu
Signed-off-by: Marek Vasut
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/lima/lima_mmu.c | 154
drivers/gpu/drm/lima/lima_mmu.h | 34 +++
2 files changed, 188 insertions(+)
create mode 100644 driv
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
Changes in
https://bugs.freedesktop.org/show_bug.cgi?id=106561
Bug ID: 106561
Summary: ./libdrm_macros.h:26:5: error: 'HAVE_VISIBILITY' is
not defined, evaluates to 0 [-Werror,-Wundef]
Product: DRI
Version: DRI git
Hardware: x86-64 (A
"id" needs to be signed for the error handling to work.
Fixes: 7a2d5c77c558 ("drm/exynos: fimc: Convert driver to IPP v2 core API")
Signed-off-by: Dan Carpenter
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
index 4dfbfc7f3b84..5ce84025d1cb 1006
On Thu, 2018-05-17 at 16:55 +0200, Thierry Reding wrote:
> On Thu, May 17, 2018 at 09:58:19AM -0400, Sean Paul wrote:
> > On Fri, Mar 30, 2018 at 03:11:22PM +0100, Daniel Stone wrote:
> > > A FB with no object is something we should be shouting very loudly
> > > about, not quietly logging as debug.
The v3d_fence_create() only returns error pointers on error. It never
returns NULL.
Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D
V3.x+")
Signed-off-by: Dan Carpenter
diff --git a/drivers/gpu/drm/v3d/v3d_sched.c b/drivers/gpu/drm/v3d/v3d_sched.c
index b07bece9417d.
From: Brian Starkey
Mali-DP has a memory writeback engine which can be used to write the
composition result to a memory buffer. Expose this functionality as a
DRM writeback connector on supported hardware.
Changes since v1:
Daniel Vetter:
- Don't require a modeset when writeback routing change
Mali DP500 behaves differently from the rest of the Mali DP IP,
in that it does not have a one-shot mode and keeps writing the
content of the current frame to the provided memory area until
stopped. As a way of emulating the one-shot behaviour, we are
going to use the CVAL interrupt that is being r
From: Brian Starkey
Add a layer bit for the SE memory-write, and add it to the pixel format
matrix for DP550/DP650.
Signed-off-by: Brian Starkey
[rebased and fixed conflicts]
Signed-off-by: Mihail Atanassov
Signed-off-by: Liviu Dudau
---
drivers/gpu/drm/arm/malidp_hw.c | 22 +++--
Mali-DP display processors are able to write the composition result to a
memory buffer via the SE.
Add entry points in the HAL for enabling/disabling this feature, and
implement support for it on DP650 and DP550. DP500 acts differently and
so is omitted from this change.
Changes since v3:
- Fix
Annotate the pixel format matrix for DP500 with the memory-write flag
for formats that are supported by the SE memwrite engine.
Signed-off-by: Liviu Dudau
---
drivers/gpu/drm/arm/malidp_hw.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/arm/malidp
Hi,
Updating the Mali DP memory writeback engine support series to match
the latest generic writeback connector support posted here [1]. As the
generic patches look ready to be merged into drm-misc-next, I'm sending
the updated Mali DP driver as well.
Changelog:
- v7: Added support for DP500 wri
On Fri, 2018-03-30 at 22:11 +0800, Daniel Stone wrote:
> Since drm_framebuffer can now store GEM objects directly, place them
> there rather than in our own subclass. As this makes the framebuffer
> create_handle and destroy functions the same as the GEM framebuffer
> helper, we can reuse those.
>
On Fri, 2018-03-30 at 22:11 +0800, Daniel Stone wrote:
> Now that mtk_drm_fb is an empty wrapper around drm_framebuffer, we can
> just delete it.
>
Reviewed-by: CK Hu
> Signed-off-by: Daniel Stone
> Cc: CK Hu
> Cc: Philipp Zabel
> ---
> drivers/gpu/drm/mediatek/mtk_drm_fb.c | 40
>
On 2018-05-17 09:05 PM, Andrey Grodzovsky wrote:
> On 05/17/2018 10:48 AM, Michel Dänzer wrote:
>> On 2018-05-17 01:18 PM, Andrey Grodzovsky wrote:
>>> Hi Michele and others, I am trying to implement the approach bellow to
>>> resolve AMDGPU's hang when commands are stuck in pipe during process
>>>
Am Freitag, 18. Mai 2018, 03:45:46 CEST schrieb Brian Norris:
> On Thu, May 17, 2018 at 6:41 PM, hl wrote:
> > On Thursday, May 17, 2018 09:51 PM, Sean Paul wrote:
> >> On Thu, May 17, 2018 at 05:18:00PM +0800, Lin Huang wrote:
> >>> DP firmware uses fixed phy config values to do training, but som
Hi Liviu,
On Fri, May 18, 2018 at 09:24:21AM +0100, Liviu Dudau wrote:
Mali DP500 behaves differently from the rest of the Mali DP IP,
in that it does not have a one-shot mode and keeps writing the
content of the current frame to the provided memory area until
stopped. As a way of emulating the
From: Michel Dänzer
Signed-off-by: Michel Dänzer
---
xf86drm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/xf86drm.c b/xf86drm.c
index 3a9d0ed2..c09437b0 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -405,7 +405,7 @@ wait_for_udev:
}
#endif
-fd = open(buf,
On Wed, May 16, 2018 at 12:22:04PM +0200, Emil Goode wrote:
> The compiler is complaining with the following errors:
>
> drivers/gpu/host1x/cdma.c:94:48: error:
> passing argument 3 of ‘dma_alloc_wc’ from incompatible pointer type
> [-Werror=incompatible-pointer-types]
>
> drivers/gpu
Anyway, the kernel can't rely on userspace using O_CLOEXEC. If the flush
callback being called from multiple processes is an issue, maybe the
flush callback isn't appropriate after all.
Userspace could also grab a reference just by opening /proc/$pid/fd/*.
The idea is just that when any proce
On Thu, 17 May 2018, John Sledge wrote:
> I’ve been doing some PTN3460 programming under Linux using C/C++ and I
> have some questions regarding on setting the brightness level to my
> display device.
>
> The display device with PTN3460 is connected in DP (display port) to
> my computer. Only need
Quoting Chris Wilson (2018-05-13 10:50:07)
> As we keep an rbtree of available holes sorted by their size, we can
> very easily determine if there is any hole large enough that might
> satisfy the allocation request. This helps when dealing with a highly
> fragmented address space and a request for
On Fri, May 18, 2018 at 03:15:10PM +0530, Jagan Teki wrote:
> Allwinner A64 has display engine pipeline like other Allwinner SOC's
> A83T/H3/H5.
>
> A64 behaviour similar to Allwinner A83T where
> Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
> Mixer1 => TCON1 => HDMI
> as per Display System Block Diagram
On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> From: Jernej Skrabec
>
> Some SoCs with DW HDMI have multiple possible clock parents, like A64
> and R40.
>
> Expand HDMI PHY clock driver to support second clock parent.
>
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Jagan Teki
Quoting Chris Wilson (2018-05-13 10:50:08)
> Searching for an available hole by address is slow, as there no
> guarantee that a hole will be available and so we must walk over all
> nodes in the rbtree before we determine the search was futile. In many
> cases, the caller doesn't strictly care for
Quoting Chris Wilson (2018-05-13 10:50:09)
> To no surprise (since we've flip-flopped over the use of PIN_HIGH a few
> times), doing a search by address over a pathologically fragmented
> address space is exceeding slow. To protect ourselves from nearly
> unbounded latency (think searching a millio
Quoting Chris Wilson (2018-05-13 10:50:10)
> If we can use an unmappable ring, try to pin it out of the mappable
> aperture. This simple layout preference is to try and keep the mappable
> aperture reserved and available to handle GGTT mmapping requests from
> userspace without causing evictions an
Quoting Joonas Lahtinen (2018-05-18 11:05:36)
> Quoting Chris Wilson (2018-05-13 10:50:09)
> > To no surprise (since we've flip-flopped over the use of PIN_HIGH a few
> > times), doing a search by address over a pathologically fragmented
> > address space is exceeding slow. To protect ourselves fro
On Wed, Apr 11, 2018 at 05:27:41PM +0200, Lucas Stach wrote:
> The patch adding support for the AUO P320HVN03 panel was written against a
> preliminary datasheet, which specified JEIDA data ordering. Testing with
> real hardware has shown that the actually used data ordering is SPWG.
>
> Fixes: 70
On Thu, Apr 19, 2018 at 11:20:03PM +0200, Stefan Agner wrote:
> All values in a struct struct timing_entry (every entry in
> struct display_timing) require an integer. Choose the closest
> safe integer of 32.
>
> This avoids a warning seen with clang:
> drivers/gpu/drm/panel/panel-simple.c:1250:
Quoting Chris Wilson (2018-05-18 13:07:16)
> Quoting Joonas Lahtinen (2018-05-18 11:05:36)
> > Quoting Chris Wilson (2018-05-13 10:50:09)
> > > To no surprise (since we've flip-flopped over the use of PIN_HIGH a few
> > > times), doing a search by address over a pathologically fragmented
> > > addr
On 17/05/18 14:22, Sinan Kaya wrote:
A host bridge is allowed to remap BAR addresses using _TRA attribute in
_CRS windows.
pci_bus :00: root bus resource [mem 0x8010010-0x8011fff window]
(bus address [0x0010-0x1fff])
pci :02:00.0: reg 0x10: [mem 0x8011e00-0x8011e
Am 18.05.2018 um 11:17 schrieb Michel Dänzer:
From: Michel Dänzer
Signed-off-by: Michel Dänzer
Reviewed-by: Christian König
---
xf86drm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/xf86drm.c b/xf86drm.c
index 3a9d0ed2..c09437b0 100644
--- a/xf86drm.c
+++
On Fri, May 18, 2018 at 09:56:20AM +0100, Brian Starkey wrote:
> Hi Liviu,
>
> On Fri, May 18, 2018 at 09:24:21AM +0100, Liviu Dudau wrote:
> > Mali DP500 behaves differently from the rest of the Mali DP IP,
> > in that it does not have a one-shot mode and keeps writing the
> > content of the curr
On 26.04.2018 10:07, Jyri Sarha wrote:
> Add device_link from panel device (supplier) to drm device (consumer)
> when drm_panel_attach() is called. This patch should protect the
> master drm driver if an attached panel driver unbinds while it is in
> use. The device_link should make sure the drm de
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
On Thu, May 17, 2018 at 10:10 AM, wrote:
> On 2018-05-17 18:01, Rob Herring wrote:
>>
>> On Thu, May 17, 2018 at 4:47 AM, wrote:
>>>
>>> On 2018-05-08 15:55, kgu...@codeaurora.org wrote:
On 2018-05-07 21:50, Bjorn Andersson wrote:
>
>
> On Thu 03 May 02:57 PDT 2018, K
On 05/17/2018 06:34 PM, Thierry Reding wrote:
From: Thierry Reding
Userspace needs to know the version of the interface implemented by a
client so it can create the proper command streams. Allow individual
drivers to store this version along with the client so that it can be
returned to userspa
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
On Fri, May 18, 2018 at 03:21:11PM +0300, Mikko Perttunen wrote:
> On 05/17/2018 06:34 PM, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Userspace needs to know the version of the interface implemented by a
> > client so it can create the proper command streams. Allow individual
> > driv
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
On 05/18/2018 03:39 PM, Thierry Reding wrote:
On Fri, May 18, 2018 at 03:21:11PM +0300, Mikko Perttunen wrote:
On 05/17/2018 06:34 PM, Thierry Reding wrote:
From: Thierry Reding
Userspace needs to know the version of the interface implemented by a
client so it can create the proper command st
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
On 18/05/18 14:51, Andrzej Hajda wrote:
> On 26.04.2018 10:07, Jyri Sarha wrote:
>> Add device_link from panel device (supplier) to drm device (consumer)
>> when drm_panel_attach() is called. This patch should protect the
>> master drm driver if an attached panel driver unbinds while it is in
>> us
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
Hi All,
The new Google "Fizz" Intel-based ChromeOS device is gaining CEC support
through it's Embedded Controller, to enable the Linux CEC Core to communicate
with it and get the CEC Physical Address from the correct HDMI Connector, the
following must be added/changed:
- Add the CEC sub-device reg
In non device-tree world, we can need to get the notifier by the driver
name directly and eventually defer probe if not yet created.
This patch adds a variant of the get function by using the device name
instead and will not create a notifier if not yet created.
But the i915 driver exposes at lea
The EC can expose a CEC bus, thus add the cros-ec-cec MFD sub-device
when the CEC feature bit is present.
Signed-off-by: Neil Armstrong
---
drivers/mfd/cros_ec_dev.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/mfd/cros_ec_dev.c b/drivers/mfd/cros_ec_dev.c
index
This patchs adds the cec_notifier feature to the intel_hdmi part
of the i915 DRM driver. It uses the HDMI DRM connector name to differentiate
between each HDMI ports.
The changes will allow the i915 HDMI code to notify EDID and HPD changes
to an eventual CEC adapter.
Signed-off-by: Neil Armstrong
The Chrome OS Embedded Controller can expose a CEC bus, this patch add the
driver for such feature of the Embedded Controller.
This driver is part of the cros-ec MFD and will be add as a sub-device when
the feature bit is exposed by the EC.
The controller will only handle a single logical address
The EC can expose a CEC bus, this patch adds the CEC related definitions
needed by the cros-ec-cec driver.
Having a 16 byte mkbp event size makes it possible to send CEC
messages from the EC to the AP directly inside the mkbp event
instead of first doing a notification and then a read.
Signed-off-
On Thu, May 17, 2018 at 6:25 PM, Stefan Schake wrote:
> Hey Rob,
>
> On Fri, May 18, 2018 at 12:08 AM, Rob Herring wrote:
>> In order to assign planes to layers in ValidateDisplay, testing
>> compositing with a DRM atomic modeset test is needed as PresentDisplay
>> is too late. This means most of
On Fri, May 18, 2018 at 03:05:01PM +0200, Neil Armstrong wrote:
> This patchs adds the cec_notifier feature to the intel_hdmi part
> of the i915 DRM driver. It uses the HDMI DRM connector name to differentiate
> between each HDMI ports.
> The changes will allow the i915 HDMI code to notify EDID and
2018-05-18 15:05 GMT+02:00 Neil Armstrong :
> The EC can expose a CEC bus, thus add the cros-ec-cec MFD sub-device
> when the CEC feature bit is present.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/mfd/cros_ec_dev.c | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/
We cannot create a framebuffer with no objects, so there's no point
testing for it.
v2: Remove the error entirely. (Sean, CK, Thierry)
Signed-off-by: Daniel Stone
Cc: Sean Paul
Cc: Thierry Reding
Cc: CK Hu
Cc: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 5 -
1 file chan
Since drm_framebuffer can now store GEM objects directly, place them
there rather than in our own subclass. As this makes the framebuffer
create_handle and destroy functions the same as the GEM framebuffer
helper, we can reuse those.
Signed-off-by: Daniel Stone
Reviewed-by: CK Hu
Reviewed-by: Th
Now that mtk_drm_fb is an empty wrapper around drm_framebuffer, we can
just delete it.
Signed-off-by: Daniel Stone
Reviewed-by: CK Hu
Reviewed-by: Thierry Reding
Reviewed-by: Sean Paul
Cc: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_drm_fb.c | 40 ++-
1 file change
Hi Neil,
2018-05-18 15:04 GMT+02:00 Neil Armstrong :
> Hi All,
>
> The new Google "Fizz" Intel-based ChromeOS device is gaining CEC support
> through it's Embedded Controller, to enable the Linux CEC Core to communicate
> with it and get the CEC Physical Address from the correct HDMI Connector, th
Hi Dave,
nothing really big in etnaviv land this time. GC7000 support is still
slowly cooking but not ready at this time.
So what we have for this cycle is a bit of spring cleaning with removal
of unused register logging code and getting rid of the license text in
favor of SPDX, a few smaller MMU
On Fri, May 18, 2018 at 03:15:26PM +0530, Jagan Teki wrote:
> Allwinner A64 has two clock parents PLL_VIDEO0 and PLL_VIDEO1.
>
> Include these macros on dt-bindings so-that the same can be
> used while defining CCU clock phadles.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - new patc
On Fri, May 18, 2018 at 02:47:03PM +0100, Daniel Stone wrote:
> We cannot create a framebuffer with no objects, so there's no point
> testing for it.
>
> v2: Remove the error entirely. (Sean, CK, Thierry)
>
> Signed-off-by: Daniel Stone
> Cc: Sean Paul
> Cc: Thierry Reding
> Cc: CK Hu
> Cc: P
On 2018-05-18 11:42 AM, Christian König wrote:
>
>> Anyway, the kernel can't rely on userspace using O_CLOEXEC. If the flush
>> callback being called from multiple processes is an issue, maybe the
>> flush callback isn't appropriate after all.
>
> Userspace could also grab a reference just by ope
https://bugs.freedesktop.org/show_bug.cgi?id=106175
--- Comment #12 from tempel.jul...@gmail.com ---
Latest drm-next-4.18-wip aa1bce17d841a362d40da940487e13affe4c7b3b still shows
the same behavior.
I'd be happy if more users would comment on this, since it makes use of
amdgpu.dc totally impossible
Am 18.05.2018 um 16:44 schrieb Michel Dänzer:
On 2018-05-18 11:42 AM, Christian König wrote:
Anyway, the kernel can't rely on userspace using O_CLOEXEC. If the flush
callback being called from multiple processes is an issue, maybe the
flush callback isn't appropriate after all.
Userspace could
Hi Neil,
2018-05-18 15:05 GMT+02:00 Neil Armstrong :
> The Chrome OS Embedded Controller can expose a CEC bus, this patch add the
A minor nit, there is a "consensus" on tell cros-ec as "ChromeOS
Embedded Controller" or "ChromeOS EC". Yes, I know that you can see in
the kernel many other ways to r
On 05/18/2018 10:50 AM, Christian König wrote:
Am 18.05.2018 um 16:44 schrieb Michel Dänzer:
On 2018-05-18 11:42 AM, Christian König wrote:
Anyway, the kernel can't rely on userspace using O_CLOEXEC. If the
flush
callback being called from multiple processes is an issue, maybe the
flush call
Due to the fact that writeback connectors behave in a special way
in DRM (they always report being disconnected) we might confuse some
userspace. Add a client capability for writeback connectors that will
filter them out for clients that don't understand the capability.
Re-requested-by: Sean Paul
Hi,
This is v8 of the writeback connector series. v7 got flagged by the
kbuild bot as not being correctly bisectable, so I went and fix that.
For anyone that wants a refresh on what changed in v6, the series
can be found here [2]. The only change in v7 is that the userspace
capabilities patch doe
From: Brian Starkey
Writeback connectors represent writeback engines which can write the
CRTC output to a memory framebuffer. Add a writeback connector type and
related support functions.
Drivers should initialize a writeback connector with
drm_writeback_connector_init() which takes care of sett
From: Brian Starkey
Add the WRITEBACK_OUT_FENCE_PTR property to writeback connectors, to
enable userspace to get a fence which will signal once the writeback is
complete. It is not allowed to request an out-fence without a
framebuffer attached to the connector.
A timeline is added to drm_writeba
On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > lookup pll-2 either.
>
> It is highly unlikely this will be higher than 2, at least for this HDMI PHY,
> since it has only 1 bit reserved for parent select
On Fri, May 18, 2018 at 10:52:17AM +0200, Heiko Stuebner wrote:
> Am Freitag, 18. Mai 2018, 03:45:46 CEST schrieb Brian Norris:
> > On Thu, May 17, 2018 at 6:41 PM, hl wrote:
> > > On Thursday, May 17, 2018 09:51 PM, Sean Paul wrote:
> > >> On Thu, May 17, 2018 at 05:18:00PM +0800, Lin Huang wrote
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