https://bugs.freedesktop.org/show_bug.cgi?id=104274
--- Comment #9 from Luke McKee ---
Using Polairs 11 I get the same error message btw when loading the latest
(today) amd-drm-staging-next. I'll include debugging symbols and try again.
Feb 26 14:56:18 hojuruku kernel: Linux agpgart interface v0
**
*Hi, all!*
*
Last *Friday* some concerns on #dri-devel were raised wrt "yet
another driver" for Xen and why not virtio-gpu. Let me highlight
on why we need a new paravirtualized driver for Xen and why we
can't just use virtio. Hope this helps the communities (both Xen
and DRI) to have be
于 2018年2月25日 GMT+08:00 下午4:11:34, Julian Calaby 写到:
>Hi Jernej,
>
>On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec
> wrote:
>> Enable HDMI output on all boards which have HDMI connector.
>>
>> Signed-off-by: Jernej Skrabec
>> ---
>> arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts| 25
>
CLK_PLL_VIDEO needs to be referenced in HDMI DT entry as a possible
PHY clock parent.
Export it so it can be used later in DT.
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 4 +++-
include/dt-bindings/clock/sun8i-h3-ccu.h | 2 ++
2 files changed, 5 insertions(+),
While A83T HDMI PHY seems to be just customized Synopsys HDMI PHY, H3
HDMI PHY is completely custom PHY.
However, they still have many things in common like clock and reset
setup, setting sync polarity and more.
Add support for H3 HDMI PHY variant.
While documentation exists for this PHY variant
Hi Jernej,
On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec wrote:
> Enable HDMI output on all boards which have HDMI connector.
>
> Signed-off-by: Jernej Skrabec
> ---
> arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts| 25
> ++
> arch/arm/boot/dts/sun8i-h3-beelink-x2.dt
Some units have to be able to set it's own clock precisely to work
correctly. Allow them to do so by adding CLK_SET_RATE_PARENT flag.
Add this flag to DE, TCON and HDMI clocks.
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 9 ++---
1 file changed, 6 insertions(+),
On 02/23/18 11:56, Laurent Pinchart wrote:
> Hi Frank,
>
> On Friday, 23 February 2018 21:43:17 EET Frank Rowand wrote:
>> On 02/23/18 01:00, Laurent Pinchart wrote:
>>> On Friday, 23 February 2018 04:38:06 EET Frank Rowand wrote:
On 02/22/18 14:10, Frank Rowand wrote:
> Hi Laurent, Rob,
There are multiple variants of DW HDMI PHYs in Allwinner SoCs. While
some things like clock and reset setup are the same, PHY configuration
differs a lot.
Split out code which is PHY specific to separate functions and create
a structure which holds pointers to those functions.
Signed-off-by: Jern
Enable HDMI output on all boards with HDMI connector.
Signed-off-by: Jernej Skrabec
---
.../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 25 ++
.../dts/allwinner/sun50i-h5-orangepi-prime.dts | 25 ++
.../allwinner/sun50i-h5-orangepi-zero-plus2.dts
Hi Icenowy,
On Sun, Feb 25, 2018 at 7:43 PM, Icenowy Zheng wrote:
>
>
> 于 2018年2月25日 GMT+08:00 下午4:11:34, Julian Calaby 写到:
>>Hi Jernej,
>>
>>On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec
>> wrote:
>>> Enable HDMI output on all boards which have HDMI connector.
>>>
>>> Signed-off-by: Jernej Sk
Add missing compatibles for H3 HDMI pipeline. These compatibles can also
be used with H5 SoC.
Signed-off-by: Jernej Skrabec
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/
H3 display engine has two mixers which are connected to HDMI and TV
output.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 3957c2ff6870..a0f43b81c
Enable HDMI output on all boards which have HDMI connector.
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts| 25 ++
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 25 ++
arch/arm/boot/dts/sun8i-h3-libretech-all-h
Plumb through the existing test based on known sample data for the
Separate Rect algorithm via Android's NATIVE_TEST harness.
Change-Id: I82b5ab8ed97e338fd20b7e38b4b35ac8c53f4d2d
Signed-off-by: Rhys Kidd
---
separate_rects.cpp| 99 -
tests/And
Since we aren't in atomic context replace this long udelay with a
usleep_range.
Signed-off-by: Stefan Wahren
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 984501e..1a6db
This commit adds all entries needed for HDMI to function properly.
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 108 +
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5
On 02/22/18 14:10, Frank Rowand wrote:
> Hi Laurent, Rob,
>
> Thanks for the prompt spin to address my concerns. There are some small
> technical issues.
>
> I did not read the v3 patch until today. v3 through v6 are still using the
> old overlay apply method which uses an expanded device tree
Reflect the boolean logic of the accompanying code, which is run after
Worker.InitWorker() has completed in test setup.
Change-Id: If5187bdaa944c5d74a70c55b5b5e58e1baa20511
Signed-off-by: Rhys Kidd
---
tests/worker_test.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/test
于 2018年2月25日 GMT+08:00 下午5:06:32, Julian Calaby 写到:
>Hi Icenowy,
>
>On Sun, Feb 25, 2018 at 7:43 PM, Icenowy Zheng wrote:
>>
>>
>> 于 2018年2月25日 GMT+08:00 下午4:11:34, Julian Calaby
> 写到:
>>>Hi Jernej,
>>>
>>>On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec
>>> wrote:
Enable HDMI output on all
Some NM PLLs doesn't work well when their output clock rate is set below
certain rate.
Add support for that constrain.
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu_nm.c | 11 +++
drivers/clk/sunxi-ng/ccu_nm.h | 27 +++
2 files changed, 34 insertions
Current polarity configuration code is cleary wrong since it compares
same flag two times. However, even if flag name is fixed, it won't work
well for resolutions which have one polarity positive and another
negative.
Fix that by properly set each bit according to each polarity. Since
those two bi
Although user manuals for H3 and H5 SoCs state that minimal rate
supported by video PLL is around 30 MHz, it seems that in reality
minimal rate is around 192 MHz.
Experiments showed that any rate below 96 MHz doesn't produce any video
output at all. Even at this frequency, stable output depends on
64-bit ARM SoCs from Allwinner have DE2/TCON/HDMI periphery which
is compatible to 32-bit SoCs, so allow building DRM driver for
arm64 architecture.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
DW HDMI PHY macros are moved to header file and expanded with the
registers present on newer SoCs like H3 and H5.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 130 +
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 16
2 files changed,
I'll rebase it on latest for-next in next version.
Thank you,
Claudiu Beznea
On 24.02.2018 22:49, kbuild test robot wrote:
> Hi Claudiu,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on pwm/for-next]
> [also build test WARNING on v4.16-rc2 next-20180223
This mixer supports 1 VI plane, 3 UI plane and HW scaling on all planes.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 9b0256
This series implements H3/H5 HDMI driver. It was tested on OrangePi 2 (H3),
OrangePi Plus2e (H3) and OrangePi PC2 (H5) with many resolutions and it
works well, except in some not yet determined cases, when there is a crash
at boot if HDMI monitor is connected. If it is connected later, everything
w
From: Hans Verkuil
Document the new core error injection callbacks.
Signed-off-by: Hans Verkuil
---
Documentation/media/kapi/cec-core.rst | 72 ++-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/Documentation/media/kapi/cec-core.rst
b/Documentati
From: Hans Verkuil
Implement all the error injection commands.
The state machine gets new states for the various error situations,
helper functions are added to detect whether an error injection is
active and the actual error injections are implemented.
Signed-off-by: Hans Verkuil
---
drivers
From: Hans Verkuil
This function will be needed for injecting a custom pulse.
Signed-off-by: Hans Verkuil
---
drivers/media/cec/cec-pin-priv.h | 2 ++
drivers/media/cec/cec-pin.c | 21 +
2 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/media/cec
From: Hans Verkuil
This patch series adds support for CEC error injection for drivers
using the CEC Pin Framework (cec-pin.c). There are two CEC drivers
currently using this framework: the sun4i Allwinner A10/A20 driver
and the cec-gpio driver. This patch series was developed with the
cec-gpio dr
From: Hans Verkuil
The CEC Pin framework adds support for Error Injection.
Document all the error injections commands and how to use it.
Signed-off-by: Hans Verkuil
---
.../media/cec-drivers/cec-pin-error-inj.rst| 321 +
Documentation/media/cec-drivers/index.rst
From: Hans Verkuil
Add support to the CEC Pin framework to parse error injection commands
and to show them.
The next patch will do the actual implementation of this.
Signed-off-by: Hans Verkuil
---
drivers/media/cec/Kconfig | 6 +
drivers/media/cec/Makefile| 4 +
d
From: Hans Verkuil
Add two new ops (error_inj_show and error_inj_parse_line) to support
error injection functionality for CEC adapters. If both are present,
then the core will add a new error-inj debugfs file that can be used
to see the current error injection commands and to set error injection
On Thu, Feb 22, 2018 at 05:12:17PM +0100, meg...@megous.com wrote:
> From: Ondrej Jirman
>
> I noticed that with 4.16-rc1 LVDS output on A83T based TBS A711 tablet doesn't
> work (there's output but it's garbled). I compared some older patches for LVDS
> support with the mainlined ones and this c
Hi,
On Fri, Feb 23, 2018 at 02:06:52PM +0100, Arnd Bergmann wrote:
> When the base sun4i DRM driver is built-in but the back-end is
> a loadable module, we run into a link error:
>
> drivers/gpu/drm/sun4i/sun4i_drv.o: In function `sun4i_drv_probe':
> sun4i_drv.c:(.text+0x60c): undefined reference
On Mon, Feb 26, 2018 at 10:21 AM, Maxime Ripard
wrote:
> Hi,
>
> On Fri, Feb 23, 2018 at 02:06:52PM +0100, Arnd Bergmann wrote:
>> When the base sun4i DRM driver is built-in but the back-end is
>> a loadable module, we run into a link error:
>>
>> drivers/gpu/drm/sun4i/sun4i_drv.o: In function `su
Hi,
On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote:
> Some NM PLLs doesn't work well when their output clock rate is set below
> certain rate.
>
> Add support for that constrain.
In such a case, you should round the rate to the minimum the clock can
operate at, and not return an
https://bugs.freedesktop.org/show_bug.cgi?id=105248
Chris Wilson changed:
What|Removed |Added
Status|NEW |RESOLVED
Assignee|intel-gfx-bu
https://bugs.freedesktop.org/show_bug.cgi?id=105251
Bug ID: 105251
Summary: [Vega10] GPU lockup on boot: VMC page fault
Product: DRI
Version: DRI git
Hardware: Other
OS: Linux (All)
Status: NEW
Severity:
Hi,
On Sat, Feb 24, 2018 at 10:45:38PM +0100, Jernej Skrabec wrote:
> Current polarity configuration code is cleary wrong since it compares
> same flag two times. However, even if flag name is fixed, it won't work
> well for resolutions which have one polarity positive and another
> negative.
>
>
On Mon, Feb 26, 2018 at 5:38 PM, Maxime Ripard
wrote:
> Hi,
>
> On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote:
>> Some NM PLLs doesn't work well when their output clock rate is set below
>> certain rate.
>>
>> Add support for that constrain.
>
> In such a case, you should round th
The adreno driver stopped building when CONFIG_DEBUGFS is disabled:
drivers/gpu/drm/msm/adreno/adreno_device.c: In function 'adreno_load_gpu':
drivers/gpu/drm/msm/adreno/adreno_device.c:153:16: error: 'const struct
msm_gpu_funcs' has no member named 'debugfs_init'
if (gpu->funcs->debugfs_init)
On Thu, 22 Feb 2018, Daniel Thompson wrote:
> On Thu, Feb 22, 2018 at 02:01:16PM +0200, Claudiu Beznea wrote:
>> Add PWM mode to pwm_config() function. The drivers which uses pwm_config()
>> were adapted to this change.
>>
>> Signed-off-by: Claudiu Beznea
>> ---
>> arch/arm/mach-s3c24xx/mach-rx
On 22/02/18 19:07, Jyri Sarha wrote:
> The first patch adds support for drm panels to tilcdc. The second is
> just for convenience. The third adds support for am335x-evm's panel to
> panel-simple driver. The third changes am335x-evm's dts file to use
> panel-simple instead of tilcdc's bundled dpi-p
On Tuesday 20 February 2018 04:44 PM, Archit Taneja wrote:
On Tuesday 20 February 2018 03:59 PM, Thierry Reding wrote:
From: Thierry Reding
DRM_DUMB_VGA_DAC is a user-visible symbol. Selecting it can cause unmet
direct dependencies such as this (on i386, randconfig):
warning: (DRM_PL1
On Mon, Feb 26, 2018 at 05:43:01PM +0800, Chen-Yu Tsai wrote:
> On Mon, Feb 26, 2018 at 5:38 PM, Maxime Ripard
> wrote:
> > Hi,
> >
> > On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote:
> >> Some NM PLLs doesn't work well when their output clock rate is set below
> >> certain rate.
>
On Mon, Feb 26, 2018 at 6:25 PM, Maxime Ripard
wrote:
> On Mon, Feb 26, 2018 at 05:43:01PM +0800, Chen-Yu Tsai wrote:
>> On Mon, Feb 26, 2018 at 5:38 PM, Maxime Ripard
>> wrote:
>> > Hi,
>> >
>> > On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote:
>> >> Some NM PLLs doesn't work well
On Mon, Feb 26, 2018 at 10:31:51AM +0100, Arnd Bergmann wrote:
> On Mon, Feb 26, 2018 at 10:21 AM, Maxime Ripard
> wrote:
> > Hi,
> >
> > On Fri, Feb 23, 2018 at 02:06:52PM +0100, Arnd Bergmann wrote:
> >> When the base sun4i DRM driver is built-in but the back-end is
> >> a loadable module, we ru
On Mon, Feb 26, 2018 at 6:53 PM, Maxime Ripard
wrote:
> On Mon, Feb 26, 2018 at 10:31:51AM +0100, Arnd Bergmann wrote:
>> On Mon, Feb 26, 2018 at 10:21 AM, Maxime Ripard
>> wrote:
>> > Hi,
>> >
>> > On Fri, Feb 23, 2018 at 02:06:52PM +0100, Arnd Bergmann wrote:
>> >> When the base sun4i DRM drive
On Sat, Feb 24, 2018 at 12:31:36AM +0100, Giulio Benetti wrote:
> Il 21/02/2018 10:20, Maxime Ripard ha scritto:
> > From: Maxime Ripard
> >
> > Both TCON clocks are very sensitive to clock changes, since any change
> > might lead to improper timings.
> >
> > Make sure our rate is never changed.
The patch
regmap: mmio: Add function to attach a clock
has been applied to the regmap tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent
https://bugs.freedesktop.org/show_bug.cgi?id=94147
Lukas Wunner changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=105248
Marta Löfstedt changed:
What|Removed |Added
Status|RESOLVED|CLOSED
--- Comment #2 from Marta Löfst
This patch clarifies the adjusted_mode documentation
for a bridge directly connected to a crtc.
Signed-off-by: Philippe Cornu
---
This patch is linked to the discussion https://lkml.org/lkml/2018/1/25/367
include/drm/drm_bridge.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --g
From: Satyajit
Currently while exporting prime handle to fd read write access is
not granted. mmap fails because of this. mmap was not supported on
prime initially.
Here is link to related discussion
https://lists.freedesktop.org/archives/dri-devel/2017-February/131840.html
Adding the DRM_RDWR f
Am 26.02.2018 um 13:37 schrieb Satyajit Sahu:
From: Satyajit
Currently while exporting prime handle to fd read write access is
not granted. mmap fails because of this. mmap was not supported on
prime initially.
Here is link to related discussion
https://lists.freedesktop.org/archives/dri-devel/
I needed this to get -rc0 to compile.
Signed-off-by: Pavel Machek
diff --git a/drivers/video/fbdev/omap2/omapfb/dss/dss.c
b/drivers/video/fbdev/omap2/omapfb/dss/dss.c
index 48c6500..990f1c9 100644
--- a/drivers/video/fbdev/omap2/omapfb/dss/dss.c
+++ b/drivers/video/fbdev/omap2/omapfb/dss/dss.c
On Wed, Feb 21, 2018 at 10:20:25AM +0100, Maxime Ripard wrote:
> From: Maxime Ripard
>
> regmap_init_mmio_clk allows to specify a clock that needs to be enabled
> while accessing the registers.
The following changes since commit 7928b2cbe55b2a410a0f5c1f154610059c57b1b2:
Linux 4.16-rc1 (2018-0
This reverts commit 07ea20d5beb24315b721adf83bbfa72ce016e146.
Unfortunately it turned out that this change broke some corner cases in
Mesa.
Revert it for now, but keep the high range in separate VA managers.
Signed-off-by: Christian König
---
amdgpu/amdgpu_device.c | 28 +++--
Return high addresses if requested and available.
Signed-off-by: Christian König
---
amdgpu/amdgpu.h | 1 +
amdgpu/amdgpu_device.c | 6 --
amdgpu/amdgpu_internal.h | 1 -
amdgpu/amdgpu_vamgr.c| 24 +++-
4 files changed, 24 insertions(+), 8 deletions(-)
https://bugs.freedesktop.org/show_bug.cgi?id=102323
--- Comment #4 from Arvind ---
Hi all,
I think I'm having a similar issue using latest kernel 4.15.5 (on Manjaro).
When resuming from S3, the following stack trace repeats continuously. System
is unresponsive and a hard reset is required. Using
v4.16-rc1 has a fix (b9058afcd6c7).
Tomi
On 26/02/18 15:00, Pavel Machek wrote:
> I needed this to get -rc0 to compile.
>
> Signed-off-by: Pavel Machek
>
>
> diff --git a/drivers/video/fbdev/omap2/omapfb/dss/dss.c
> b/drivers/video/fbdev/omap2/omapfb/dss/dss.c
> index 48c6500..990f1c9 10064
https://bugs.freedesktop.org/show_bug.cgi?id=105254
Bug ID: 105254
Summary: piglit tests/sanity.py fail on ppc, mesa-18.0.0_rc4
Product: Mesa
Version: git
Hardware: PowerPC
OS: All
Status: NEW
Severity: no
https://bugs.freedesktop.org/show_bug.cgi?id=105254
--- Comment #1 from erhar...@mailbox.org ---
Created attachment 137607
--> https://bugs.freedesktop.org/attachment.cgi?id=137607&action=edit
xorg.log
--
You are receiving this mail because:
You are the assignee for the bug.___
https://bugs.freedesktop.org/show_bug.cgi?id=105254
--- Comment #2 from erhar...@mailbox.org ---
Created attachment 137608
--> https://bugs.freedesktop.org/attachment.cgi?id=137608&action=edit
dmesg output
--
You are receiving this mail because:
You are the assignee for the bug.___
From: Ville Syrjälä
sparse complains:
drivers/gpu/drm/drm_panel_orientation_quirks.c:133:5: warning: symbol
'drm_get_panel_orientation_quirk' was not declared. Should it be static?
Cc: Hans de Goede
Cc: Daniel Vetter
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_panel_orientation_qui
Hi,
On 26-02-18 15:24, Ville Syrjala wrote:
From: Ville Syrjälä
sparse complains:
drivers/gpu/drm/drm_panel_orientation_quirks.c:133:5: warning: symbol
'drm_get_panel_orientation_quirk' was not declared. Should it be static?
Cc: Hans de Goede
Cc: Daniel Vetter
Signed-off-by: Ville Syrjälä
Patch f0a8b49c03d2 ("drm/bridge: analogix dp: Fix runtime PM state on
driver bind") fixed unbalanced call to phy_power_on() in analogix_dp_bind()
function by calling phy_power_off() at the end of bind operation.
However it turned out that having PHY powered is required for proper DRM
display pipel
On Wed, Jan 10, 2018 at 02:04:57PM +0100, Daniel Vetter wrote:
> On Fri, Dec 22, 2017 at 09:22:30PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Currently we only check that the plane supports the pixel format of the
> > fb we're about to feed to it. Extend it to check also the mod
Hi Ville,
Thanks for your time for the review and the suggestions.
Please find my comments inline:
On 2/23/2018 7:52 PM, Ville Syrjälä wrote:
On Thu, Feb 15, 2018 at 05:50:58PM +0530, Nautiyal, Ankit K wrote:
From: Ankit Nautiyal
If the user space does not support aspect-ratio, then getbl
Hi Ville,
I agree to all the comments here, and will correct the required things
in the next patch-set.
On 2/23/2018 7:58 PM, Ville Syrjälä wrote:
On Thu, Feb 15, 2018 at 05:50:59PM +0530, Nautiyal, Ankit K wrote:
From: Ankit Nautiyal
If the user-space does not support aspect-ratio, and re
https://bugs.freedesktop.org/show_bug.cgi?id=105163
Eric Engestrom changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On Wed, Feb 21, 2018 at 9:55 AM, Andrzej Hajda wrote:
> OF graph describes MHL data lanes between MHL and respective USB
> connector.
>
> Signed-off-by: Andrzej Hajda
> ---
> v4:
> - added missing reg property in connector's port node (Krzysztof)
> ---
> .../boot/dts/exynos/exynos5433-tm2-common
https://bugs.freedesktop.org/show_bug.cgi?id=105039
--- Comment #3 from Harry Wentland ---
This should be fixed in our staging branches.
Can you try either the amd-staging-drm-next or drm-next-4.17-wip branch from
Alex's repo. You can find it at
https://cgit.freedesktop.org/~agd5f/linux/?h=amd-s
On 2/23/2018 8:06 PM, Ville Syrjälä wrote:
On Thu, Feb 15, 2018 at 05:51:00PM +0530, Nautiyal, Ankit K wrote:
From: Ankit Nautiyal
We parse the EDID and add all the modes in the connector's modelist.
This adds CEA modes with aspect ratio information too, regadless of
whether user space reques
On Fri, Feb 23, 2018 at 01:15:54PM -0500, Rob Clark wrote:
> On Fri, Feb 23, 2018 at 11:30 AM, Sean Paul wrote:
> > On Fri, Feb 23, 2018 at 08:17:54AM -0500, Rob Clark wrote:
> >> In a way, based on the original writeback patch from Jilai Wang, but a
> >> lot has shifted around since then.
> >>
>
On Mon, Feb 26, 2018 at 03:35:34PM +0100, Hans de Goede wrote:
> Hi,
>
> On 26-02-18 15:24, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > sparse complains:
> > drivers/gpu/drm/drm_panel_orientation_quirks.c:133:5: warning: symbol
> > 'drm_get_panel_orientation_quirk' was not declared. Sh
https://bugs.freedesktop.org/show_bug.cgi?id=100919
--- Comment #14 from Thomas R. ---
Harry, I tried amd-staging-drm-next and there is no corruption on the primary,
but my second monitor is dead. It may be something like bug #91202 or something
else entirely, the dmesg output is very sparse (egr
On 2/23/2018 8:24 PM, Ville Syrjälä wrote:
On Thu, Feb 15, 2018 at 05:51:01PM +0530, Nautiyal, Ankit K wrote:
From: "Sharma, Shashank"
Current DRM layer functions don't parse aspect ratio information
while converting a user mode->kernel mode or vice versa. This
causes modeset to pick mode wi
https://bugs.freedesktop.org/show_bug.cgi?id=100919
--- Comment #15 from Harry Wentland ---
Please open a separate ticket for the issue with amd-stg and the 2nd monitor,
including
* dmesg log with amdgpu.dc_log=1 and drm.debug=0x6 kernel options
* model of both monitors and how they're connected
On Mon, Feb 26, 2018 at 09:18:57PM +0530, Nautiyal, Ankit K wrote:
>
>
> On 2/23/2018 8:24 PM, Ville Syrjälä wrote:
> > On Thu, Feb 15, 2018 at 05:51:01PM +0530, Nautiyal, Ankit K wrote:
> >> From: "Sharma, Shashank"
> >>
> >> Current DRM layer functions don't parse aspect ratio information
> >>
This is an attempt to revive the color space conversation that started
here [1] and was materialized with the color encoding and color range
properties for converting YUV2RGB, the last version of this patch
series is here [2].
However, we still need a way of specifing the color gamut and transfer
From: Mihail Atanassov
Export drm_plane_enable_color_mgmt, which attaches the existing degamma,
ctm, and gamma properties to a plane. Add a color_mgmt_changed flag to
drm_plane_state, mimicking the drm_crtc_state flag of the same name.
Signed-off-by: Mihail Atanassov
Signed-off-by: Alexandru Gh
https://bugs.freedesktop.org/show_bug.cgi?id=102323
--- Comment #5 from Harry Wentland ---
Are you able to give Alex's amd-staging-drm-next or drm-next-4.17-wip branch
from https://cgit.freedesktop.org/~agd5f/linux/?h=amd-staging-drm-next a try?
--
You are receiving this mail because:
You are t
On Mon, Feb 26, 2018 at 03:59:21PM +, Alexandru Gheorghe wrote:
> This is an attempt to revive the color space conversation that started
> here [1] and was materialized with the color encoding and color range
> properties for converting YUV2RGB, the last version of this patch
> series is here [
https://bugs.freedesktop.org/show_bug.cgi?id=105244
--- Comment #1 from Alex Deucher ---
Created attachment 137609
--> https://bugs.freedesktop.org/attachment.cgi?id=137609&action=edit
possible fix
This patch should fix it.
--
You are receiving this mail because:
You are the assignee for the
https://bugzilla.kernel.org/show_bug.cgi?id=198883
--- Comment #22 from Andrey Grodzovsky (andrey.grodzov...@amd.com) ---
I tried cold resets around 15 times (taking out the power cord) running lightdm
manger or directly xinit and haven't seen any hang.
Let me know your firmware versions -
cat /
For the series:
Reviewed-by: Marek Olšák
Marek
On Mon, Feb 26, 2018 at 2:16 PM, Christian König
wrote:
> Return high addresses if requested and available.
>
> Signed-off-by: Christian König
> ---
> amdgpu/amdgpu.h | 1 +
> amdgpu/amdgpu_device.c | 6 --
> amdgpu/amdgpu_inter
https://bugs.freedesktop.org/show_bug.cgi?id=104285
--- Comment #8 from Alex Vorobyev ---
I think it's not the same bug. CS:GO works on my system as it should, while SCS
games still have broken shadows.
--
You are receiving this mail because:
You are the assignee for the bug.___
https://bugs.freedesktop.org/show_bug.cgi?id=105256
Bug ID: 105256
Summary: Slow performance using glDrawElementsBaseVertex
Product: Mesa
Version: 17.3
Hardware: Other
OS: Linux (All)
Status: NEW
Severity:
On Mon, Feb 26, 2018 at 06:04:37PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 26, 2018 at 03:59:21PM +, Alexandru Gheorghe wrote:
> > This is an attempt to revive the color space conversation that started
> > here [1] and was materialized with the color encoding and color range
> > properties fo
On 02/15/2018 06:24 PM, Laura Abbott wrote:
> There's no need to print messages each time we alloc and free. Remove them.
>
> Signed-off-by: Laura Abbott
> ---
> tools/testing/selftests/android/ion/ionutils.c | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/tools/testing/selftests/
On 02/19/2018 11:33 AM, Daniel Vetter wrote:
> On Mon, Feb 19, 2018 at 10:18:21AM -0800, Laura Abbott wrote:
>> On 02/19/2018 07:31 AM, Daniel Vetter wrote:
>>> On Thu, Feb 15, 2018 at 05:24:45PM -0800, Laura Abbott wrote:
Ion is designed to be a framework used by other clients who perform
>>>
HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
is enabled. Using the I915 power well infrastruture, above requirement
is verified.
This patch enables the hdcp initialization for HSW, BDW, and BXT.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 31 ++
As per DP spec when R0 mismatch is detected, HDCP source supported
re-read the R0 atleast twice.
And For HDMI and DP minimum wait required for the R0 availability is
100mSec. So this patch changes the wait time to 100mSec but retries
twice with the time interval of 100mSec for each attempt.
DP CT
In case of V prime mismatch, DP HDCP spec mandates the re-read of
Vprime atleast twice.
DP HDCP CTS Test: 1B-05
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/dr
In a connected state, If a HDMI HDCP sink is responded with NACK for
HDCP I2C register access, then HDMI HDCP spec mandates the polling
of any HDCP space registers for accessibility, minimum once in 2Secs
atleast for 4Secs.
Just to make it simple, this is generically implemented for both HDMI
and
This series addresses the requriement of below HDCP compliance tests
DP: 1A-06 and 1B-05
HDMI: 1A-04 and 1A-07a
One of the patch uses the I915 power infra-structure for checking
the power state of PW#1. Which enables the init path for all legacy
platforms.
And encoder specific msg
1 - 100 of 172 matches
Mail list logo
